2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <linux/uaccess.h>
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
37 EXPORT_SYMBOL_GPL(elf_hwcap);
39 #ifdef CONFIG_MIPS_FP_SUPPORT
42 * Get the FPU Implementation/Revision.
44 static inline unsigned long cpu_get_fpu_id(void)
46 unsigned long tmp, fpu_id;
48 tmp = read_c0_status();
49 __enable_fpu(FPU_AS_IS);
50 fpu_id = read_32bit_cp1_register(CP1_REVISION);
56 * Check if the CPU has an external FPU.
58 static inline int __cpu_has_fpu(void)
60 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
64 * Determine the FCSR mask for FPU hardware.
66 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
68 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
71 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
73 sr = read_c0_status();
74 __enable_fpu(FPU_AS_IS);
77 write_32bit_cp1_register(CP1_STATUS, fcsr0);
78 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
81 write_32bit_cp1_register(CP1_STATUS, fcsr1);
82 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
84 write_32bit_cp1_register(CP1_STATUS, fcsr);
88 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
92 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
93 * supported by FPU hardware.
95 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
97 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
98 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
99 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
100 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
102 sr = read_c0_status();
103 __enable_fpu(FPU_AS_IS);
105 fir = read_32bit_cp1_register(CP1_REVISION);
106 if (fir & MIPS_FPIR_HAS2008) {
107 fcsr = read_32bit_cp1_register(CP1_STATUS);
109 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
110 write_32bit_cp1_register(CP1_STATUS, fcsr0);
111 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
113 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
114 write_32bit_cp1_register(CP1_STATUS, fcsr1);
115 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
117 write_32bit_cp1_register(CP1_STATUS, fcsr);
119 if (!(fcsr0 & FPU_CSR_NAN2008))
120 c->options |= MIPS_CPU_NAN_LEGACY;
121 if (fcsr1 & FPU_CSR_NAN2008)
122 c->options |= MIPS_CPU_NAN_2008;
124 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
125 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
127 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
129 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
130 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
132 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
134 c->options |= MIPS_CPU_NAN_LEGACY;
139 c->options |= MIPS_CPU_NAN_LEGACY;
144 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
145 * ABS.fmt/NEG.fmt execution mode.
147 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
150 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
151 * to support by the FPU emulator according to the IEEE 754 conformance
152 * mode selected. Note that "relaxed" straps the emulator so that it
153 * allows 2008-NaN binaries even for legacy processors.
155 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
157 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
158 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
159 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
163 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
164 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
165 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
166 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
168 c->options |= MIPS_CPU_NAN_LEGACY;
169 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
173 c->options |= MIPS_CPU_NAN_LEGACY;
174 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
177 c->options |= MIPS_CPU_NAN_2008;
178 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
182 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
188 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
189 * according to the "ieee754=" parameter.
191 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
195 mips_use_nan_legacy = !!cpu_has_nan_legacy;
196 mips_use_nan_2008 = !!cpu_has_nan_2008;
199 mips_use_nan_legacy = !!cpu_has_nan_legacy;
200 mips_use_nan_2008 = !cpu_has_nan_legacy;
203 mips_use_nan_legacy = !cpu_has_nan_2008;
204 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 mips_use_nan_legacy = true;
208 mips_use_nan_2008 = true;
214 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
217 * strict: accept binaries that request a NaN encoding supported by the FPU
218 * legacy: only accept legacy-NaN binaries
219 * 2008: only accept 2008-NaN binaries
220 * relaxed: accept any binaries regardless of whether supported by the FPU
222 static int __init ieee754_setup(char *s)
226 else if (!strcmp(s, "strict"))
228 else if (!strcmp(s, "legacy"))
230 else if (!strcmp(s, "2008"))
232 else if (!strcmp(s, "relaxed"))
237 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
238 cpu_set_nofpu_2008(&boot_cpu_data);
239 cpu_set_nan_2008(&boot_cpu_data);
244 early_param("ieee754", ieee754_setup);
247 * Set the FIR feature flags for the FPU emulator.
249 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
254 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
255 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
256 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
257 value |= MIPS_FPIR_D | MIPS_FPIR_S;
258 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
259 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
260 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
261 if (c->options & MIPS_CPU_NAN_2008)
262 value |= MIPS_FPIR_HAS2008;
266 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
267 static unsigned int mips_nofpu_msk31;
270 * Set options for FPU hardware.
272 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
274 c->fpu_id = cpu_get_fpu_id();
275 mips_nofpu_msk31 = c->fpu_msk31;
277 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
278 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
279 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
280 if (c->fpu_id & MIPS_FPIR_3D)
281 c->ases |= MIPS_ASE_MIPS3D;
282 if (c->fpu_id & MIPS_FPIR_UFRP)
283 c->options |= MIPS_CPU_UFR;
284 if (c->fpu_id & MIPS_FPIR_FREP)
285 c->options |= MIPS_CPU_FRE;
288 cpu_set_fpu_fcsr_mask(c);
294 * Set options for the FPU emulator.
296 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
298 c->options &= ~MIPS_CPU_FPU;
299 c->fpu_msk31 = mips_nofpu_msk31;
301 cpu_set_nofpu_2008(c);
306 static int mips_fpu_disabled;
308 static int __init fpu_disable(char *s)
310 cpu_set_nofpu_opts(&boot_cpu_data);
311 mips_fpu_disabled = 1;
316 __setup("nofpu", fpu_disable);
318 #else /* !CONFIG_MIPS_FP_SUPPORT */
320 #define mips_fpu_disabled 1
322 static inline unsigned long cpu_get_fpu_id(void)
324 return FPIR_IMP_NONE;
327 static inline int __cpu_has_fpu(void)
332 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
337 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
342 #endif /* CONFIG_MIPS_FP_SUPPORT */
344 static inline unsigned long cpu_get_msa_id(void)
346 unsigned long status, msa_id;
348 status = read_c0_status();
349 __enable_fpu(FPU_64BIT);
351 msa_id = read_msa_ir();
353 write_c0_status(status);
357 static int mips_dsp_disabled;
359 static int __init dsp_disable(char *s)
361 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
362 mips_dsp_disabled = 1;
367 __setup("nodsp", dsp_disable);
369 static int mips_htw_disabled;
371 static int __init htw_disable(char *s)
373 mips_htw_disabled = 1;
374 cpu_data[0].options &= ~MIPS_CPU_HTW;
375 write_c0_pwctl(read_c0_pwctl() &
376 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
381 __setup("nohtw", htw_disable);
383 static int mips_ftlb_disabled;
384 static int mips_has_ftlb_configured;
388 FTLB_SET_PROB = 1 << 1,
391 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
393 static int __init ftlb_disable(char *s)
395 unsigned int config4, mmuextdef;
398 * If the core hasn't done any FTLB configuration, there is nothing
401 if (!mips_has_ftlb_configured)
404 /* Disable it in the boot cpu */
405 if (set_ftlb_enable(&cpu_data[0], 0)) {
406 pr_warn("Can't turn FTLB off\n");
410 config4 = read_c0_config4();
412 /* Check that FTLB has been disabled */
413 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
414 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
415 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
416 /* This should never happen */
417 pr_warn("FTLB could not be disabled!\n");
421 mips_ftlb_disabled = 1;
422 mips_has_ftlb_configured = 0;
425 * noftlb is mainly used for debug purposes so print
426 * an informative message instead of using pr_debug()
428 pr_info("FTLB has been disabled\n");
431 * Some of these bits are duplicated in the decode_config4.
432 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
433 * once FTLB has been disabled so undo what decode_config4 did.
435 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
436 cpu_data[0].tlbsizeftlbsets;
437 cpu_data[0].tlbsizeftlbsets = 0;
438 cpu_data[0].tlbsizeftlbways = 0;
443 __setup("noftlb", ftlb_disable);
446 * Check if the CPU has per tc perf counters
448 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
450 if (read_c0_config7() & MTI_CONF7_PTC)
451 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
454 static inline void check_errata(void)
456 struct cpuinfo_mips *c = ¤t_cpu_data;
458 switch (current_cpu_type()) {
461 * Erratum "RPS May Cause Incorrect Instruction Execution"
462 * This code only handles VPE0, any SMP/RTOS code
463 * making use of VPE1 will be responsable for that VPE.
465 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
466 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
473 void __init check_bugs32(void)
479 * Probe whether cpu has config register by trying to play with
480 * alternate cache bit and see whether it matters.
481 * It's used by cpu_probe to distinguish between R3000A and R3081.
483 static inline int cpu_has_confreg(void)
485 #ifdef CONFIG_CPU_R3000
486 extern unsigned long r3k_cache_size(unsigned long);
487 unsigned long size1, size2;
488 unsigned long cfg = read_c0_conf();
490 size1 = r3k_cache_size(ST0_ISC);
491 write_c0_conf(cfg ^ R30XX_CONF_AC);
492 size2 = r3k_cache_size(ST0_ISC);
494 return size1 != size2;
500 static inline void set_elf_platform(int cpu, const char *plat)
503 __elf_platform = plat;
506 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
508 #ifdef __NEED_VMBITS_PROBE
509 write_c0_entryhi(0x3fffffffffffe000ULL);
510 back_to_back_c0_hazard();
511 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
515 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
518 case MIPS_CPU_ISA_M64R2:
519 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
521 case MIPS_CPU_ISA_M64R1:
522 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
525 c->isa_level |= MIPS_CPU_ISA_V;
527 case MIPS_CPU_ISA_IV:
528 c->isa_level |= MIPS_CPU_ISA_IV;
530 case MIPS_CPU_ISA_III:
531 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
534 /* R6 incompatible with everything else */
535 case MIPS_CPU_ISA_M64R6:
536 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
538 case MIPS_CPU_ISA_M32R6:
539 c->isa_level |= MIPS_CPU_ISA_M32R6;
540 /* Break here so we don't add incompatible ISAs */
542 case MIPS_CPU_ISA_M32R2:
543 c->isa_level |= MIPS_CPU_ISA_M32R2;
545 case MIPS_CPU_ISA_M32R1:
546 c->isa_level |= MIPS_CPU_ISA_M32R1;
548 case MIPS_CPU_ISA_II:
549 c->isa_level |= MIPS_CPU_ISA_II;
554 static char unknown_isa[] = KERN_ERR \
555 "Unsupported ISA type, c0.config0: %d.";
557 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
560 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
563 * 0 = All TLBWR instructions go to FTLB
564 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
565 * FTLB and 1 goes to the VTLB.
566 * 2 = 7:1: As above with 7:1 ratio.
567 * 3 = 3:1: As above with 3:1 ratio.
569 * Use the linear midpoint as the probability threshold.
571 if (probability >= 12)
573 else if (probability >= 6)
577 * So FTLB is less than 4 times bigger than VTLB.
578 * A 3:1 ratio can still be useful though.
583 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
587 /* It's implementation dependent how the FTLB can be enabled */
588 switch (c->cputype) {
592 /* proAptiv & related cores use Config6 to enable the FTLB */
593 config = read_c0_config6();
596 config |= MIPS_CONF6_FTLBEN;
598 config &= ~MIPS_CONF6_FTLBEN;
600 if (flags & FTLB_SET_PROB) {
601 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
602 config |= calculate_ftlb_probability(c)
603 << MIPS_CONF6_FTLBP_SHIFT;
606 write_c0_config6(config);
607 back_to_back_c0_hazard();
611 /* There's no way to disable the FTLB */
612 if (!(flags & FTLB_EN))
616 /* Flush ITLB, DTLB, VTLB and FTLB */
617 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
618 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
619 /* Loongson-3 cores use Config6 to enable the FTLB */
620 config = read_c0_config6();
623 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
626 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
635 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
637 unsigned int config0;
640 config0 = read_c0_config();
643 * Look for Standard TLB or Dual VTLB and FTLB
645 mt = config0 & MIPS_CONF_MT;
646 if (mt == MIPS_CONF_MT_TLB)
647 c->options |= MIPS_CPU_TLB;
648 else if (mt == MIPS_CONF_MT_FTLB)
649 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
651 isa = (config0 & MIPS_CONF_AT) >> 13;
654 switch ((config0 & MIPS_CONF_AR) >> 10) {
656 set_isa(c, MIPS_CPU_ISA_M32R1);
659 set_isa(c, MIPS_CPU_ISA_M32R2);
662 set_isa(c, MIPS_CPU_ISA_M32R6);
669 switch ((config0 & MIPS_CONF_AR) >> 10) {
671 set_isa(c, MIPS_CPU_ISA_M64R1);
674 set_isa(c, MIPS_CPU_ISA_M64R2);
677 set_isa(c, MIPS_CPU_ISA_M64R6);
687 return config0 & MIPS_CONF_M;
690 panic(unknown_isa, config0);
693 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
695 unsigned int config1;
697 config1 = read_c0_config1();
699 if (config1 & MIPS_CONF1_MD)
700 c->ases |= MIPS_ASE_MDMX;
701 if (config1 & MIPS_CONF1_PC)
702 c->options |= MIPS_CPU_PERF;
703 if (config1 & MIPS_CONF1_WR)
704 c->options |= MIPS_CPU_WATCH;
705 if (config1 & MIPS_CONF1_CA)
706 c->ases |= MIPS_ASE_MIPS16;
707 if (config1 & MIPS_CONF1_EP)
708 c->options |= MIPS_CPU_EJTAG;
709 if (config1 & MIPS_CONF1_FP) {
710 c->options |= MIPS_CPU_FPU;
711 c->options |= MIPS_CPU_32FPR;
714 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
715 c->tlbsizevtlb = c->tlbsize;
716 c->tlbsizeftlbsets = 0;
719 return config1 & MIPS_CONF_M;
722 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
724 unsigned int config2;
726 config2 = read_c0_config2();
728 if (config2 & MIPS_CONF2_SL)
729 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
731 return config2 & MIPS_CONF_M;
734 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
736 unsigned int config3;
738 config3 = read_c0_config3();
740 if (config3 & MIPS_CONF3_SM) {
741 c->ases |= MIPS_ASE_SMARTMIPS;
742 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
744 if (config3 & MIPS_CONF3_RXI)
745 c->options |= MIPS_CPU_RIXI;
746 if (config3 & MIPS_CONF3_CTXTC)
747 c->options |= MIPS_CPU_CTXTC;
748 if (config3 & MIPS_CONF3_DSP)
749 c->ases |= MIPS_ASE_DSP;
750 if (config3 & MIPS_CONF3_DSP2P) {
751 c->ases |= MIPS_ASE_DSP2P;
753 c->ases |= MIPS_ASE_DSP3;
755 if (config3 & MIPS_CONF3_VINT)
756 c->options |= MIPS_CPU_VINT;
757 if (config3 & MIPS_CONF3_VEIC)
758 c->options |= MIPS_CPU_VEIC;
759 if (config3 & MIPS_CONF3_LPA)
760 c->options |= MIPS_CPU_LPA;
761 if (config3 & MIPS_CONF3_MT)
762 c->ases |= MIPS_ASE_MIPSMT;
763 if (config3 & MIPS_CONF3_ULRI)
764 c->options |= MIPS_CPU_ULRI;
765 if (config3 & MIPS_CONF3_ISA)
766 c->options |= MIPS_CPU_MICROMIPS;
767 if (config3 & MIPS_CONF3_VZ)
768 c->ases |= MIPS_ASE_VZ;
769 if (config3 & MIPS_CONF3_SC)
770 c->options |= MIPS_CPU_SEGMENTS;
771 if (config3 & MIPS_CONF3_BI)
772 c->options |= MIPS_CPU_BADINSTR;
773 if (config3 & MIPS_CONF3_BP)
774 c->options |= MIPS_CPU_BADINSTRP;
775 if (config3 & MIPS_CONF3_MSA)
776 c->ases |= MIPS_ASE_MSA;
777 if (config3 & MIPS_CONF3_PW) {
779 c->options |= MIPS_CPU_HTW;
781 if (config3 & MIPS_CONF3_CDMM)
782 c->options |= MIPS_CPU_CDMM;
783 if (config3 & MIPS_CONF3_SP)
784 c->options |= MIPS_CPU_SP;
786 return config3 & MIPS_CONF_M;
789 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
791 unsigned int config4;
793 unsigned int mmuextdef;
794 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
795 unsigned long asid_mask;
797 config4 = read_c0_config4();
800 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
801 c->options |= MIPS_CPU_TLBINV;
804 * R6 has dropped the MMUExtDef field from config4.
805 * On R6 the fields always describe the FTLB, and only if it is
806 * present according to Config.MT.
808 if (!cpu_has_mips_r6)
809 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
810 else if (cpu_has_ftlb)
811 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
816 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
817 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
818 c->tlbsizevtlb = c->tlbsize;
820 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
822 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
823 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
824 c->tlbsize = c->tlbsizevtlb;
825 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
827 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
828 if (mips_ftlb_disabled)
830 newcf4 = (config4 & ~ftlb_page) |
831 (page_size_ftlb(mmuextdef) <<
832 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
833 write_c0_config4(newcf4);
834 back_to_back_c0_hazard();
835 config4 = read_c0_config4();
836 if (config4 != newcf4) {
837 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
839 /* Switch FTLB off */
840 set_ftlb_enable(c, 0);
841 mips_ftlb_disabled = 1;
844 c->tlbsizeftlbsets = 1 <<
845 ((config4 & MIPS_CONF4_FTLBSETS) >>
846 MIPS_CONF4_FTLBSETS_SHIFT);
847 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
848 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
849 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
850 mips_has_ftlb_configured = 1;
855 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
856 >> MIPS_CONF4_KSCREXIST_SHIFT;
858 asid_mask = MIPS_ENTRYHI_ASID;
859 if (config4 & MIPS_CONF4_AE)
860 asid_mask |= MIPS_ENTRYHI_ASIDX;
861 set_cpu_asid_mask(c, asid_mask);
864 * Warn if the computed ASID mask doesn't match the mask the kernel
865 * is built for. This may indicate either a serious problem or an
866 * easy optimisation opportunity, but either way should be addressed.
868 WARN_ON(asid_mask != cpu_asid_mask(c));
870 return config4 & MIPS_CONF_M;
873 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
875 unsigned int config5;
877 config5 = read_c0_config5();
878 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
879 write_c0_config5(config5);
881 if (config5 & MIPS_CONF5_EVA)
882 c->options |= MIPS_CPU_EVA;
883 if (config5 & MIPS_CONF5_MRP)
884 c->options |= MIPS_CPU_MAAR;
885 if (config5 & MIPS_CONF5_LLB)
886 c->options |= MIPS_CPU_RW_LLB;
887 if (config5 & MIPS_CONF5_MVH)
888 c->options |= MIPS_CPU_MVH;
889 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
890 c->options |= MIPS_CPU_VP;
891 if (config5 & MIPS_CONF5_CA2)
892 c->ases |= MIPS_ASE_MIPS16E2;
894 if (config5 & MIPS_CONF5_CRCP)
895 elf_hwcap |= HWCAP_MIPS_CRC32;
897 return config5 & MIPS_CONF_M;
900 static void decode_configs(struct cpuinfo_mips *c)
904 /* MIPS32 or MIPS64 compliant CPU. */
905 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
906 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
908 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
910 /* Enable FTLB if present and not disabled */
911 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
913 ok = decode_config0(c); /* Read Config registers. */
914 BUG_ON(!ok); /* Arch spec violation! */
916 ok = decode_config1(c);
918 ok = decode_config2(c);
920 ok = decode_config3(c);
922 ok = decode_config4(c);
924 ok = decode_config5(c);
926 /* Probe the EBase.WG bit */
927 if (cpu_has_mips_r2_r6) {
931 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
932 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
933 : (s32)read_c0_ebase();
934 if (ebase & MIPS_EBASE_WG) {
935 /* WG bit already set, we can avoid the clumsy probe */
936 c->options |= MIPS_CPU_EBASE_WG;
938 /* Its UNDEFINED to change EBase while BEV=0 */
939 status = read_c0_status();
940 write_c0_status(status | ST0_BEV);
943 * On pre-r6 cores, this may well clobber the upper bits
944 * of EBase. This is hard to avoid without potentially
945 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
947 if (cpu_has_mips64r6)
948 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
950 write_c0_ebase(ebase | MIPS_EBASE_WG);
951 back_to_back_c0_hazard();
953 write_c0_status(status);
954 if (read_c0_ebase() & MIPS_EBASE_WG) {
955 c->options |= MIPS_CPU_EBASE_WG;
956 write_c0_ebase(ebase);
961 /* configure the FTLB write probability */
962 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
964 mips_probe_watch_registers(c);
966 #ifndef CONFIG_MIPS_CPS
967 if (cpu_has_mips_r2_r6) {
970 core = get_ebase_cpunum();
972 core >>= fls(core_nvpes()) - 1;
973 cpu_set_core(c, core);
979 * Probe for certain guest capabilities by writing config bits and reading back.
980 * Finally write back the original value.
982 #define probe_gc0_config(name, maxconf, bits) \
985 tmp = read_gc0_##name(); \
986 write_gc0_##name(tmp | (bits)); \
987 back_to_back_c0_hazard(); \
988 maxconf = read_gc0_##name(); \
989 write_gc0_##name(tmp); \
993 * Probe for dynamic guest capabilities by changing certain config bits and
994 * reading back to see if they change. Finally write back the original value.
996 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
998 maxconf = read_gc0_##name(); \
999 write_gc0_##name(maxconf ^ (bits)); \
1000 back_to_back_c0_hazard(); \
1001 dynconf = maxconf ^ read_gc0_##name(); \
1002 write_gc0_##name(maxconf); \
1003 maxconf |= dynconf; \
1006 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1008 unsigned int config0;
1010 probe_gc0_config(config, config0, MIPS_CONF_M);
1012 if (config0 & MIPS_CONF_M)
1013 c->guest.conf |= BIT(1);
1014 return config0 & MIPS_CONF_M;
1017 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1019 unsigned int config1, config1_dyn;
1021 probe_gc0_config_dyn(config1, config1, config1_dyn,
1022 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1025 if (config1 & MIPS_CONF1_FP)
1026 c->guest.options |= MIPS_CPU_FPU;
1027 if (config1_dyn & MIPS_CONF1_FP)
1028 c->guest.options_dyn |= MIPS_CPU_FPU;
1030 if (config1 & MIPS_CONF1_WR)
1031 c->guest.options |= MIPS_CPU_WATCH;
1032 if (config1_dyn & MIPS_CONF1_WR)
1033 c->guest.options_dyn |= MIPS_CPU_WATCH;
1035 if (config1 & MIPS_CONF1_PC)
1036 c->guest.options |= MIPS_CPU_PERF;
1037 if (config1_dyn & MIPS_CONF1_PC)
1038 c->guest.options_dyn |= MIPS_CPU_PERF;
1040 if (config1 & MIPS_CONF_M)
1041 c->guest.conf |= BIT(2);
1042 return config1 & MIPS_CONF_M;
1045 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1047 unsigned int config2;
1049 probe_gc0_config(config2, config2, MIPS_CONF_M);
1051 if (config2 & MIPS_CONF_M)
1052 c->guest.conf |= BIT(3);
1053 return config2 & MIPS_CONF_M;
1056 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1058 unsigned int config3, config3_dyn;
1060 probe_gc0_config_dyn(config3, config3, config3_dyn,
1061 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1064 if (config3 & MIPS_CONF3_CTXTC)
1065 c->guest.options |= MIPS_CPU_CTXTC;
1066 if (config3_dyn & MIPS_CONF3_CTXTC)
1067 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1069 if (config3 & MIPS_CONF3_PW)
1070 c->guest.options |= MIPS_CPU_HTW;
1072 if (config3 & MIPS_CONF3_ULRI)
1073 c->guest.options |= MIPS_CPU_ULRI;
1075 if (config3 & MIPS_CONF3_SC)
1076 c->guest.options |= MIPS_CPU_SEGMENTS;
1078 if (config3 & MIPS_CONF3_BI)
1079 c->guest.options |= MIPS_CPU_BADINSTR;
1080 if (config3 & MIPS_CONF3_BP)
1081 c->guest.options |= MIPS_CPU_BADINSTRP;
1083 if (config3 & MIPS_CONF3_MSA)
1084 c->guest.ases |= MIPS_ASE_MSA;
1085 if (config3_dyn & MIPS_CONF3_MSA)
1086 c->guest.ases_dyn |= MIPS_ASE_MSA;
1088 if (config3 & MIPS_CONF_M)
1089 c->guest.conf |= BIT(4);
1090 return config3 & MIPS_CONF_M;
1093 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1095 unsigned int config4;
1097 probe_gc0_config(config4, config4,
1098 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1100 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1101 >> MIPS_CONF4_KSCREXIST_SHIFT;
1103 if (config4 & MIPS_CONF_M)
1104 c->guest.conf |= BIT(5);
1105 return config4 & MIPS_CONF_M;
1108 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1110 unsigned int config5, config5_dyn;
1112 probe_gc0_config_dyn(config5, config5, config5_dyn,
1113 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1115 if (config5 & MIPS_CONF5_MRP)
1116 c->guest.options |= MIPS_CPU_MAAR;
1117 if (config5_dyn & MIPS_CONF5_MRP)
1118 c->guest.options_dyn |= MIPS_CPU_MAAR;
1120 if (config5 & MIPS_CONF5_LLB)
1121 c->guest.options |= MIPS_CPU_RW_LLB;
1123 if (config5 & MIPS_CONF5_MVH)
1124 c->guest.options |= MIPS_CPU_MVH;
1126 if (config5 & MIPS_CONF_M)
1127 c->guest.conf |= BIT(6);
1128 return config5 & MIPS_CONF_M;
1131 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1135 ok = decode_guest_config0(c);
1137 ok = decode_guest_config1(c);
1139 ok = decode_guest_config2(c);
1141 ok = decode_guest_config3(c);
1143 ok = decode_guest_config4(c);
1145 decode_guest_config5(c);
1148 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1150 unsigned int guestctl0, temp;
1152 guestctl0 = read_c0_guestctl0();
1154 if (guestctl0 & MIPS_GCTL0_G0E)
1155 c->options |= MIPS_CPU_GUESTCTL0EXT;
1156 if (guestctl0 & MIPS_GCTL0_G1)
1157 c->options |= MIPS_CPU_GUESTCTL1;
1158 if (guestctl0 & MIPS_GCTL0_G2)
1159 c->options |= MIPS_CPU_GUESTCTL2;
1160 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1161 c->options |= MIPS_CPU_GUESTID;
1164 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1165 * first, otherwise all data accesses will be fully virtualised
1166 * as if they were performed by guest mode.
1168 write_c0_guestctl1(0);
1171 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1172 back_to_back_c0_hazard();
1173 temp = read_c0_guestctl0();
1175 if (temp & MIPS_GCTL0_DRG) {
1176 write_c0_guestctl0(guestctl0);
1177 c->options |= MIPS_CPU_DRG;
1182 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1184 if (cpu_has_guestid) {
1185 /* determine the number of bits of GuestID available */
1186 write_c0_guestctl1(MIPS_GCTL1_ID);
1187 back_to_back_c0_hazard();
1188 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1189 >> MIPS_GCTL1_ID_SHIFT;
1190 write_c0_guestctl1(0);
1194 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1196 /* determine the number of bits of GTOffset available */
1197 write_c0_gtoffset(0xffffffff);
1198 back_to_back_c0_hazard();
1199 c->gtoffset_mask = read_c0_gtoffset();
1200 write_c0_gtoffset(0);
1203 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1205 cpu_probe_guestctl0(c);
1206 if (cpu_has_guestctl1)
1207 cpu_probe_guestctl1(c);
1209 cpu_probe_gtoffset(c);
1211 decode_guest_configs(c);
1214 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1217 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1219 switch (c->processor_id & PRID_IMP_MASK) {
1220 case PRID_IMP_R2000:
1221 c->cputype = CPU_R2000;
1222 __cpu_name[cpu] = "R2000";
1223 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1224 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1226 if (__cpu_has_fpu())
1227 c->options |= MIPS_CPU_FPU;
1230 case PRID_IMP_R3000:
1231 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1232 if (cpu_has_confreg()) {
1233 c->cputype = CPU_R3081E;
1234 __cpu_name[cpu] = "R3081";
1236 c->cputype = CPU_R3000A;
1237 __cpu_name[cpu] = "R3000A";
1240 c->cputype = CPU_R3000;
1241 __cpu_name[cpu] = "R3000";
1243 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1244 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1246 if (__cpu_has_fpu())
1247 c->options |= MIPS_CPU_FPU;
1250 case PRID_IMP_R4000:
1251 if (read_c0_config() & CONF_SC) {
1252 if ((c->processor_id & PRID_REV_MASK) >=
1254 c->cputype = CPU_R4400PC;
1255 __cpu_name[cpu] = "R4400PC";
1257 c->cputype = CPU_R4000PC;
1258 __cpu_name[cpu] = "R4000PC";
1261 int cca = read_c0_config() & CONF_CM_CMASK;
1265 * SC and MC versions can't be reliably told apart,
1266 * but only the latter support coherent caching
1267 * modes so assume the firmware has set the KSEG0
1268 * coherency attribute reasonably (if uncached, we
1272 case CONF_CM_CACHABLE_CE:
1273 case CONF_CM_CACHABLE_COW:
1274 case CONF_CM_CACHABLE_CUW:
1281 if ((c->processor_id & PRID_REV_MASK) >=
1283 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1284 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1286 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1287 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1291 set_isa(c, MIPS_CPU_ISA_III);
1292 c->fpu_msk31 |= FPU_CSR_CONDX;
1293 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1294 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1298 case PRID_IMP_VR41XX:
1299 set_isa(c, MIPS_CPU_ISA_III);
1300 c->fpu_msk31 |= FPU_CSR_CONDX;
1301 c->options = R4K_OPTS;
1303 switch (c->processor_id & 0xf0) {
1304 case PRID_REV_VR4111:
1305 c->cputype = CPU_VR4111;
1306 __cpu_name[cpu] = "NEC VR4111";
1308 case PRID_REV_VR4121:
1309 c->cputype = CPU_VR4121;
1310 __cpu_name[cpu] = "NEC VR4121";
1312 case PRID_REV_VR4122:
1313 if ((c->processor_id & 0xf) < 0x3) {
1314 c->cputype = CPU_VR4122;
1315 __cpu_name[cpu] = "NEC VR4122";
1317 c->cputype = CPU_VR4181A;
1318 __cpu_name[cpu] = "NEC VR4181A";
1321 case PRID_REV_VR4130:
1322 if ((c->processor_id & 0xf) < 0x4) {
1323 c->cputype = CPU_VR4131;
1324 __cpu_name[cpu] = "NEC VR4131";
1326 c->cputype = CPU_VR4133;
1327 c->options |= MIPS_CPU_LLSC;
1328 __cpu_name[cpu] = "NEC VR4133";
1332 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1333 c->cputype = CPU_VR41XX;
1334 __cpu_name[cpu] = "NEC Vr41xx";
1338 case PRID_IMP_R4300:
1339 c->cputype = CPU_R4300;
1340 __cpu_name[cpu] = "R4300";
1341 set_isa(c, MIPS_CPU_ISA_III);
1342 c->fpu_msk31 |= FPU_CSR_CONDX;
1343 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1347 case PRID_IMP_R4600:
1348 c->cputype = CPU_R4600;
1349 __cpu_name[cpu] = "R4600";
1350 set_isa(c, MIPS_CPU_ISA_III);
1351 c->fpu_msk31 |= FPU_CSR_CONDX;
1352 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1357 case PRID_IMP_R4650:
1359 * This processor doesn't have an MMU, so it's not
1360 * "real easy" to run Linux on it. It is left purely
1361 * for documentation. Commented out because it shares
1362 * it's c0_prid id number with the TX3900.
1364 c->cputype = CPU_R4650;
1365 __cpu_name[cpu] = "R4650";
1366 set_isa(c, MIPS_CPU_ISA_III);
1367 c->fpu_msk31 |= FPU_CSR_CONDX;
1368 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1373 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1374 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1376 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1377 c->cputype = CPU_TX3927;
1378 __cpu_name[cpu] = "TX3927";
1381 switch (c->processor_id & PRID_REV_MASK) {
1382 case PRID_REV_TX3912:
1383 c->cputype = CPU_TX3912;
1384 __cpu_name[cpu] = "TX3912";
1387 case PRID_REV_TX3922:
1388 c->cputype = CPU_TX3922;
1389 __cpu_name[cpu] = "TX3922";
1395 case PRID_IMP_R4700:
1396 c->cputype = CPU_R4700;
1397 __cpu_name[cpu] = "R4700";
1398 set_isa(c, MIPS_CPU_ISA_III);
1399 c->fpu_msk31 |= FPU_CSR_CONDX;
1400 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1405 c->cputype = CPU_TX49XX;
1406 __cpu_name[cpu] = "R49XX";
1407 set_isa(c, MIPS_CPU_ISA_III);
1408 c->fpu_msk31 |= FPU_CSR_CONDX;
1409 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1410 if (!(c->processor_id & 0x08))
1411 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1414 case PRID_IMP_R5000:
1415 c->cputype = CPU_R5000;
1416 __cpu_name[cpu] = "R5000";
1417 set_isa(c, MIPS_CPU_ISA_IV);
1418 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1422 case PRID_IMP_R5432:
1423 c->cputype = CPU_R5432;
1424 __cpu_name[cpu] = "R5432";
1425 set_isa(c, MIPS_CPU_ISA_IV);
1426 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1427 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1430 case PRID_IMP_R5500:
1431 c->cputype = CPU_R5500;
1432 __cpu_name[cpu] = "R5500";
1433 set_isa(c, MIPS_CPU_ISA_IV);
1434 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1435 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1438 case PRID_IMP_NEVADA:
1439 c->cputype = CPU_NEVADA;
1440 __cpu_name[cpu] = "Nevada";
1441 set_isa(c, MIPS_CPU_ISA_IV);
1442 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1443 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1446 case PRID_IMP_RM7000:
1447 c->cputype = CPU_RM7000;
1448 __cpu_name[cpu] = "RM7000";
1449 set_isa(c, MIPS_CPU_ISA_IV);
1450 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1453 * Undocumented RM7000: Bit 29 in the info register of
1454 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1457 * 29 1 => 64 entry JTLB
1458 * 0 => 48 entry JTLB
1460 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1462 case PRID_IMP_R8000:
1463 c->cputype = CPU_R8000;
1464 __cpu_name[cpu] = "RM8000";
1465 set_isa(c, MIPS_CPU_ISA_IV);
1466 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1467 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1469 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1471 case PRID_IMP_R10000:
1472 c->cputype = CPU_R10000;
1473 __cpu_name[cpu] = "R10000";
1474 set_isa(c, MIPS_CPU_ISA_IV);
1475 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1476 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1477 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1481 case PRID_IMP_R12000:
1482 c->cputype = CPU_R12000;
1483 __cpu_name[cpu] = "R12000";
1484 set_isa(c, MIPS_CPU_ISA_IV);
1485 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1486 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1487 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1488 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1491 case PRID_IMP_R14000:
1492 if (((c->processor_id >> 4) & 0x0f) > 2) {
1493 c->cputype = CPU_R16000;
1494 __cpu_name[cpu] = "R16000";
1496 c->cputype = CPU_R14000;
1497 __cpu_name[cpu] = "R14000";
1499 set_isa(c, MIPS_CPU_ISA_IV);
1500 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1501 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1502 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1503 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1506 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1507 switch (c->processor_id & PRID_REV_MASK) {
1508 case PRID_REV_LOONGSON2E:
1509 c->cputype = CPU_LOONGSON2;
1510 __cpu_name[cpu] = "ICT Loongson-2";
1511 set_elf_platform(cpu, "loongson2e");
1512 set_isa(c, MIPS_CPU_ISA_III);
1513 c->fpu_msk31 |= FPU_CSR_CONDX;
1515 case PRID_REV_LOONGSON2F:
1516 c->cputype = CPU_LOONGSON2;
1517 __cpu_name[cpu] = "ICT Loongson-2";
1518 set_elf_platform(cpu, "loongson2f");
1519 set_isa(c, MIPS_CPU_ISA_III);
1520 c->fpu_msk31 |= FPU_CSR_CONDX;
1522 case PRID_REV_LOONGSON3A_R1:
1523 c->cputype = CPU_LOONGSON3;
1524 __cpu_name[cpu] = "ICT Loongson-3";
1525 set_elf_platform(cpu, "loongson3a");
1526 set_isa(c, MIPS_CPU_ISA_M64R1);
1528 case PRID_REV_LOONGSON3B_R1:
1529 case PRID_REV_LOONGSON3B_R2:
1530 c->cputype = CPU_LOONGSON3;
1531 __cpu_name[cpu] = "ICT Loongson-3";
1532 set_elf_platform(cpu, "loongson3b");
1533 set_isa(c, MIPS_CPU_ISA_M64R1);
1537 c->options = R4K_OPTS |
1538 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1541 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1543 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1546 c->cputype = CPU_LOONGSON1;
1548 switch (c->processor_id & PRID_REV_MASK) {
1549 case PRID_REV_LOONGSON1B:
1550 __cpu_name[cpu] = "Loongson 1B";
1558 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1560 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1561 switch (c->processor_id & PRID_IMP_MASK) {
1562 case PRID_IMP_QEMU_GENERIC:
1563 c->writecombine = _CACHE_UNCACHED;
1564 c->cputype = CPU_QEMU_GENERIC;
1565 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1568 c->cputype = CPU_4KC;
1569 c->writecombine = _CACHE_UNCACHED;
1570 __cpu_name[cpu] = "MIPS 4Kc";
1573 case PRID_IMP_4KECR2:
1574 c->cputype = CPU_4KEC;
1575 c->writecombine = _CACHE_UNCACHED;
1576 __cpu_name[cpu] = "MIPS 4KEc";
1580 c->cputype = CPU_4KSC;
1581 c->writecombine = _CACHE_UNCACHED;
1582 __cpu_name[cpu] = "MIPS 4KSc";
1585 c->cputype = CPU_5KC;
1586 c->writecombine = _CACHE_UNCACHED;
1587 __cpu_name[cpu] = "MIPS 5Kc";
1590 c->cputype = CPU_5KE;
1591 c->writecombine = _CACHE_UNCACHED;
1592 __cpu_name[cpu] = "MIPS 5KE";
1595 c->cputype = CPU_20KC;
1596 c->writecombine = _CACHE_UNCACHED;
1597 __cpu_name[cpu] = "MIPS 20Kc";
1600 c->cputype = CPU_24K;
1601 c->writecombine = _CACHE_UNCACHED;
1602 __cpu_name[cpu] = "MIPS 24Kc";
1605 c->cputype = CPU_24K;
1606 c->writecombine = _CACHE_UNCACHED;
1607 __cpu_name[cpu] = "MIPS 24KEc";
1610 c->cputype = CPU_25KF;
1611 c->writecombine = _CACHE_UNCACHED;
1612 __cpu_name[cpu] = "MIPS 25Kc";
1615 c->cputype = CPU_34K;
1616 c->writecombine = _CACHE_UNCACHED;
1617 __cpu_name[cpu] = "MIPS 34Kc";
1618 cpu_set_mt_per_tc_perf(c);
1621 c->cputype = CPU_74K;
1622 c->writecombine = _CACHE_UNCACHED;
1623 __cpu_name[cpu] = "MIPS 74Kc";
1625 case PRID_IMP_M14KC:
1626 c->cputype = CPU_M14KC;
1627 c->writecombine = _CACHE_UNCACHED;
1628 __cpu_name[cpu] = "MIPS M14Kc";
1630 case PRID_IMP_M14KEC:
1631 c->cputype = CPU_M14KEC;
1632 c->writecombine = _CACHE_UNCACHED;
1633 __cpu_name[cpu] = "MIPS M14KEc";
1635 case PRID_IMP_1004K:
1636 c->cputype = CPU_1004K;
1637 c->writecombine = _CACHE_UNCACHED;
1638 __cpu_name[cpu] = "MIPS 1004Kc";
1639 cpu_set_mt_per_tc_perf(c);
1641 case PRID_IMP_1074K:
1642 c->cputype = CPU_1074K;
1643 c->writecombine = _CACHE_UNCACHED;
1644 __cpu_name[cpu] = "MIPS 1074Kc";
1646 case PRID_IMP_INTERAPTIV_UP:
1647 c->cputype = CPU_INTERAPTIV;
1648 __cpu_name[cpu] = "MIPS interAptiv";
1649 cpu_set_mt_per_tc_perf(c);
1651 case PRID_IMP_INTERAPTIV_MP:
1652 c->cputype = CPU_INTERAPTIV;
1653 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1654 cpu_set_mt_per_tc_perf(c);
1656 case PRID_IMP_PROAPTIV_UP:
1657 c->cputype = CPU_PROAPTIV;
1658 __cpu_name[cpu] = "MIPS proAptiv";
1660 case PRID_IMP_PROAPTIV_MP:
1661 c->cputype = CPU_PROAPTIV;
1662 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1664 case PRID_IMP_P5600:
1665 c->cputype = CPU_P5600;
1666 __cpu_name[cpu] = "MIPS P5600";
1668 case PRID_IMP_P6600:
1669 c->cputype = CPU_P6600;
1670 __cpu_name[cpu] = "MIPS P6600";
1672 case PRID_IMP_I6400:
1673 c->cputype = CPU_I6400;
1674 __cpu_name[cpu] = "MIPS I6400";
1676 case PRID_IMP_I6500:
1677 c->cputype = CPU_I6500;
1678 __cpu_name[cpu] = "MIPS I6500";
1680 case PRID_IMP_M5150:
1681 c->cputype = CPU_M5150;
1682 __cpu_name[cpu] = "MIPS M5150";
1684 case PRID_IMP_M6250:
1685 c->cputype = CPU_M6250;
1686 __cpu_name[cpu] = "MIPS M6250";
1694 switch (__get_cpu_type(c->cputype)) {
1696 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1699 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1706 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1709 switch (c->processor_id & PRID_IMP_MASK) {
1710 case PRID_IMP_AU1_REV1:
1711 case PRID_IMP_AU1_REV2:
1712 c->cputype = CPU_ALCHEMY;
1713 switch ((c->processor_id >> 24) & 0xff) {
1715 __cpu_name[cpu] = "Au1000";
1718 __cpu_name[cpu] = "Au1500";
1721 __cpu_name[cpu] = "Au1100";
1724 __cpu_name[cpu] = "Au1550";
1727 __cpu_name[cpu] = "Au1200";
1728 if ((c->processor_id & PRID_REV_MASK) == 2)
1729 __cpu_name[cpu] = "Au1250";
1732 __cpu_name[cpu] = "Au1210";
1735 __cpu_name[cpu] = "Au1xxx";
1742 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1746 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1747 switch (c->processor_id & PRID_IMP_MASK) {
1749 c->cputype = CPU_SB1;
1750 __cpu_name[cpu] = "SiByte SB1";
1751 /* FPU in pass1 is known to have issues. */
1752 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1753 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1756 c->cputype = CPU_SB1A;
1757 __cpu_name[cpu] = "SiByte SB1A";
1762 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1765 switch (c->processor_id & PRID_IMP_MASK) {
1766 case PRID_IMP_SR71000:
1767 c->cputype = CPU_SR71000;
1768 __cpu_name[cpu] = "Sandcraft SR71000";
1775 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1778 switch (c->processor_id & PRID_IMP_MASK) {
1779 case PRID_IMP_PR4450:
1780 c->cputype = CPU_PR4450;
1781 __cpu_name[cpu] = "Philips PR4450";
1782 set_isa(c, MIPS_CPU_ISA_M32R1);
1787 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1790 switch (c->processor_id & PRID_IMP_MASK) {
1791 case PRID_IMP_BMIPS32_REV4:
1792 case PRID_IMP_BMIPS32_REV8:
1793 c->cputype = CPU_BMIPS32;
1794 __cpu_name[cpu] = "Broadcom BMIPS32";
1795 set_elf_platform(cpu, "bmips32");
1797 case PRID_IMP_BMIPS3300:
1798 case PRID_IMP_BMIPS3300_ALT:
1799 case PRID_IMP_BMIPS3300_BUG:
1800 c->cputype = CPU_BMIPS3300;
1801 __cpu_name[cpu] = "Broadcom BMIPS3300";
1802 set_elf_platform(cpu, "bmips3300");
1804 case PRID_IMP_BMIPS43XX: {
1805 int rev = c->processor_id & PRID_REV_MASK;
1807 if (rev >= PRID_REV_BMIPS4380_LO &&
1808 rev <= PRID_REV_BMIPS4380_HI) {
1809 c->cputype = CPU_BMIPS4380;
1810 __cpu_name[cpu] = "Broadcom BMIPS4380";
1811 set_elf_platform(cpu, "bmips4380");
1812 c->options |= MIPS_CPU_RIXI;
1814 c->cputype = CPU_BMIPS4350;
1815 __cpu_name[cpu] = "Broadcom BMIPS4350";
1816 set_elf_platform(cpu, "bmips4350");
1820 case PRID_IMP_BMIPS5000:
1821 case PRID_IMP_BMIPS5200:
1822 c->cputype = CPU_BMIPS5000;
1823 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1824 __cpu_name[cpu] = "Broadcom BMIPS5200";
1826 __cpu_name[cpu] = "Broadcom BMIPS5000";
1827 set_elf_platform(cpu, "bmips5000");
1828 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1833 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1836 switch (c->processor_id & PRID_IMP_MASK) {
1837 case PRID_IMP_CAVIUM_CN38XX:
1838 case PRID_IMP_CAVIUM_CN31XX:
1839 case PRID_IMP_CAVIUM_CN30XX:
1840 c->cputype = CPU_CAVIUM_OCTEON;
1841 __cpu_name[cpu] = "Cavium Octeon";
1843 case PRID_IMP_CAVIUM_CN58XX:
1844 case PRID_IMP_CAVIUM_CN56XX:
1845 case PRID_IMP_CAVIUM_CN50XX:
1846 case PRID_IMP_CAVIUM_CN52XX:
1847 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1848 __cpu_name[cpu] = "Cavium Octeon+";
1850 set_elf_platform(cpu, "octeon");
1852 case PRID_IMP_CAVIUM_CN61XX:
1853 case PRID_IMP_CAVIUM_CN63XX:
1854 case PRID_IMP_CAVIUM_CN66XX:
1855 case PRID_IMP_CAVIUM_CN68XX:
1856 case PRID_IMP_CAVIUM_CNF71XX:
1857 c->cputype = CPU_CAVIUM_OCTEON2;
1858 __cpu_name[cpu] = "Cavium Octeon II";
1859 set_elf_platform(cpu, "octeon2");
1861 case PRID_IMP_CAVIUM_CN70XX:
1862 case PRID_IMP_CAVIUM_CN73XX:
1863 case PRID_IMP_CAVIUM_CNF75XX:
1864 case PRID_IMP_CAVIUM_CN78XX:
1865 c->cputype = CPU_CAVIUM_OCTEON3;
1866 __cpu_name[cpu] = "Cavium Octeon III";
1867 set_elf_platform(cpu, "octeon3");
1870 printk(KERN_INFO "Unknown Octeon chip!\n");
1871 c->cputype = CPU_UNKNOWN;
1876 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1878 switch (c->processor_id & PRID_IMP_MASK) {
1879 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1880 switch (c->processor_id & PRID_REV_MASK) {
1881 case PRID_REV_LOONGSON3A_R2_0:
1882 case PRID_REV_LOONGSON3A_R2_1:
1883 c->cputype = CPU_LOONGSON3;
1884 __cpu_name[cpu] = "ICT Loongson-3";
1885 set_elf_platform(cpu, "loongson3a");
1886 set_isa(c, MIPS_CPU_ISA_M64R2);
1888 case PRID_REV_LOONGSON3A_R3_0:
1889 case PRID_REV_LOONGSON3A_R3_1:
1890 c->cputype = CPU_LOONGSON3;
1891 __cpu_name[cpu] = "ICT Loongson-3";
1892 set_elf_platform(cpu, "loongson3a");
1893 set_isa(c, MIPS_CPU_ISA_M64R2);
1898 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1899 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1902 panic("Unknown Loongson Processor ID!");
1907 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1910 /* JZRISC does not implement the CP0 counter. */
1911 c->options &= ~MIPS_CPU_COUNTER;
1912 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1913 switch (c->processor_id & PRID_IMP_MASK) {
1914 case PRID_IMP_JZRISC:
1915 c->cputype = CPU_JZRISC;
1916 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1917 __cpu_name[cpu] = "Ingenic JZRISC";
1920 panic("Unknown Ingenic Processor ID!");
1925 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1929 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1930 c->cputype = CPU_ALCHEMY;
1931 __cpu_name[cpu] = "Au1300";
1932 /* following stuff is not for Alchemy */
1936 c->options = (MIPS_CPU_TLB |
1944 switch (c->processor_id & PRID_IMP_MASK) {
1945 case PRID_IMP_NETLOGIC_XLP2XX:
1946 case PRID_IMP_NETLOGIC_XLP9XX:
1947 case PRID_IMP_NETLOGIC_XLP5XX:
1948 c->cputype = CPU_XLP;
1949 __cpu_name[cpu] = "Broadcom XLPII";
1952 case PRID_IMP_NETLOGIC_XLP8XX:
1953 case PRID_IMP_NETLOGIC_XLP3XX:
1954 c->cputype = CPU_XLP;
1955 __cpu_name[cpu] = "Netlogic XLP";
1958 case PRID_IMP_NETLOGIC_XLR732:
1959 case PRID_IMP_NETLOGIC_XLR716:
1960 case PRID_IMP_NETLOGIC_XLR532:
1961 case PRID_IMP_NETLOGIC_XLR308:
1962 case PRID_IMP_NETLOGIC_XLR532C:
1963 case PRID_IMP_NETLOGIC_XLR516C:
1964 case PRID_IMP_NETLOGIC_XLR508C:
1965 case PRID_IMP_NETLOGIC_XLR308C:
1966 c->cputype = CPU_XLR;
1967 __cpu_name[cpu] = "Netlogic XLR";
1970 case PRID_IMP_NETLOGIC_XLS608:
1971 case PRID_IMP_NETLOGIC_XLS408:
1972 case PRID_IMP_NETLOGIC_XLS404:
1973 case PRID_IMP_NETLOGIC_XLS208:
1974 case PRID_IMP_NETLOGIC_XLS204:
1975 case PRID_IMP_NETLOGIC_XLS108:
1976 case PRID_IMP_NETLOGIC_XLS104:
1977 case PRID_IMP_NETLOGIC_XLS616B:
1978 case PRID_IMP_NETLOGIC_XLS608B:
1979 case PRID_IMP_NETLOGIC_XLS416B:
1980 case PRID_IMP_NETLOGIC_XLS412B:
1981 case PRID_IMP_NETLOGIC_XLS408B:
1982 case PRID_IMP_NETLOGIC_XLS404B:
1983 c->cputype = CPU_XLR;
1984 __cpu_name[cpu] = "Netlogic XLS";
1988 pr_info("Unknown Netlogic chip id [%02x]!\n",
1990 c->cputype = CPU_XLR;
1994 if (c->cputype == CPU_XLP) {
1995 set_isa(c, MIPS_CPU_ISA_M64R2);
1996 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1997 /* This will be updated again after all threads are woken up */
1998 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2000 set_isa(c, MIPS_CPU_ISA_M64R1);
2001 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2003 c->kscratch_mask = 0xf;
2007 /* For use by uaccess.h */
2009 EXPORT_SYMBOL(__ua_limit);
2012 const char *__cpu_name[NR_CPUS];
2013 const char *__elf_platform;
2015 void cpu_probe(void)
2017 struct cpuinfo_mips *c = ¤t_cpu_data;
2018 unsigned int cpu = smp_processor_id();
2021 * Set a default elf platform, cpu probe may later
2022 * overwrite it with a more precise value
2024 set_elf_platform(cpu, "mips");
2026 c->processor_id = PRID_IMP_UNKNOWN;
2027 c->fpu_id = FPIR_IMP_NONE;
2028 c->cputype = CPU_UNKNOWN;
2029 c->writecombine = _CACHE_UNCACHED;
2031 c->fpu_csr31 = FPU_CSR_RN;
2032 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2034 c->processor_id = read_c0_prid();
2035 switch (c->processor_id & PRID_COMP_MASK) {
2036 case PRID_COMP_LEGACY:
2037 cpu_probe_legacy(c, cpu);
2039 case PRID_COMP_MIPS:
2040 cpu_probe_mips(c, cpu);
2042 case PRID_COMP_ALCHEMY:
2043 cpu_probe_alchemy(c, cpu);
2045 case PRID_COMP_SIBYTE:
2046 cpu_probe_sibyte(c, cpu);
2048 case PRID_COMP_BROADCOM:
2049 cpu_probe_broadcom(c, cpu);
2051 case PRID_COMP_SANDCRAFT:
2052 cpu_probe_sandcraft(c, cpu);
2055 cpu_probe_nxp(c, cpu);
2057 case PRID_COMP_CAVIUM:
2058 cpu_probe_cavium(c, cpu);
2060 case PRID_COMP_LOONGSON:
2061 cpu_probe_loongson(c, cpu);
2063 case PRID_COMP_INGENIC_D0:
2064 case PRID_COMP_INGENIC_D1:
2065 case PRID_COMP_INGENIC_E1:
2066 cpu_probe_ingenic(c, cpu);
2068 case PRID_COMP_NETLOGIC:
2069 cpu_probe_netlogic(c, cpu);
2073 BUG_ON(!__cpu_name[cpu]);
2074 BUG_ON(c->cputype == CPU_UNKNOWN);
2077 * Platform code can force the cpu type to optimize code
2078 * generation. In that case be sure the cpu type is correctly
2079 * manually setup otherwise it could trigger some nasty bugs.
2081 BUG_ON(current_cpu_type() != c->cputype);
2084 /* Enable the RIXI exceptions */
2085 set_c0_pagegrain(PG_IEC);
2086 back_to_back_c0_hazard();
2087 /* Verify the IEC bit is set */
2088 if (read_c0_pagegrain() & PG_IEC)
2089 c->options |= MIPS_CPU_RIXIEX;
2092 if (mips_fpu_disabled)
2093 c->options &= ~MIPS_CPU_FPU;
2095 if (mips_dsp_disabled)
2096 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2098 if (mips_htw_disabled) {
2099 c->options &= ~MIPS_CPU_HTW;
2100 write_c0_pwctl(read_c0_pwctl() &
2101 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2104 if (c->options & MIPS_CPU_FPU)
2105 cpu_set_fpu_opts(c);
2107 cpu_set_nofpu_opts(c);
2109 if (cpu_has_bp_ghist)
2110 write_c0_r10k_diag(read_c0_r10k_diag() |
2113 if (cpu_has_mips_r2_r6) {
2114 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2115 /* R2 has Performance Counter Interrupt indicator */
2116 c->options |= MIPS_CPU_PCI;
2121 if (cpu_has_mips_r6)
2122 elf_hwcap |= HWCAP_MIPS_R6;
2125 c->msa_id = cpu_get_msa_id();
2126 WARN(c->msa_id & MSA_IR_WRPF,
2127 "Vector register partitioning unimplemented!");
2128 elf_hwcap |= HWCAP_MIPS_MSA;
2134 cpu_probe_vmbits(c);
2138 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2142 void cpu_report(void)
2144 struct cpuinfo_mips *c = ¤t_cpu_data;
2146 pr_info("CPU%d revision is: %08x (%s)\n",
2147 smp_processor_id(), c->processor_id, cpu_name_string());
2148 if (c->options & MIPS_CPU_FPU)
2149 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2151 pr_info("MSA revision is: %08x\n", c->msa_id);
2154 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2156 /* Ensure the core number fits in the field */
2157 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2158 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2160 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2161 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2164 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2166 /* Ensure the core number fits in the field */
2167 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2169 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2170 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2173 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2175 /* Ensure the VP(E) ID fits in the field */
2176 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2178 /* Ensure we're not using VP(E)s without support */
2179 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2180 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2182 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2183 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;