arch/mips/kernel/cpu-probe.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Processor capabilities determination functions.
   4  *
   5  * Copyright (C) xxxx  the Anonymous
   6  * Copyright (C) 1994 - 2006 Ralf Baechle
   7  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   8  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/smp.h>
  14 #include <linux/stddef.h>
  15 #include <linux/export.h>
  16
  17 #include <asm/bugs.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpu-features.h>
  20 #include <asm/cpu-type.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/mipsmtregs.h>
  24 #include <asm/msa.h>
  25 #include <asm/watch.h>
  26 #include <asm/elf.h>
  27 #include <asm/pgtable-bits.h>
  28 #include <asm/spram.h>
  29 #include <linux/uaccess.h>
  30
  31 #include <asm/mach-loongson64/cpucfg-emul.h>
  32
  33 /* Hardware capabilities */
  34 unsigned int elf_hwcap __read_mostly;
  35 EXPORT_SYMBOL_GPL(elf_hwcap);
  36
  37 #ifdef CONFIG_MIPS_FP_SUPPORT
  38
  39 /*
  40  * Get the FPU Implementation/Revision.
  41  */
  42 static inline unsigned long cpu_get_fpu_id(void)
  43 {
  44         unsigned long tmp, fpu_id;
  45
  46         tmp = read_c0_status();
  47         __enable_fpu(FPU_AS_IS);
  48         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  49         write_c0_status(tmp);
  50         return fpu_id;
  51 }
  52
  53 /*
  54  * Check if the CPU has an external FPU.
  55  */
  56 static inline int __cpu_has_fpu(void)
  57 {
  58         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  59 }
  60
  61 /*
  62  * Determine the FCSR mask for FPU hardware.
  63  */
  64 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  65 {
  66         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  67
  68         fcsr = c->fpu_csr31;
  69         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  70
  71         sr = read_c0_status();
  72         __enable_fpu(FPU_AS_IS);
  73
  74         fcsr0 = fcsr & mask;
  75         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  76         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  77
  78         fcsr1 = fcsr | ~mask;
  79         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  80         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  81
  82         write_32bit_cp1_register(CP1_STATUS, fcsr);
  83
  84         write_c0_status(sr);
  85
  86         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  87 }
  88
  89 /*
  90  * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
  91  * supported by FPU hardware.
  92  */
  93 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
  94 {
  95         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
  96                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
  97                             MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
  98                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
  99                 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
 100
 101                 sr = read_c0_status();
 102                 __enable_fpu(FPU_AS_IS);
 103
 104                 fir = read_32bit_cp1_register(CP1_REVISION);
 105                 if (fir & MIPS_FPIR_HAS2008) {
 106                         fcsr = read_32bit_cp1_register(CP1_STATUS);
 107
 108                         /*
 109                          * MAC2008 toolchain never landed in real world, so we're only
 110                          * testing wether it can be disabled and don't try to enabled
 111                          * it.
 112                          */
 113                         fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008 | FPU_CSR_MAC2008);
 114                         write_32bit_cp1_register(CP1_STATUS, fcsr0);
 115                         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
 116
 117                         fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 118                         write_32bit_cp1_register(CP1_STATUS, fcsr1);
 119                         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
 120
 121                         write_32bit_cp1_register(CP1_STATUS, fcsr);
 122
 123                         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2)) {
 124                                 /*
 125                                  * The bit for MAC2008 might be reused by R6 in future,
 126                                  * so we only test for R2-R5.
 127                                  */
 128                                 if (fcsr0 & FPU_CSR_MAC2008)
 129                                         c->options |= MIPS_CPU_MAC_2008_ONLY;
 130                         }
 131
 132                         if (!(fcsr0 & FPU_CSR_NAN2008))
 133                                 c->options |= MIPS_CPU_NAN_LEGACY;
 134                         if (fcsr1 & FPU_CSR_NAN2008)
 135                                 c->options |= MIPS_CPU_NAN_2008;
 136
 137                         if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
 138                                 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
 139                         else
 140                                 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
 141
 142                         if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
 143                                 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
 144                         else
 145                                 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
 146                 } else {
 147                         c->options |= MIPS_CPU_NAN_LEGACY;
 148                 }
 149
 150                 write_c0_status(sr);
 151         } else {
 152                 c->options |= MIPS_CPU_NAN_LEGACY;
 153         }
 154 }
 155
 156 /*
 157  * IEEE 754 conformance mode to use.  Affects the NaN encoding and the
 158  * ABS.fmt/NEG.fmt execution mode.
 159  */
 160 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
 161
 162 /*
 163  * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
 164  * to support by the FPU emulator according to the IEEE 754 conformance
 165  * mode selected.  Note that "relaxed" straps the emulator so that it
 166  * allows 2008-NaN binaries even for legacy processors.
 167  */
 168 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
 169 {
 170         c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
 171         c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 172         c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 173
 174         switch (ieee754) {
 175         case STRICT:
 176                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 177                                     MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 178                                     MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
 179                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 180                         c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
 181                 } else {
 182                         c->options |= MIPS_CPU_NAN_LEGACY;
 183                         c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 184                 }
 185                 break;
 186         case LEGACY:
 187                 c->options |= MIPS_CPU_NAN_LEGACY;
 188                 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 189                 break;
 190         case STD2008:
 191                 c->options |= MIPS_CPU_NAN_2008;
 192                 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 193                 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 194                 break;
 195         case RELAXED:
 196                 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
 197                 break;
 198         }
 199 }
 200
 201 /*
 202  * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
 203  * according to the "ieee754=" parameter.
 204  */
 205 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
 206 {
 207         switch (ieee754) {
 208         case STRICT:
 209                 mips_use_nan_legacy = !!cpu_has_nan_legacy;
 210                 mips_use_nan_2008 = !!cpu_has_nan_2008;
 211                 break;
 212         case LEGACY:
 213                 mips_use_nan_legacy = !!cpu_has_nan_legacy;
 214                 mips_use_nan_2008 = !cpu_has_nan_legacy;
 215                 break;
 216         case STD2008:
 217                 mips_use_nan_legacy = !cpu_has_nan_2008;
 218                 mips_use_nan_2008 = !!cpu_has_nan_2008;
 219                 break;
 220         case RELAXED:
 221                 mips_use_nan_legacy = true;
 222                 mips_use_nan_2008 = true;
 223                 break;
 224         }
 225 }
 226
 227 /*
 228  * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
 229  * settings:
 230  *
 231  * strict:  accept binaries that request a NaN encoding supported by the FPU
 232  * legacy:  only accept legacy-NaN binaries
 233  * 2008:    only accept 2008-NaN binaries
 234  * relaxed: accept any binaries regardless of whether supported by the FPU
 235  */
 236 static int __init ieee754_setup(char *s)
 237 {
 238         if (!s)
 239                 return -1;
 240         else if (!strcmp(s, "strict"))
 241                 ieee754 = STRICT;
 242         else if (!strcmp(s, "legacy"))
 243                 ieee754 = LEGACY;
 244         else if (!strcmp(s, "2008"))
 245                 ieee754 = STD2008;
 246         else if (!strcmp(s, "relaxed"))
 247                 ieee754 = RELAXED;
 248         else
 249                 return -1;
 250
 251         if (!(boot_cpu_data.options & MIPS_CPU_FPU))
 252                 cpu_set_nofpu_2008(&boot_cpu_data);
 253         cpu_set_nan_2008(&boot_cpu_data);
 254
 255         return 0;
 256 }
 257
 258 early_param("ieee754", ieee754_setup);
 259
 260 /*
 261  * Set the FIR feature flags for the FPU emulator.
 262  */
 263 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 264 {
 265         u32 value;
 266
 267         value = 0;
 268         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 269                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 270                             MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
 271                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 272                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 273         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 274                             MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
 275                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 276                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 277         if (c->options & MIPS_CPU_NAN_2008)
 278                 value |= MIPS_FPIR_HAS2008;
 279         c->fpu_id = value;
 280 }
 281
 282 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 283 static unsigned int mips_nofpu_msk31;
 284
 285 /*
 286  * Set options for FPU hardware.
 287  */
 288 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 289 {
 290         c->fpu_id = cpu_get_fpu_id();
 291         mips_nofpu_msk31 = c->fpu_msk31;
 292
 293         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 294                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 295                             MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
 296                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 297                 if (c->fpu_id & MIPS_FPIR_3D)
 298                         c->ases |= MIPS_ASE_MIPS3D;
 299                 if (c->fpu_id & MIPS_FPIR_UFRP)
 300                         c->options |= MIPS_CPU_UFR;
 301                 if (c->fpu_id & MIPS_FPIR_FREP)
 302                         c->options |= MIPS_CPU_FRE;
 303         }
 304
 305         cpu_set_fpu_fcsr_mask(c);
 306         cpu_set_fpu_2008(c);
 307         cpu_set_nan_2008(c);
 308 }
 309
 310 /*
 311  * Set options for the FPU emulator.
 312  */
 313 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 314 {
 315         c->options &= ~MIPS_CPU_FPU;
 316         c->fpu_msk31 = mips_nofpu_msk31;
 317
 318         cpu_set_nofpu_2008(c);
 319         cpu_set_nan_2008(c);
 320         cpu_set_nofpu_id(c);
 321 }
 322
 323 static int mips_fpu_disabled;
 324
 325 static int __init fpu_disable(char *s)
 326 {
 327         cpu_set_nofpu_opts(&boot_cpu_data);
 328         mips_fpu_disabled = 1;
 329
 330         return 1;
 331 }
 332
 333 __setup("nofpu", fpu_disable);
 334
 335 #else /* !CONFIG_MIPS_FP_SUPPORT */
 336
 337 #define mips_fpu_disabled 1
 338
 339 static inline unsigned long cpu_get_fpu_id(void)
 340 {
 341         return FPIR_IMP_NONE;
 342 }
 343
 344 static inline int __cpu_has_fpu(void)
 345 {
 346         return 0;
 347 }
 348
 349 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 350 {
 351         /* no-op */
 352 }
 353
 354 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 355 {
 356         /* no-op */
 357 }
 358
 359 #endif /* CONFIG_MIPS_FP_SUPPORT */
 360
 361 static inline unsigned long cpu_get_msa_id(void)
 362 {
 363         unsigned long status, msa_id;
 364
 365         status = read_c0_status();
 366         __enable_fpu(FPU_64BIT);
 367         enable_msa();
 368         msa_id = read_msa_ir();
 369         disable_msa();
 370         write_c0_status(status);
 371         return msa_id;
 372 }
 373
 374 static int mips_dsp_disabled;
 375
 376 static int __init dsp_disable(char *s)
 377 {
 378         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 379         mips_dsp_disabled = 1;
 380
 381         return 1;
 382 }
 383
 384 __setup("nodsp", dsp_disable);
 385
 386 static int mips_htw_disabled;
 387
 388 static int __init htw_disable(char *s)
 389 {
 390         mips_htw_disabled = 1;
 391         cpu_data[0].options &= ~MIPS_CPU_HTW;
 392         write_c0_pwctl(read_c0_pwctl() &
 393                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 394
 395         return 1;
 396 }
 397
 398 __setup("nohtw", htw_disable);
 399
 400 static int mips_ftlb_disabled;
 401 static int mips_has_ftlb_configured;
 402
 403 enum ftlb_flags {
 404         FTLB_EN         = 1 << 0,
 405         FTLB_SET_PROB   = 1 << 1,
 406 };
 407
 408 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
 409
 410 static int __init ftlb_disable(char *s)
 411 {
 412         unsigned int config4, mmuextdef;
 413
 414         /*
 415          * If the core hasn't done any FTLB configuration, there is nothing
 416          * for us to do here.
 417          */
 418         if (!mips_has_ftlb_configured)
 419                 return 1;
 420
 421         /* Disable it in the boot cpu */
 422         if (set_ftlb_enable(&cpu_data[0], 0)) {
 423                 pr_warn("Can't turn FTLB off\n");
 424                 return 1;
 425         }
 426
 427         config4 = read_c0_config4();
 428
 429         /* Check that FTLB has been disabled */
 430         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 431         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 432         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 433                 /* This should never happen */
 434                 pr_warn("FTLB could not be disabled!\n");
 435                 return 1;
 436         }
 437
 438         mips_ftlb_disabled = 1;
 439         mips_has_ftlb_configured = 0;
 440
 441         /*
 442          * noftlb is mainly used for debug purposes so print
 443          * an informative message instead of using pr_debug()
 444          */
 445         pr_info("FTLB has been disabled\n");
 446
 447         /*
 448          * Some of these bits are duplicated in the decode_config4.
 449          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 450          * once FTLB has been disabled so undo what decode_config4 did.
 451          */
 452         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 453                                cpu_data[0].tlbsizeftlbsets;
 454         cpu_data[0].tlbsizeftlbsets = 0;
 455         cpu_data[0].tlbsizeftlbways = 0;
 456
 457         return 1;
 458 }
 459
 460 __setup("noftlb", ftlb_disable);
 461
 462 /*
 463  * Check if the CPU has per tc perf counters
 464  */
 465 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
 466 {
 467         if (read_c0_config7() & MTI_CONF7_PTC)
 468                 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
 469 }
 470
 471 static inline void check_errata(void)
 472 {
 473         struct cpuinfo_mips *c = &current_cpu_data;
 474
 475         switch (current_cpu_type()) {
 476         case CPU_34K:
 477                 /*
 478                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 479                  * This code only handles VPE0, any SMP/RTOS code
 480                  * making use of VPE1 will be responsable for that VPE.
 481                  */
 482                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 483                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 484                 break;
 485         default:
 486                 break;
 487         }
 488 }
 489
 490 void __init check_bugs32(void)
 491 {
 492         check_errata();
 493 }
 494
 495 /*
 496  * Probe whether cpu has config register by trying to play with
 497  * alternate cache bit and see whether it matters.
 498  * It's used by cpu_probe to distinguish between R3000A and R3081.
 499  */
 500 static inline int cpu_has_confreg(void)
 501 {
 502 #ifdef CONFIG_CPU_R3000
 503         extern unsigned long r3k_cache_size(unsigned long);
 504         unsigned long size1, size2;
 505         unsigned long cfg = read_c0_conf();
 506
 507         size1 = r3k_cache_size(ST0_ISC);
 508         write_c0_conf(cfg ^ R30XX_CONF_AC);
 509         size2 = r3k_cache_size(ST0_ISC);
 510         write_c0_conf(cfg);
 511         return size1 != size2;
 512 #else
 513         return 0;
 514 #endif
 515 }
 516
 517 static inline void set_elf_platform(int cpu, const char *plat)
 518 {
 519         if (cpu == 0)
 520                 __elf_platform = plat;
 521 }
 522
 523 static inline void set_elf_base_platform(const char *plat)
 524 {
 525         if (__elf_base_platform == NULL) {
 526                 __elf_base_platform = plat;
 527         }
 528 }
 529
 530 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 531 {
 532 #ifdef __NEED_VMBITS_PROBE
 533         write_c0_entryhi(0x3fffffffffffe000ULL);
 534         back_to_back_c0_hazard();
 535         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 536 #endif
 537 }
 538
 539 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 540 {
 541         switch (isa) {
 542         case MIPS_CPU_ISA_M64R5:
 543                 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
 544                 set_elf_base_platform("mips64r5");
 545                 fallthrough;
 546         case MIPS_CPU_ISA_M64R2:
 547                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 548                 set_elf_base_platform("mips64r2");
 549                 fallthrough;
 550         case MIPS_CPU_ISA_M64R1:
 551                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 552                 set_elf_base_platform("mips64");
 553                 fallthrough;
 554         case MIPS_CPU_ISA_V:
 555                 c->isa_level |= MIPS_CPU_ISA_V;
 556                 set_elf_base_platform("mips5");
 557                 fallthrough;
 558         case MIPS_CPU_ISA_IV:
 559                 c->isa_level |= MIPS_CPU_ISA_IV;
 560                 set_elf_base_platform("mips4");
 561                 fallthrough;
 562         case MIPS_CPU_ISA_III:
 563                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 564                 set_elf_base_platform("mips3");
 565                 break;
 566
 567         /* R6 incompatible with everything else */
 568         case MIPS_CPU_ISA_M64R6:
 569                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 570                 set_elf_base_platform("mips64r6");
 571                 fallthrough;
 572         case MIPS_CPU_ISA_M32R6:
 573                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 574                 set_elf_base_platform("mips32r6");
 575                 /* Break here so we don't add incompatible ISAs */
 576                 break;
 577         case MIPS_CPU_ISA_M32R5:
 578                 c->isa_level |= MIPS_CPU_ISA_M32R5;
 579                 set_elf_base_platform("mips32r5");
 580                 fallthrough;
 581         case MIPS_CPU_ISA_M32R2:
 582                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 583                 set_elf_base_platform("mips32r2");
 584                 fallthrough;
 585         case MIPS_CPU_ISA_M32R1:
 586                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 587                 set_elf_base_platform("mips32");
 588                 fallthrough;
 589         case MIPS_CPU_ISA_II:
 590                 c->isa_level |= MIPS_CPU_ISA_II;
 591                 set_elf_base_platform("mips2");
 592                 break;
 593         }
 594 }
 595
 596 static char unknown_isa[] = KERN_ERR \
 597         "Unsupported ISA type, c0.config0: %d.";
 598
 599 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 600 {
 601
 602         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 603
 604         /*
 605          * 0 = All TLBWR instructions go to FTLB
 606          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 607          * FTLB and 1 goes to the VTLB.
 608          * 2 = 7:1: As above with 7:1 ratio.
 609          * 3 = 3:1: As above with 3:1 ratio.
 610          *
 611          * Use the linear midpoint as the probability threshold.
 612          */
 613         if (probability >= 12)
 614                 return 1;
 615         else if (probability >= 6)
 616                 return 2;
 617         else
 618                 /*
 619                  * So FTLB is less than 4 times bigger than VTLB.
 620                  * A 3:1 ratio can still be useful though.
 621                  */
 622                 return 3;
 623 }
 624
 625 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
 626 {
 627         unsigned int config;
 628
 629         /* It's implementation dependent how the FTLB can be enabled */
 630         switch (c->cputype) {
 631         case CPU_PROAPTIV:
 632         case CPU_P5600:
 633         case CPU_P6600:
 634                 /* proAptiv & related cores use Config6 to enable the FTLB */
 635                 config = read_c0_config6();
 636
 637                 if (flags & FTLB_EN)
 638                         config |= MIPS_CONF6_MTI_FTLBEN;
 639                 else
 640                         config &= ~MIPS_CONF6_MTI_FTLBEN;
 641
 642                 if (flags & FTLB_SET_PROB) {
 643                         config &= ~(3 << MIPS_CONF6_MTI_FTLBP_SHIFT);
 644                         config |= calculate_ftlb_probability(c)
 645                                   << MIPS_CONF6_MTI_FTLBP_SHIFT;
 646                 }
 647
 648                 write_c0_config6(config);
 649                 back_to_back_c0_hazard();
 650                 break;
 651         case CPU_I6400:
 652         case CPU_I6500:
 653                 /* There's no way to disable the FTLB */
 654                 if (!(flags & FTLB_EN))
 655                         return 1;
 656                 return 0;
 657         case CPU_LOONGSON64:
 658                 /* Flush ITLB, DTLB, VTLB and FTLB */
 659                 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
 660                               LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
 661                 /* Loongson-3 cores use Config6 to enable the FTLB */
 662                 config = read_c0_config6();
 663                 if (flags & FTLB_EN)
 664                         /* Enable FTLB */
 665                         write_c0_config6(config & ~MIPS_CONF6_LOONGSON_FTLBDIS);
 666                 else
 667                         /* Disable FTLB */
 668                         write_c0_config6(config | MIPS_CONF6_LOONGSON_FTLBDIS);
 669                 break;
 670         default:
 671                 return 1;
 672         }
 673
 674         return 0;
 675 }
 676
 677 static int mm_config(struct cpuinfo_mips *c)
 678 {
 679         unsigned int config0, update, mm;
 680
 681         config0 = read_c0_config();
 682         mm = config0 & MIPS_CONF_MM;
 683
 684         /*
 685          * It's implementation dependent what type of write-merge is supported
 686          * and whether it can be enabled/disabled. If it is settable lets make
 687          * the merging allowed by default. Some platforms might have
 688          * write-through caching unsupported. In this case just ignore the
 689          * CP0.Config.MM bit field value.
 690          */
 691         switch (c->cputype) {
 692         case CPU_24K:
 693         case CPU_34K:
 694         case CPU_74K:
 695         case CPU_P5600:
 696         case CPU_P6600:
 697                 c->options |= MIPS_CPU_MM_FULL;
 698                 update = MIPS_CONF_MM_FULL;
 699                 break;
 700         case CPU_1004K:
 701         case CPU_1074K:
 702         case CPU_INTERAPTIV:
 703         case CPU_PROAPTIV:
 704                 mm = 0;
 705                 fallthrough;
 706         default:
 707                 update = 0;
 708                 break;
 709         }
 710
 711         if (update) {
 712                 config0 = (config0 & ~MIPS_CONF_MM) | update;
 713                 write_c0_config(config0);
 714         } else if (mm == MIPS_CONF_MM_SYSAD) {
 715                 c->options |= MIPS_CPU_MM_SYSAD;
 716         } else if (mm == MIPS_CONF_MM_FULL) {
 717                 c->options |= MIPS_CPU_MM_FULL;
 718         }
 719
 720         return 0;
 721 }
 722
 723 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 724 {
 725         unsigned int config0;
 726         int isa, mt;
 727
 728         config0 = read_c0_config();
 729
 730         /*
 731          * Look for Standard TLB or Dual VTLB and FTLB
 732          */
 733         mt = config0 & MIPS_CONF_MT;
 734         if (mt == MIPS_CONF_MT_TLB)
 735                 c->options |= MIPS_CPU_TLB;
 736         else if (mt == MIPS_CONF_MT_FTLB)
 737                 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
 738
 739         isa = (config0 & MIPS_CONF_AT) >> 13;
 740         switch (isa) {
 741         case 0:
 742                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 743                 case 0:
 744                         set_isa(c, MIPS_CPU_ISA_M32R1);
 745                         break;
 746                 case 1:
 747                         set_isa(c, MIPS_CPU_ISA_M32R2);
 748                         break;
 749                 case 2:
 750                         set_isa(c, MIPS_CPU_ISA_M32R6);
 751                         break;
 752                 default:
 753                         goto unknown;
 754                 }
 755                 break;
 756         case 2:
 757                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 758                 case 0:
 759                         set_isa(c, MIPS_CPU_ISA_M64R1);
 760                         break;
 761                 case 1:
 762                         set_isa(c, MIPS_CPU_ISA_M64R2);
 763                         break;
 764                 case 2:
 765                         set_isa(c, MIPS_CPU_ISA_M64R6);
 766                         break;
 767                 default:
 768                         goto unknown;
 769                 }
 770                 break;
 771         default:
 772                 goto unknown;
 773         }
 774
 775         return config0 & MIPS_CONF_M;
 776
 777 unknown:
 778         panic(unknown_isa, config0);
 779 }
 780
 781 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 782 {
 783         unsigned int config1;
 784
 785         config1 = read_c0_config1();
 786
 787         if (config1 & MIPS_CONF1_MD)
 788                 c->ases |= MIPS_ASE_MDMX;
 789         if (config1 & MIPS_CONF1_PC)
 790                 c->options |= MIPS_CPU_PERF;
 791         if (config1 & MIPS_CONF1_WR)
 792                 c->options |= MIPS_CPU_WATCH;
 793         if (config1 & MIPS_CONF1_CA)
 794                 c->ases |= MIPS_ASE_MIPS16;
 795         if (config1 & MIPS_CONF1_EP)
 796                 c->options |= MIPS_CPU_EJTAG;
 797         if (config1 & MIPS_CONF1_FP) {
 798                 c->options |= MIPS_CPU_FPU;
 799                 c->options |= MIPS_CPU_32FPR;
 800         }
 801         if (cpu_has_tlb) {
 802                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 803                 c->tlbsizevtlb = c->tlbsize;
 804                 c->tlbsizeftlbsets = 0;
 805         }
 806
 807         return config1 & MIPS_CONF_M;
 808 }
 809
 810 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 811 {
 812         unsigned int config2;
 813
 814         config2 = read_c0_config2();
 815
 816         if (config2 & MIPS_CONF2_SL)
 817                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 818
 819         return config2 & MIPS_CONF_M;
 820 }
 821
 822 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 823 {
 824         unsigned int config3;
 825
 826         config3 = read_c0_config3();
 827
 828         if (config3 & MIPS_CONF3_SM) {
 829                 c->ases |= MIPS_ASE_SMARTMIPS;
 830                 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
 831         }
 832         if (config3 & MIPS_CONF3_RXI)
 833                 c->options |= MIPS_CPU_RIXI;
 834         if (config3 & MIPS_CONF3_CTXTC)
 835                 c->options |= MIPS_CPU_CTXTC;
 836         if (config3 & MIPS_CONF3_DSP)
 837                 c->ases |= MIPS_ASE_DSP;
 838         if (config3 & MIPS_CONF3_DSP2P) {
 839                 c->ases |= MIPS_ASE_DSP2P;
 840                 if (cpu_has_mips_r6)
 841                         c->ases |= MIPS_ASE_DSP3;
 842         }
 843         if (config3 & MIPS_CONF3_VINT)
 844                 c->options |= MIPS_CPU_VINT;
 845         if (config3 & MIPS_CONF3_VEIC)
 846                 c->options |= MIPS_CPU_VEIC;
 847         if (config3 & MIPS_CONF3_LPA)
 848                 c->options |= MIPS_CPU_LPA;
 849         if (config3 & MIPS_CONF3_MT)
 850                 c->ases |= MIPS_ASE_MIPSMT;
 851         if (config3 & MIPS_CONF3_ULRI)
 852                 c->options |= MIPS_CPU_ULRI;
 853         if (config3 & MIPS_CONF3_ISA)
 854                 c->options |= MIPS_CPU_MICROMIPS;
 855         if (config3 & MIPS_CONF3_VZ)
 856                 c->ases |= MIPS_ASE_VZ;
 857         if (config3 & MIPS_CONF3_SC)
 858                 c->options |= MIPS_CPU_SEGMENTS;
 859         if (config3 & MIPS_CONF3_BI)
 860                 c->options |= MIPS_CPU_BADINSTR;
 861         if (config3 & MIPS_CONF3_BP)
 862                 c->options |= MIPS_CPU_BADINSTRP;
 863         if (config3 & MIPS_CONF3_MSA)
 864                 c->ases |= MIPS_ASE_MSA;
 865         if (config3 & MIPS_CONF3_PW) {
 866                 c->htw_seq = 0;
 867                 c->options |= MIPS_CPU_HTW;
 868         }
 869         if (config3 & MIPS_CONF3_CDMM)
 870                 c->options |= MIPS_CPU_CDMM;
 871         if (config3 & MIPS_CONF3_SP)
 872                 c->options |= MIPS_CPU_SP;
 873
 874         return config3 & MIPS_CONF_M;
 875 }
 876
 877 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 878 {
 879         unsigned int config4;
 880         unsigned int newcf4;
 881         unsigned int mmuextdef;
 882         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 883         unsigned long asid_mask;
 884
 885         config4 = read_c0_config4();
 886
 887         if (cpu_has_tlb) {
 888                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 889                         c->options |= MIPS_CPU_TLBINV;
 890
 891                 /*
 892                  * R6 has dropped the MMUExtDef field from config4.
 893                  * On R6 the fields always describe the FTLB, and only if it is
 894                  * present according to Config.MT.
 895                  */
 896                 if (!cpu_has_mips_r6)
 897                         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 898                 else if (cpu_has_ftlb)
 899                         mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
 900                 else
 901                         mmuextdef = 0;
 902
 903                 switch (mmuextdef) {
 904                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 905                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 906                         c->tlbsizevtlb = c->tlbsize;
 907                         break;
 908                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 909                         c->tlbsizevtlb +=
 910                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 911                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 912                         c->tlbsize = c->tlbsizevtlb;
 913                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 914                         fallthrough;
 915                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 916                         if (mips_ftlb_disabled)
 917                                 break;
 918                         newcf4 = (config4 & ~ftlb_page) |
 919                                 (page_size_ftlb(mmuextdef) <<
 920                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 921                         write_c0_config4(newcf4);
 922                         back_to_back_c0_hazard();
 923                         config4 = read_c0_config4();
 924                         if (config4 != newcf4) {
 925                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 926                                        PAGE_SIZE, config4);
 927                                 /* Switch FTLB off */
 928                                 set_ftlb_enable(c, 0);
 929                                 mips_ftlb_disabled = 1;
 930                                 break;
 931                         }
 932                         c->tlbsizeftlbsets = 1 <<
 933                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 934                                  MIPS_CONF4_FTLBSETS_SHIFT);
 935                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 936                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 937                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 938                         mips_has_ftlb_configured = 1;
 939                         break;
 940                 }
 941         }
 942
 943         c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
 944                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
 945
 946         asid_mask = MIPS_ENTRYHI_ASID;
 947         if (config4 & MIPS_CONF4_AE)
 948                 asid_mask |= MIPS_ENTRYHI_ASIDX;
 949         set_cpu_asid_mask(c, asid_mask);
 950
 951         /*
 952          * Warn if the computed ASID mask doesn't match the mask the kernel
 953          * is built for. This may indicate either a serious problem or an
 954          * easy optimisation opportunity, but either way should be addressed.
 955          */
 956         WARN_ON(asid_mask != cpu_asid_mask(c));
 957
 958         return config4 & MIPS_CONF_M;
 959 }
 960
 961 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 962 {
 963         unsigned int config5, max_mmid_width;
 964         unsigned long asid_mask;
 965
 966         config5 = read_c0_config5();
 967         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 968
 969         if (cpu_has_mips_r6) {
 970                 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
 971                         config5 |= MIPS_CONF5_MI;
 972                 else
 973                         config5 &= ~MIPS_CONF5_MI;
 974         }
 975
 976         write_c0_config5(config5);
 977
 978         if (config5 & MIPS_CONF5_EVA)
 979                 c->options |= MIPS_CPU_EVA;
 980         if (config5 & MIPS_CONF5_MRP)
 981                 c->options |= MIPS_CPU_MAAR;
 982         if (config5 & MIPS_CONF5_LLB)
 983                 c->options |= MIPS_CPU_RW_LLB;
 984         if (config5 & MIPS_CONF5_MVH)
 985                 c->options |= MIPS_CPU_MVH;
 986         if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
 987                 c->options |= MIPS_CPU_VP;
 988         if (config5 & MIPS_CONF5_CA2)
 989                 c->ases |= MIPS_ASE_MIPS16E2;
 990
 991         if (config5 & MIPS_CONF5_CRCP)
 992                 elf_hwcap |= HWCAP_MIPS_CRC32;
 993
 994         if (cpu_has_mips_r6) {
 995                 /* Ensure the write to config5 above takes effect */
 996                 back_to_back_c0_hazard();
 997
 998                 /* Check whether we successfully enabled MMID support */
 999                 config5 = read_c0_config5();
1000                 if (config5 & MIPS_CONF5_MI)
1001                         c->options |= MIPS_CPU_MMID;
1002
1003                 /*
1004                  * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
1005                  * for the CPU we're running on, or if CPUs in an SMP system
1006                  * have inconsistent MMID support.
1007                  */
1008                 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
1009
1010                 if (cpu_has_mmid) {
1011                         write_c0_memorymapid(~0ul);
1012                         back_to_back_c0_hazard();
1013                         asid_mask = read_c0_memorymapid();
1014
1015                         /*
1016                          * We maintain a bitmap to track MMID allocation, and
1017                          * need a sensible upper bound on the size of that
1018                          * bitmap. The initial CPU with MMID support (I6500)
1019                          * supports 16 bit MMIDs, which gives us an 8KiB
1020                          * bitmap. The architecture recommends that hardware
1021                          * support 32 bit MMIDs, which would give us a 512MiB
1022                          * bitmap - that's too big in most cases.
1023                          *
1024                          * Cap MMID width at 16 bits for now & we can revisit
1025                          * this if & when hardware supports anything wider.
1026                          */
1027                         max_mmid_width = 16;
1028                         if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
1029                                 pr_info("Capping MMID width at %d bits",
1030                                         max_mmid_width);
1031                                 asid_mask = GENMASK(max_mmid_width - 1, 0);
1032                         }
1033
1034                         set_cpu_asid_mask(c, asid_mask);
1035                 }
1036         }
1037
1038         return config5 & MIPS_CONF_M;
1039 }
1040
1041 static void decode_configs(struct cpuinfo_mips *c)
1042 {
1043         int ok;
1044
1045         /* MIPS32 or MIPS64 compliant CPU.  */
1046         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
1047                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
1048
1049         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
1050
1051         /* Enable FTLB if present and not disabled */
1052         set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
1053
1054         ok = decode_config0(c);                 /* Read Config registers.  */
1055         BUG_ON(!ok);                            /* Arch spec violation!  */
1056         if (ok)
1057                 ok = decode_config1(c);
1058         if (ok)
1059                 ok = decode_config2(c);
1060         if (ok)
1061                 ok = decode_config3(c);
1062         if (ok)
1063                 ok = decode_config4(c);
1064         if (ok)
1065                 ok = decode_config5(c);
1066
1067         /* Probe the EBase.WG bit */
1068         if (cpu_has_mips_r2_r6) {
1069                 u64 ebase;
1070                 unsigned int status;
1071
1072                 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
1073                 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
1074                                          : (s32)read_c0_ebase();
1075                 if (ebase & MIPS_EBASE_WG) {
1076                         /* WG bit already set, we can avoid the clumsy probe */
1077                         c->options |= MIPS_CPU_EBASE_WG;
1078                 } else {
1079                         /* Its UNDEFINED to change EBase while BEV=0 */
1080                         status = read_c0_status();
1081                         write_c0_status(status | ST0_BEV);
1082                         irq_enable_hazard();
1083                         /*
1084                          * On pre-r6 cores, this may well clobber the upper bits
1085                          * of EBase. This is hard to avoid without potentially
1086                          * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
1087                          */
1088                         if (cpu_has_mips64r6)
1089                                 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
1090                         else
1091                                 write_c0_ebase(ebase | MIPS_EBASE_WG);
1092                         back_to_back_c0_hazard();
1093                         /* Restore BEV */
1094                         write_c0_status(status);
1095                         if (read_c0_ebase() & MIPS_EBASE_WG) {
1096                                 c->options |= MIPS_CPU_EBASE_WG;
1097                                 write_c0_ebase(ebase);
1098                         }
1099                 }
1100         }
1101
1102         /* configure the FTLB write probability */
1103         set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
1104
1105         mips_probe_watch_registers(c);
1106
1107 #ifndef CONFIG_MIPS_CPS
1108         if (cpu_has_mips_r2_r6) {
1109                 unsigned int core;
1110
1111                 core = get_ebase_cpunum();
1112                 if (cpu_has_mipsmt)
1113                         core >>= fls(core_nvpes()) - 1;
1114                 cpu_set_core(c, core);
1115         }
1116 #endif
1117 }
1118
1119 /*
1120  * Probe for certain guest capabilities by writing config bits and reading back.
1121  * Finally write back the original value.
1122  */
1123 #define probe_gc0_config(name, maxconf, bits)                           \
1124 do {                                                                    \
1125         unsigned int tmp;                                               \
1126         tmp = read_gc0_##name();                                        \
1127         write_gc0_##name(tmp | (bits));                                 \
1128         back_to_back_c0_hazard();                                       \
1129         maxconf = read_gc0_##name();                                    \
1130         write_gc0_##name(tmp);                                          \
1131 } while (0)
1132
1133 /*
1134  * Probe for dynamic guest capabilities by changing certain config bits and
1135  * reading back to see if they change. Finally write back the original value.
1136  */
1137 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits)              \
1138 do {                                                                    \
1139         maxconf = read_gc0_##name();                                    \
1140         write_gc0_##name(maxconf ^ (bits));                             \
1141         back_to_back_c0_hazard();                                       \
1142         dynconf = maxconf ^ read_gc0_##name();                          \
1143         write_gc0_##name(maxconf);                                      \
1144         maxconf |= dynconf;                                             \
1145 } while (0)
1146
1147 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1148 {
1149         unsigned int config0;
1150
1151         probe_gc0_config(config, config0, MIPS_CONF_M);
1152
1153         if (config0 & MIPS_CONF_M)
1154                 c->guest.conf |= BIT(1);
1155         return config0 & MIPS_CONF_M;
1156 }
1157
1158 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1159 {
1160         unsigned int config1, config1_dyn;
1161
1162         probe_gc0_config_dyn(config1, config1, config1_dyn,
1163                              MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1164                              MIPS_CONF1_FP);
1165
1166         if (config1 & MIPS_CONF1_FP)
1167                 c->guest.options |= MIPS_CPU_FPU;
1168         if (config1_dyn & MIPS_CONF1_FP)
1169                 c->guest.options_dyn |= MIPS_CPU_FPU;
1170
1171         if (config1 & MIPS_CONF1_WR)
1172                 c->guest.options |= MIPS_CPU_WATCH;
1173         if (config1_dyn & MIPS_CONF1_WR)
1174                 c->guest.options_dyn |= MIPS_CPU_WATCH;
1175
1176         if (config1 & MIPS_CONF1_PC)
1177                 c->guest.options |= MIPS_CPU_PERF;
1178         if (config1_dyn & MIPS_CONF1_PC)
1179                 c->guest.options_dyn |= MIPS_CPU_PERF;
1180
1181         if (config1 & MIPS_CONF_M)
1182                 c->guest.conf |= BIT(2);
1183         return config1 & MIPS_CONF_M;
1184 }
1185
1186 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1187 {
1188         unsigned int config2;
1189
1190         probe_gc0_config(config2, config2, MIPS_CONF_M);
1191
1192         if (config2 & MIPS_CONF_M)
1193                 c->guest.conf |= BIT(3);
1194         return config2 & MIPS_CONF_M;
1195 }
1196
1197 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1198 {
1199         unsigned int config3, config3_dyn;
1200
1201         probe_gc0_config_dyn(config3, config3, config3_dyn,
1202                              MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1203                              MIPS_CONF3_CTXTC);
1204
1205         if (config3 & MIPS_CONF3_CTXTC)
1206                 c->guest.options |= MIPS_CPU_CTXTC;
1207         if (config3_dyn & MIPS_CONF3_CTXTC)
1208                 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1209
1210         if (config3 & MIPS_CONF3_PW)
1211                 c->guest.options |= MIPS_CPU_HTW;
1212
1213         if (config3 & MIPS_CONF3_ULRI)
1214                 c->guest.options |= MIPS_CPU_ULRI;
1215
1216         if (config3 & MIPS_CONF3_SC)
1217                 c->guest.options |= MIPS_CPU_SEGMENTS;
1218
1219         if (config3 & MIPS_CONF3_BI)
1220                 c->guest.options |= MIPS_CPU_BADINSTR;
1221         if (config3 & MIPS_CONF3_BP)
1222                 c->guest.options |= MIPS_CPU_BADINSTRP;
1223
1224         if (config3 & MIPS_CONF3_MSA)
1225                 c->guest.ases |= MIPS_ASE_MSA;
1226         if (config3_dyn & MIPS_CONF3_MSA)
1227                 c->guest.ases_dyn |= MIPS_ASE_MSA;
1228
1229         if (config3 & MIPS_CONF_M)
1230                 c->guest.conf |= BIT(4);
1231         return config3 & MIPS_CONF_M;
1232 }
1233
1234 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1235 {
1236         unsigned int config4;
1237
1238         probe_gc0_config(config4, config4,
1239                          MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1240
1241         c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1242                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
1243
1244         if (config4 & MIPS_CONF_M)
1245                 c->guest.conf |= BIT(5);
1246         return config4 & MIPS_CONF_M;
1247 }
1248
1249 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1250 {
1251         unsigned int config5, config5_dyn;
1252
1253         probe_gc0_config_dyn(config5, config5, config5_dyn,
1254                          MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1255
1256         if (config5 & MIPS_CONF5_MRP)
1257                 c->guest.options |= MIPS_CPU_MAAR;
1258         if (config5_dyn & MIPS_CONF5_MRP)
1259                 c->guest.options_dyn |= MIPS_CPU_MAAR;
1260
1261         if (config5 & MIPS_CONF5_LLB)
1262                 c->guest.options |= MIPS_CPU_RW_LLB;
1263
1264         if (config5 & MIPS_CONF5_MVH)
1265                 c->guest.options |= MIPS_CPU_MVH;
1266
1267         if (config5 & MIPS_CONF_M)
1268                 c->guest.conf |= BIT(6);
1269         return config5 & MIPS_CONF_M;
1270 }
1271
1272 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1273 {
1274         unsigned int ok;
1275
1276         ok = decode_guest_config0(c);
1277         if (ok)
1278                 ok = decode_guest_config1(c);
1279         if (ok)
1280                 ok = decode_guest_config2(c);
1281         if (ok)
1282                 ok = decode_guest_config3(c);
1283         if (ok)
1284                 ok = decode_guest_config4(c);
1285         if (ok)
1286                 decode_guest_config5(c);
1287 }
1288
1289 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1290 {
1291         unsigned int guestctl0, temp;
1292
1293         guestctl0 = read_c0_guestctl0();
1294
1295         if (guestctl0 & MIPS_GCTL0_G0E)
1296                 c->options |= MIPS_CPU_GUESTCTL0EXT;
1297         if (guestctl0 & MIPS_GCTL0_G1)
1298                 c->options |= MIPS_CPU_GUESTCTL1;
1299         if (guestctl0 & MIPS_GCTL0_G2)
1300                 c->options |= MIPS_CPU_GUESTCTL2;
1301         if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1302                 c->options |= MIPS_CPU_GUESTID;
1303
1304                 /*
1305                  * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1306                  * first, otherwise all data accesses will be fully virtualised
1307                  * as if they were performed by guest mode.
1308                  */
1309                 write_c0_guestctl1(0);
1310                 tlbw_use_hazard();
1311
1312                 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1313                 back_to_back_c0_hazard();
1314                 temp = read_c0_guestctl0();
1315
1316                 if (temp & MIPS_GCTL0_DRG) {
1317                         write_c0_guestctl0(guestctl0);
1318                         c->options |= MIPS_CPU_DRG;
1319                 }
1320         }
1321 }
1322
1323 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1324 {
1325         if (cpu_has_guestid) {
1326                 /* determine the number of bits of GuestID available */
1327                 write_c0_guestctl1(MIPS_GCTL1_ID);
1328                 back_to_back_c0_hazard();
1329                 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1330                                                 >> MIPS_GCTL1_ID_SHIFT;
1331                 write_c0_guestctl1(0);
1332         }
1333 }
1334
1335 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1336 {
1337         /* determine the number of bits of GTOffset available */
1338         write_c0_gtoffset(0xffffffff);
1339         back_to_back_c0_hazard();
1340         c->gtoffset_mask = read_c0_gtoffset();
1341         write_c0_gtoffset(0);
1342 }
1343
1344 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1345 {
1346         cpu_probe_guestctl0(c);
1347         if (cpu_has_guestctl1)
1348                 cpu_probe_guestctl1(c);
1349
1350         cpu_probe_gtoffset(c);
1351
1352         decode_guest_configs(c);
1353 }
1354
1355 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1356                 | MIPS_CPU_COUNTER)
1357
1358 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1359 {
1360         switch (c->processor_id & PRID_IMP_MASK) {
1361         case PRID_IMP_R2000:
1362                 c->cputype = CPU_R2000;
1363                 __cpu_name[cpu] = "R2000";
1364                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1365                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1366                              MIPS_CPU_NOFPUEX;
1367                 if (__cpu_has_fpu())
1368                         c->options |= MIPS_CPU_FPU;
1369                 c->tlbsize = 64;
1370                 break;
1371         case PRID_IMP_R3000:
1372                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1373                         if (cpu_has_confreg()) {
1374                                 c->cputype = CPU_R3081E;
1375                                 __cpu_name[cpu] = "R3081";
1376                         } else {
1377                                 c->cputype = CPU_R3000A;
1378                                 __cpu_name[cpu] = "R3000A";
1379                         }
1380                 } else {
1381                         c->cputype = CPU_R3000;
1382                         __cpu_name[cpu] = "R3000";
1383                 }
1384                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1385                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1386                              MIPS_CPU_NOFPUEX;
1387                 if (__cpu_has_fpu())
1388                         c->options |= MIPS_CPU_FPU;
1389                 c->tlbsize = 64;
1390                 break;
1391         case PRID_IMP_R4000:
1392                 if (read_c0_config() & CONF_SC) {
1393                         if ((c->processor_id & PRID_REV_MASK) >=
1394                             PRID_REV_R4400) {
1395                                 c->cputype = CPU_R4400PC;
1396                                 __cpu_name[cpu] = "R4400PC";
1397                         } else {
1398                                 c->cputype = CPU_R4000PC;
1399                                 __cpu_name[cpu] = "R4000PC";
1400                         }
1401                 } else {
1402                         int cca = read_c0_config() & CONF_CM_CMASK;
1403                         int mc;
1404
1405                         /*
1406                          * SC and MC versions can't be reliably told apart,
1407                          * but only the latter support coherent caching
1408                          * modes so assume the firmware has set the KSEG0
1409                          * coherency attribute reasonably (if uncached, we
1410                          * assume SC).
1411                          */
1412                         switch (cca) {
1413                         case CONF_CM_CACHABLE_CE:
1414                         case CONF_CM_CACHABLE_COW:
1415                         case CONF_CM_CACHABLE_CUW:
1416                                 mc = 1;
1417                                 break;
1418                         default:
1419                                 mc = 0;
1420                                 break;
1421                         }
1422                         if ((c->processor_id & PRID_REV_MASK) >=
1423                             PRID_REV_R4400) {
1424                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1425                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1426                         } else {
1427                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1428                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1429                         }
1430                 }
1431
1432                 set_isa(c, MIPS_CPU_ISA_III);
1433                 c->fpu_msk31 |= FPU_CSR_CONDX;
1434                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1435                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
1436                              MIPS_CPU_LLSC;
1437                 c->tlbsize = 48;
1438                 break;
1439         case PRID_IMP_VR41XX:
1440                 set_isa(c, MIPS_CPU_ISA_III);
1441                 c->fpu_msk31 |= FPU_CSR_CONDX;
1442                 c->options = R4K_OPTS;
1443                 c->tlbsize = 32;
1444                 switch (c->processor_id & 0xf0) {
1445                 case PRID_REV_VR4111:
1446                         c->cputype = CPU_VR4111;
1447                         __cpu_name[cpu] = "NEC VR4111";
1448                         break;
1449                 case PRID_REV_VR4121:
1450                         c->cputype = CPU_VR4121;
1451                         __cpu_name[cpu] = "NEC VR4121";
1452                         break;
1453                 case PRID_REV_VR4122:
1454                         if ((c->processor_id & 0xf) < 0x3) {
1455                                 c->cputype = CPU_VR4122;
1456                                 __cpu_name[cpu] = "NEC VR4122";
1457                         } else {
1458                                 c->cputype = CPU_VR4181A;
1459                                 __cpu_name[cpu] = "NEC VR4181A";
1460                         }
1461                         break;
1462                 case PRID_REV_VR4130:
1463                         if ((c->processor_id & 0xf) < 0x4) {
1464                                 c->cputype = CPU_VR4131;
1465                                 __cpu_name[cpu] = "NEC VR4131";
1466                         } else {
1467                                 c->cputype = CPU_VR4133;
1468                                 c->options |= MIPS_CPU_LLSC;
1469                                 __cpu_name[cpu] = "NEC VR4133";
1470                         }
1471                         break;
1472                 default:
1473                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1474                         c->cputype = CPU_VR41XX;
1475                         __cpu_name[cpu] = "NEC Vr41xx";
1476                         break;
1477                 }
1478                 break;
1479         case PRID_IMP_R4600:
1480                 c->cputype = CPU_R4600;
1481                 __cpu_name[cpu] = "R4600";
1482                 set_isa(c, MIPS_CPU_ISA_III);
1483                 c->fpu_msk31 |= FPU_CSR_CONDX;
1484                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1485                              MIPS_CPU_LLSC;
1486                 c->tlbsize = 48;
1487                 break;
1488         #if 0
1489         case PRID_IMP_R4650:
1490                 /*
1491                  * This processor doesn't have an MMU, so it's not
1492                  * "real easy" to run Linux on it. It is left purely
1493                  * for documentation.  Commented out because it shares
1494                  * it's c0_prid id number with the TX3900.
1495                  */
1496                 c->cputype = CPU_R4650;
1497                 __cpu_name[cpu] = "R4650";
1498                 set_isa(c, MIPS_CPU_ISA_III);
1499                 c->fpu_msk31 |= FPU_CSR_CONDX;
1500                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1501                 c->tlbsize = 48;
1502                 break;
1503         #endif
1504         case PRID_IMP_TX39:
1505                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1506                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1507
1508                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1509                         c->cputype = CPU_TX3927;
1510                         __cpu_name[cpu] = "TX3927";
1511                         c->tlbsize = 64;
1512                 } else {
1513                         switch (c->processor_id & PRID_REV_MASK) {
1514                         case PRID_REV_TX3912:
1515                                 c->cputype = CPU_TX3912;
1516                                 __cpu_name[cpu] = "TX3912";
1517                                 c->tlbsize = 32;
1518                                 break;
1519                         case PRID_REV_TX3922:
1520                                 c->cputype = CPU_TX3922;
1521                                 __cpu_name[cpu] = "TX3922";
1522                                 c->tlbsize = 64;
1523                                 break;
1524                         }
1525                 }
1526                 break;
1527         case PRID_IMP_R4700:
1528                 c->cputype = CPU_R4700;
1529                 __cpu_name[cpu] = "R4700";
1530                 set_isa(c, MIPS_CPU_ISA_III);
1531                 c->fpu_msk31 |= FPU_CSR_CONDX;
1532                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1533                              MIPS_CPU_LLSC;
1534                 c->tlbsize = 48;
1535                 break;
1536         case PRID_IMP_TX49:
1537                 c->cputype = CPU_TX49XX;
1538                 __cpu_name[cpu] = "R49XX";
1539                 set_isa(c, MIPS_CPU_ISA_III);
1540                 c->fpu_msk31 |= FPU_CSR_CONDX;
1541                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1542                 if (!(c->processor_id & 0x08))
1543                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1544                 c->tlbsize = 48;
1545                 break;
1546         case PRID_IMP_R5000:
1547                 c->cputype = CPU_R5000;
1548                 __cpu_name[cpu] = "R5000";
1549                 set_isa(c, MIPS_CPU_ISA_IV);
1550                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1551                              MIPS_CPU_LLSC;
1552                 c->tlbsize = 48;
1553                 break;
1554         case PRID_IMP_R5500:
1555                 c->cputype = CPU_R5500;
1556                 __cpu_name[cpu] = "R5500";
1557                 set_isa(c, MIPS_CPU_ISA_IV);
1558                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1559                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1560                 c->tlbsize = 48;
1561                 break;
1562         case PRID_IMP_NEVADA:
1563                 c->cputype = CPU_NEVADA;
1564                 __cpu_name[cpu] = "Nevada";
1565                 set_isa(c, MIPS_CPU_ISA_IV);
1566                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1567                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1568                 c->tlbsize = 48;
1569                 break;
1570         case PRID_IMP_RM7000:
1571                 c->cputype = CPU_RM7000;
1572                 __cpu_name[cpu] = "RM7000";
1573                 set_isa(c, MIPS_CPU_ISA_IV);
1574                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1575                              MIPS_CPU_LLSC;
1576                 /*
1577                  * Undocumented RM7000:  Bit 29 in the info register of
1578                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
1579                  * entries.
1580                  *
1581                  * 29      1 =>    64 entry JTLB
1582                  *         0 =>    48 entry JTLB
1583                  */
1584                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1585                 break;
1586         case PRID_IMP_R10000:
1587                 c->cputype = CPU_R10000;
1588                 __cpu_name[cpu] = "R10000";
1589                 set_isa(c, MIPS_CPU_ISA_IV);
1590                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1591                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1592                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1593                              MIPS_CPU_LLSC;
1594                 c->tlbsize = 64;
1595                 break;
1596         case PRID_IMP_R12000:
1597                 c->cputype = CPU_R12000;
1598                 __cpu_name[cpu] = "R12000";
1599                 set_isa(c, MIPS_CPU_ISA_IV);
1600                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1601                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1602                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1603                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1604                 c->tlbsize = 64;
1605                 break;
1606         case PRID_IMP_R14000:
1607                 if (((c->processor_id >> 4) & 0x0f) > 2) {
1608                         c->cputype = CPU_R16000;
1609                         __cpu_name[cpu] = "R16000";
1610                 } else {
1611                         c->cputype = CPU_R14000;
1612                         __cpu_name[cpu] = "R14000";
1613                 }
1614                 set_isa(c, MIPS_CPU_ISA_IV);
1615                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1616                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1617                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1618                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1619                 c->tlbsize = 64;
1620                 break;
1621         case PRID_IMP_LOONGSON_64C:  /* Loongson-2/3 */
1622                 switch (c->processor_id & PRID_REV_MASK) {
1623                 case PRID_REV_LOONGSON2E:
1624                         c->cputype = CPU_LOONGSON2EF;
1625                         __cpu_name[cpu] = "ICT Loongson-2";
1626                         set_elf_platform(cpu, "loongson2e");
1627                         set_isa(c, MIPS_CPU_ISA_III);
1628                         c->fpu_msk31 |= FPU_CSR_CONDX;
1629                         break;
1630                 case PRID_REV_LOONGSON2F:
1631                         c->cputype = CPU_LOONGSON2EF;
1632                         __cpu_name[cpu] = "ICT Loongson-2";
1633                         set_elf_platform(cpu, "loongson2f");
1634                         set_isa(c, MIPS_CPU_ISA_III);
1635                         c->fpu_msk31 |= FPU_CSR_CONDX;
1636                         break;
1637                 case PRID_REV_LOONGSON3A_R1:
1638                         c->cputype = CPU_LOONGSON64;
1639                         __cpu_name[cpu] = "ICT Loongson-3";
1640                         set_elf_platform(cpu, "loongson3a");
1641                         set_isa(c, MIPS_CPU_ISA_M64R1);
1642                         c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1643                                 MIPS_ASE_LOONGSON_EXT);
1644                         break;
1645                 case PRID_REV_LOONGSON3B_R1:
1646                 case PRID_REV_LOONGSON3B_R2:
1647                         c->cputype = CPU_LOONGSON64;
1648                         __cpu_name[cpu] = "ICT Loongson-3";
1649                         set_elf_platform(cpu, "loongson3b");
1650                         set_isa(c, MIPS_CPU_ISA_M64R1);
1651                         c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1652                                 MIPS_ASE_LOONGSON_EXT);
1653                         break;
1654                 }
1655
1656                 c->options = R4K_OPTS |
1657                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1658                              MIPS_CPU_32FPR;
1659                 c->tlbsize = 64;
1660                 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1661                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1662                 break;
1663         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1664                 decode_configs(c);
1665
1666                 c->cputype = CPU_LOONGSON32;
1667
1668                 switch (c->processor_id & PRID_REV_MASK) {
1669                 case PRID_REV_LOONGSON1B:
1670                         __cpu_name[cpu] = "Loongson 1B";
1671                         break;
1672                 }
1673
1674                 break;
1675         }
1676 }
1677
1678 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1679 {
1680         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1681         switch (c->processor_id & PRID_IMP_MASK) {
1682         case PRID_IMP_QEMU_GENERIC:
1683                 c->writecombine = _CACHE_UNCACHED;
1684                 c->cputype = CPU_QEMU_GENERIC;
1685                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1686                 break;
1687         case PRID_IMP_4KC:
1688                 c->cputype = CPU_4KC;
1689                 c->writecombine = _CACHE_UNCACHED;
1690                 __cpu_name[cpu] = "MIPS 4Kc";
1691                 break;
1692         case PRID_IMP_4KEC:
1693         case PRID_IMP_4KECR2:
1694                 c->cputype = CPU_4KEC;
1695                 c->writecombine = _CACHE_UNCACHED;
1696                 __cpu_name[cpu] = "MIPS 4KEc";
1697                 break;
1698         case PRID_IMP_4KSC:
1699         case PRID_IMP_4KSD:
1700                 c->cputype = CPU_4KSC;
1701                 c->writecombine = _CACHE_UNCACHED;
1702                 __cpu_name[cpu] = "MIPS 4KSc";
1703                 break;
1704         case PRID_IMP_5KC:
1705                 c->cputype = CPU_5KC;
1706                 c->writecombine = _CACHE_UNCACHED;
1707                 __cpu_name[cpu] = "MIPS 5Kc";
1708                 break;
1709         case PRID_IMP_5KE:
1710                 c->cputype = CPU_5KE;
1711                 c->writecombine = _CACHE_UNCACHED;
1712                 __cpu_name[cpu] = "MIPS 5KE";
1713                 break;
1714         case PRID_IMP_20KC:
1715                 c->cputype = CPU_20KC;
1716                 c->writecombine = _CACHE_UNCACHED;
1717                 __cpu_name[cpu] = "MIPS 20Kc";
1718                 break;
1719         case PRID_IMP_24K:
1720                 c->cputype = CPU_24K;
1721                 c->writecombine = _CACHE_UNCACHED;
1722                 __cpu_name[cpu] = "MIPS 24Kc";
1723                 break;
1724         case PRID_IMP_24KE:
1725                 c->cputype = CPU_24K;
1726                 c->writecombine = _CACHE_UNCACHED;
1727                 __cpu_name[cpu] = "MIPS 24KEc";
1728                 break;
1729         case PRID_IMP_25KF:
1730                 c->cputype = CPU_25KF;
1731                 c->writecombine = _CACHE_UNCACHED;
1732                 __cpu_name[cpu] = "MIPS 25Kc";
1733                 break;
1734         case PRID_IMP_34K:
1735                 c->cputype = CPU_34K;
1736                 c->writecombine = _CACHE_UNCACHED;
1737                 __cpu_name[cpu] = "MIPS 34Kc";
1738                 cpu_set_mt_per_tc_perf(c);
1739                 break;
1740         case PRID_IMP_74K:
1741                 c->cputype = CPU_74K;
1742                 c->writecombine = _CACHE_UNCACHED;
1743                 __cpu_name[cpu] = "MIPS 74Kc";
1744                 break;
1745         case PRID_IMP_M14KC:
1746                 c->cputype = CPU_M14KC;
1747                 c->writecombine = _CACHE_UNCACHED;
1748                 __cpu_name[cpu] = "MIPS M14Kc";
1749                 break;
1750         case PRID_IMP_M14KEC:
1751                 c->cputype = CPU_M14KEC;
1752                 c->writecombine = _CACHE_UNCACHED;
1753                 __cpu_name[cpu] = "MIPS M14KEc";
1754                 break;
1755         case PRID_IMP_1004K:
1756                 c->cputype = CPU_1004K;
1757                 c->writecombine = _CACHE_UNCACHED;
1758                 __cpu_name[cpu] = "MIPS 1004Kc";
1759                 cpu_set_mt_per_tc_perf(c);
1760                 break;
1761         case PRID_IMP_1074K:
1762                 c->cputype = CPU_1074K;
1763                 c->writecombine = _CACHE_UNCACHED;
1764                 __cpu_name[cpu] = "MIPS 1074Kc";
1765                 break;
1766         case PRID_IMP_INTERAPTIV_UP:
1767                 c->cputype = CPU_INTERAPTIV;
1768                 __cpu_name[cpu] = "MIPS interAptiv";
1769                 cpu_set_mt_per_tc_perf(c);
1770                 break;
1771         case PRID_IMP_INTERAPTIV_MP:
1772                 c->cputype = CPU_INTERAPTIV;
1773                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1774                 cpu_set_mt_per_tc_perf(c);
1775                 break;
1776         case PRID_IMP_PROAPTIV_UP:
1777                 c->cputype = CPU_PROAPTIV;
1778                 __cpu_name[cpu] = "MIPS proAptiv";
1779                 break;
1780         case PRID_IMP_PROAPTIV_MP:
1781                 c->cputype = CPU_PROAPTIV;
1782                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1783                 break;
1784         case PRID_IMP_P5600:
1785                 c->cputype = CPU_P5600;
1786                 __cpu_name[cpu] = "MIPS P5600";
1787                 break;
1788         case PRID_IMP_P6600:
1789                 c->cputype = CPU_P6600;
1790                 __cpu_name[cpu] = "MIPS P6600";
1791                 break;
1792         case PRID_IMP_I6400:
1793                 c->cputype = CPU_I6400;
1794                 __cpu_name[cpu] = "MIPS I6400";
1795                 break;
1796         case PRID_IMP_I6500:
1797                 c->cputype = CPU_I6500;
1798                 __cpu_name[cpu] = "MIPS I6500";
1799                 break;
1800         case PRID_IMP_M5150:
1801                 c->cputype = CPU_M5150;
1802                 __cpu_name[cpu] = "MIPS M5150";
1803                 break;
1804         case PRID_IMP_M6250:
1805                 c->cputype = CPU_M6250;
1806                 __cpu_name[cpu] = "MIPS M6250";
1807                 break;
1808         }
1809
1810         decode_configs(c);
1811
1812         spram_config();
1813
1814         mm_config(c);
1815
1816         switch (__get_cpu_type(c->cputype)) {
1817         case CPU_M5150:
1818         case CPU_P5600:
1819                 set_isa(c, MIPS_CPU_ISA_M32R5);
1820                 break;
1821         case CPU_I6500:
1822                 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1823                 fallthrough;
1824         case CPU_I6400:
1825                 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1826                 fallthrough;
1827         default:
1828                 break;
1829         }
1830 }
1831
1832 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1833 {
1834         decode_configs(c);
1835         switch (c->processor_id & PRID_IMP_MASK) {
1836         case PRID_IMP_AU1_REV1:
1837         case PRID_IMP_AU1_REV2:
1838                 c->cputype = CPU_ALCHEMY;
1839                 switch ((c->processor_id >> 24) & 0xff) {
1840                 case 0:
1841                         __cpu_name[cpu] = "Au1000";
1842                         break;
1843                 case 1:
1844                         __cpu_name[cpu] = "Au1500";
1845                         break;
1846                 case 2:
1847                         __cpu_name[cpu] = "Au1100";
1848                         break;
1849                 case 3:
1850                         __cpu_name[cpu] = "Au1550";
1851                         break;
1852                 case 4:
1853                         __cpu_name[cpu] = "Au1200";
1854                         if ((c->processor_id & PRID_REV_MASK) == 2)
1855                                 __cpu_name[cpu] = "Au1250";
1856                         break;
1857                 case 5:
1858                         __cpu_name[cpu] = "Au1210";
1859                         break;
1860                 default:
1861                         __cpu_name[cpu] = "Au1xxx";
1862                         break;
1863                 }
1864                 break;
1865         }
1866 }
1867
1868 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1869 {
1870         decode_configs(c);
1871
1872         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1873         switch (c->processor_id & PRID_IMP_MASK) {
1874         case PRID_IMP_SB1:
1875                 c->cputype = CPU_SB1;
1876                 __cpu_name[cpu] = "SiByte SB1";
1877                 /* FPU in pass1 is known to have issues. */
1878                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1879                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1880                 break;
1881         case PRID_IMP_SB1A:
1882                 c->cputype = CPU_SB1A;
1883                 __cpu_name[cpu] = "SiByte SB1A";
1884                 break;
1885         }
1886 }
1887
1888 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1889 {
1890         decode_configs(c);
1891         switch (c->processor_id & PRID_IMP_MASK) {
1892         case PRID_IMP_SR71000:
1893                 c->cputype = CPU_SR71000;
1894                 __cpu_name[cpu] = "Sandcraft SR71000";
1895                 c->scache.ways = 8;
1896                 c->tlbsize = 64;
1897                 break;
1898         }
1899 }
1900
1901 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1902 {
1903         decode_configs(c);
1904         switch (c->processor_id & PRID_IMP_MASK) {
1905         case PRID_IMP_PR4450:
1906                 c->cputype = CPU_PR4450;
1907                 __cpu_name[cpu] = "Philips PR4450";
1908                 set_isa(c, MIPS_CPU_ISA_M32R1);
1909                 break;
1910         }
1911 }
1912
1913 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1914 {
1915         decode_configs(c);
1916         switch (c->processor_id & PRID_IMP_MASK) {
1917         case PRID_IMP_BMIPS32_REV4:
1918         case PRID_IMP_BMIPS32_REV8:
1919                 c->cputype = CPU_BMIPS32;
1920                 __cpu_name[cpu] = "Broadcom BMIPS32";
1921                 set_elf_platform(cpu, "bmips32");
1922                 break;
1923         case PRID_IMP_BMIPS3300:
1924         case PRID_IMP_BMIPS3300_ALT:
1925         case PRID_IMP_BMIPS3300_BUG:
1926                 c->cputype = CPU_BMIPS3300;
1927                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1928                 set_elf_platform(cpu, "bmips3300");
1929                 break;
1930         case PRID_IMP_BMIPS43XX: {
1931                 int rev = c->processor_id & PRID_REV_MASK;
1932
1933                 if (rev >= PRID_REV_BMIPS4380_LO &&
1934                                 rev <= PRID_REV_BMIPS4380_HI) {
1935                         c->cputype = CPU_BMIPS4380;
1936                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1937                         set_elf_platform(cpu, "bmips4380");
1938                         c->options |= MIPS_CPU_RIXI;
1939                 } else {
1940                         c->cputype = CPU_BMIPS4350;
1941                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1942                         set_elf_platform(cpu, "bmips4350");
1943                 }
1944                 break;
1945         }
1946         case PRID_IMP_BMIPS5000:
1947         case PRID_IMP_BMIPS5200:
1948                 c->cputype = CPU_BMIPS5000;
1949                 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1950                         __cpu_name[cpu] = "Broadcom BMIPS5200";
1951                 else
1952                         __cpu_name[cpu] = "Broadcom BMIPS5000";
1953                 set_elf_platform(cpu, "bmips5000");
1954                 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1955                 break;
1956         }
1957 }
1958
1959 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1960 {
1961         decode_configs(c);
1962         switch (c->processor_id & PRID_IMP_MASK) {
1963         case PRID_IMP_CAVIUM_CN38XX:
1964         case PRID_IMP_CAVIUM_CN31XX:
1965         case PRID_IMP_CAVIUM_CN30XX:
1966                 c->cputype = CPU_CAVIUM_OCTEON;
1967                 __cpu_name[cpu] = "Cavium Octeon";
1968                 goto platform;
1969         case PRID_IMP_CAVIUM_CN58XX:
1970         case PRID_IMP_CAVIUM_CN56XX:
1971         case PRID_IMP_CAVIUM_CN50XX:
1972         case PRID_IMP_CAVIUM_CN52XX:
1973                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1974                 __cpu_name[cpu] = "Cavium Octeon+";
1975 platform:
1976                 set_elf_platform(cpu, "octeon");
1977                 break;
1978         case PRID_IMP_CAVIUM_CN61XX:
1979         case PRID_IMP_CAVIUM_CN63XX:
1980         case PRID_IMP_CAVIUM_CN66XX:
1981         case PRID_IMP_CAVIUM_CN68XX:
1982         case PRID_IMP_CAVIUM_CNF71XX:
1983                 c->cputype = CPU_CAVIUM_OCTEON2;
1984                 __cpu_name[cpu] = "Cavium Octeon II";
1985                 set_elf_platform(cpu, "octeon2");
1986                 break;
1987         case PRID_IMP_CAVIUM_CN70XX:
1988         case PRID_IMP_CAVIUM_CN73XX:
1989         case PRID_IMP_CAVIUM_CNF75XX:
1990         case PRID_IMP_CAVIUM_CN78XX:
1991                 c->cputype = CPU_CAVIUM_OCTEON3;
1992                 __cpu_name[cpu] = "Cavium Octeon III";
1993                 set_elf_platform(cpu, "octeon3");
1994                 break;
1995         default:
1996                 printk(KERN_INFO "Unknown Octeon chip!\n");
1997                 c->cputype = CPU_UNKNOWN;
1998                 break;
1999         }
2000 }
2001
2002 #ifdef CONFIG_CPU_LOONGSON64
2003 #include <loongson_regs.h>
2004
2005 static inline void decode_cpucfg(struct cpuinfo_mips *c)
2006 {
2007         u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
2008         u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
2009         u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
2010
2011         if (cfg1 & LOONGSON_CFG1_MMI)
2012                 c->ases |= MIPS_ASE_LOONGSON_MMI;
2013
2014         if (cfg2 & LOONGSON_CFG2_LEXT1)
2015                 c->ases |= MIPS_ASE_LOONGSON_EXT;
2016
2017         if (cfg2 & LOONGSON_CFG2_LEXT2)
2018                 c->ases |= MIPS_ASE_LOONGSON_EXT2;
2019
2020         if (cfg2 & LOONGSON_CFG2_LSPW)
2021                 c->options |= MIPS_CPU_LDPTE;
2022
2023         if (cfg3 & LOONGSON_CFG3_LCAMP)
2024                 c->ases |= MIPS_ASE_LOONGSON_CAM;
2025 }
2026
2027 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
2028 {
2029         decode_configs(c);
2030
2031         switch (c->processor_id & PRID_IMP_MASK) {
2032         case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
2033                 switch (c->processor_id & PRID_REV_MASK) {
2034                 case PRID_REV_LOONGSON2K_R1_0:
2035                 case PRID_REV_LOONGSON2K_R1_1:
2036                 case PRID_REV_LOONGSON2K_R1_2:
2037                 case PRID_REV_LOONGSON2K_R1_3:
2038                         c->cputype = CPU_LOONGSON64;
2039                         __cpu_name[cpu] = "Loongson-2K";
2040                         set_elf_platform(cpu, "gs264e");
2041                         set_isa(c, MIPS_CPU_ISA_M64R2);
2042                         break;
2043                 }
2044                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2045                 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
2046                                 MIPS_ASE_LOONGSON_EXT2);
2047                 break;
2048         case PRID_IMP_LOONGSON_64C:  /* Loongson-3 Classic */
2049                 switch (c->processor_id & PRID_REV_MASK) {
2050                 case PRID_REV_LOONGSON3A_R2_0:
2051                 case PRID_REV_LOONGSON3A_R2_1:
2052                         c->cputype = CPU_LOONGSON64;
2053                         __cpu_name[cpu] = "ICT Loongson-3";
2054                         set_elf_platform(cpu, "loongson3a");
2055                         set_isa(c, MIPS_CPU_ISA_M64R2);
2056                         break;
2057                 case PRID_REV_LOONGSON3A_R3_0:
2058                 case PRID_REV_LOONGSON3A_R3_1:
2059                         c->cputype = CPU_LOONGSON64;
2060                         __cpu_name[cpu] = "ICT Loongson-3";
2061                         set_elf_platform(cpu, "loongson3a");
2062                         set_isa(c, MIPS_CPU_ISA_M64R2);
2063                         break;
2064                 }
2065                 /*
2066                  * Loongson-3 Classic did not implement MIPS standard TLBINV
2067                  * but implemented TLBINVF and EHINV. As currently we're only
2068                  * using these two features, enable MIPS_CPU_TLBINV as well.
2069                  *
2070                  * Also some early Loongson-3A2000 had wrong TLB type in Config
2071                  * register, we correct it here.
2072                  */
2073                 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
2074                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2075                 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
2076                         MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
2077                 break;
2078         case PRID_IMP_LOONGSON_64G:
2079                 c->cputype = CPU_LOONGSON64;
2080                 __cpu_name[cpu] = "ICT Loongson-3";
2081                 set_elf_platform(cpu, "loongson3a");
2082                 set_isa(c, MIPS_CPU_ISA_M64R2);
2083                 decode_cpucfg(c);
2084                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2085                 break;
2086         default:
2087                 panic("Unknown Loongson Processor ID!");
2088                 break;
2089         }
2090 }
2091 #else
2092 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
2093 #endif
2094
2095 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
2096 {
2097         decode_configs(c);
2098
2099         /*
2100          * XBurst misses a config2 register, so config3 decode was skipped in
2101          * decode_configs().
2102          */
2103         decode_config3(c);
2104
2105         /* XBurst does not implement the CP0 counter. */
2106         c->options &= ~MIPS_CPU_COUNTER;
2107         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
2108
2109         switch (c->processor_id & PRID_IMP_MASK) {
2110         case PRID_IMP_XBURST_REV1:
2111
2112                 /*
2113                  * The XBurst core by default attempts to avoid branch target
2114                  * buffer lookups by detecting & special casing loops. This
2115                  * feature will cause BogoMIPS and lpj calculate in error.
2116                  * Set cp0 config7 bit 4 to disable this feature.
2117                  */
2118                 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
2119
2120                 switch (c->processor_id & PRID_COMP_MASK) {
2121
2122                 /*
2123                  * The config0 register in the XBurst CPUs with a processor ID of
2124                  * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
2125                  * but they don't actually support this ISA.
2126                  */
2127                 case PRID_COMP_INGENIC_D0:
2128                         c->isa_level &= ~MIPS_CPU_ISA_M32R2;
2129                         break;
2130
2131                 /*
2132                  * The config0 register in the XBurst CPUs with a processor ID of
2133                  * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
2134                  * mode is not compatible with the MIPS standard, it will cause
2135                  * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
2136                  * when starting the init process. After chip reset, the default
2137                  * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
2138                  * switch back to VTLB mode to prevent getting stuck.
2139                  */
2140                 case PRID_COMP_INGENIC_D1:
2141                         write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
2142                         break;
2143
2144                 default:
2145                         break;
2146                 }
2147                 fallthrough;
2148         case PRID_IMP_XBURST_REV2:
2149                 c->cputype = CPU_XBURST;
2150                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2151                 __cpu_name[cpu] = "Ingenic XBurst";
2152                 break;
2153
2154         default:
2155                 panic("Unknown Ingenic Processor ID!");
2156                 break;
2157         }
2158 }
2159
2160 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
2161 {
2162         decode_configs(c);
2163
2164         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
2165                 c->cputype = CPU_ALCHEMY;
2166                 __cpu_name[cpu] = "Au1300";
2167                 /* following stuff is not for Alchemy */
2168                 return;
2169         }
2170
2171         c->options = (MIPS_CPU_TLB       |
2172                         MIPS_CPU_4KEX    |
2173                         MIPS_CPU_COUNTER |
2174                         MIPS_CPU_DIVEC   |
2175                         MIPS_CPU_WATCH   |
2176                         MIPS_CPU_EJTAG   |
2177                         MIPS_CPU_LLSC);
2178
2179         switch (c->processor_id & PRID_IMP_MASK) {
2180         case PRID_IMP_NETLOGIC_XLP2XX:
2181         case PRID_IMP_NETLOGIC_XLP9XX:
2182         case PRID_IMP_NETLOGIC_XLP5XX:
2183                 c->cputype = CPU_XLP;
2184                 __cpu_name[cpu] = "Broadcom XLPII";
2185                 break;
2186
2187         case PRID_IMP_NETLOGIC_XLP8XX:
2188         case PRID_IMP_NETLOGIC_XLP3XX:
2189                 c->cputype = CPU_XLP;
2190                 __cpu_name[cpu] = "Netlogic XLP";
2191                 break;
2192
2193         case PRID_IMP_NETLOGIC_XLR732:
2194         case PRID_IMP_NETLOGIC_XLR716:
2195         case PRID_IMP_NETLOGIC_XLR532:
2196         case PRID_IMP_NETLOGIC_XLR308:
2197         case PRID_IMP_NETLOGIC_XLR532C:
2198         case PRID_IMP_NETLOGIC_XLR516C:
2199         case PRID_IMP_NETLOGIC_XLR508C:
2200         case PRID_IMP_NETLOGIC_XLR308C:
2201                 c->cputype = CPU_XLR;
2202                 __cpu_name[cpu] = "Netlogic XLR";
2203                 break;
2204
2205         case PRID_IMP_NETLOGIC_XLS608:
2206         case PRID_IMP_NETLOGIC_XLS408:
2207         case PRID_IMP_NETLOGIC_XLS404:
2208         case PRID_IMP_NETLOGIC_XLS208:
2209         case PRID_IMP_NETLOGIC_XLS204:
2210         case PRID_IMP_NETLOGIC_XLS108:
2211         case PRID_IMP_NETLOGIC_XLS104:
2212         case PRID_IMP_NETLOGIC_XLS616B:
2213         case PRID_IMP_NETLOGIC_XLS608B:
2214         case PRID_IMP_NETLOGIC_XLS416B:
2215         case PRID_IMP_NETLOGIC_XLS412B:
2216         case PRID_IMP_NETLOGIC_XLS408B:
2217         case PRID_IMP_NETLOGIC_XLS404B:
2218                 c->cputype = CPU_XLR;
2219                 __cpu_name[cpu] = "Netlogic XLS";
2220                 break;
2221
2222         default:
2223                 pr_info("Unknown Netlogic chip id [%02x]!\n",
2224                        c->processor_id);
2225                 c->cputype = CPU_XLR;
2226                 break;
2227         }
2228
2229         if (c->cputype == CPU_XLP) {
2230                 set_isa(c, MIPS_CPU_ISA_M64R2);
2231                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
2232                 /* This will be updated again after all threads are woken up */
2233                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2234         } else {
2235                 set_isa(c, MIPS_CPU_ISA_M64R1);
2236                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2237         }
2238         c->kscratch_mask = 0xf;
2239 }
2240
2241 #ifdef CONFIG_64BIT
2242 /* For use by uaccess.h */
2243 u64 __ua_limit;
2244 EXPORT_SYMBOL(__ua_limit);
2245 #endif
2246
2247 const char *__cpu_name[NR_CPUS];
2248 const char *__elf_platform;
2249 const char *__elf_base_platform;
2250
2251 void cpu_probe(void)
2252 {
2253         struct cpuinfo_mips *c = &current_cpu_data;
2254         unsigned int cpu = smp_processor_id();
2255
2256         /*
2257          * Set a default elf platform, cpu probe may later
2258          * overwrite it with a more precise value
2259          */
2260         set_elf_platform(cpu, "mips");
2261
2262         c->processor_id = PRID_IMP_UNKNOWN;
2263         c->fpu_id       = FPIR_IMP_NONE;
2264         c->cputype      = CPU_UNKNOWN;
2265         c->writecombine = _CACHE_UNCACHED;
2266
2267         c->fpu_csr31    = FPU_CSR_RN;
2268         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2269
2270         c->processor_id = read_c0_prid();
2271         switch (c->processor_id & PRID_COMP_MASK) {
2272         case PRID_COMP_LEGACY:
2273                 cpu_probe_legacy(c, cpu);
2274                 break;
2275         case PRID_COMP_MIPS:
2276                 cpu_probe_mips(c, cpu);
2277                 break;
2278         case PRID_COMP_ALCHEMY:
2279                 cpu_probe_alchemy(c, cpu);
2280                 break;
2281         case PRID_COMP_SIBYTE:
2282                 cpu_probe_sibyte(c, cpu);
2283                 break;
2284         case PRID_COMP_BROADCOM:
2285                 cpu_probe_broadcom(c, cpu);
2286                 break;
2287         case PRID_COMP_SANDCRAFT:
2288                 cpu_probe_sandcraft(c, cpu);
2289                 break;
2290         case PRID_COMP_NXP:
2291                 cpu_probe_nxp(c, cpu);
2292                 break;
2293         case PRID_COMP_CAVIUM:
2294                 cpu_probe_cavium(c, cpu);
2295                 break;
2296         case PRID_COMP_LOONGSON:
2297                 cpu_probe_loongson(c, cpu);
2298                 break;
2299         case PRID_COMP_INGENIC_D0:
2300         case PRID_COMP_INGENIC_D1:
2301         case PRID_COMP_INGENIC_E1:
2302                 cpu_probe_ingenic(c, cpu);
2303                 break;
2304         case PRID_COMP_NETLOGIC:
2305                 cpu_probe_netlogic(c, cpu);
2306                 break;
2307         }
2308
2309         BUG_ON(!__cpu_name[cpu]);
2310         BUG_ON(c->cputype == CPU_UNKNOWN);
2311
2312         /*
2313          * Platform code can force the cpu type to optimize code
2314          * generation. In that case be sure the cpu type is correctly
2315          * manually setup otherwise it could trigger some nasty bugs.
2316          */
2317         BUG_ON(current_cpu_type() != c->cputype);
2318
2319         if (cpu_has_rixi) {
2320                 /* Enable the RIXI exceptions */
2321                 set_c0_pagegrain(PG_IEC);
2322                 back_to_back_c0_hazard();
2323                 /* Verify the IEC bit is set */
2324                 if (read_c0_pagegrain() & PG_IEC)
2325                         c->options |= MIPS_CPU_RIXIEX;
2326         }
2327
2328         if (mips_fpu_disabled)
2329                 c->options &= ~MIPS_CPU_FPU;
2330
2331         if (mips_dsp_disabled)
2332                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2333
2334         if (mips_htw_disabled) {
2335                 c->options &= ~MIPS_CPU_HTW;
2336                 write_c0_pwctl(read_c0_pwctl() &
2337                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2338         }
2339
2340         if (c->options & MIPS_CPU_FPU)
2341                 cpu_set_fpu_opts(c);
2342         else
2343                 cpu_set_nofpu_opts(c);
2344
2345         if (cpu_has_bp_ghist)
2346                 write_c0_r10k_diag(read_c0_r10k_diag() |
2347                                    R10K_DIAG_E_GHIST);
2348
2349         if (cpu_has_mips_r2_r6) {
2350                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2351                 /* R2 has Performance Counter Interrupt indicator */
2352                 c->options |= MIPS_CPU_PCI;
2353         }
2354         else
2355                 c->srsets = 1;
2356
2357         if (cpu_has_mips_r6)
2358                 elf_hwcap |= HWCAP_MIPS_R6;
2359
2360         if (cpu_has_msa) {
2361                 c->msa_id = cpu_get_msa_id();
2362                 WARN(c->msa_id & MSA_IR_WRPF,
2363                      "Vector register partitioning unimplemented!");
2364                 elf_hwcap |= HWCAP_MIPS_MSA;
2365         }
2366
2367         if (cpu_has_mips16)
2368                 elf_hwcap |= HWCAP_MIPS_MIPS16;
2369
2370         if (cpu_has_mdmx)
2371                 elf_hwcap |= HWCAP_MIPS_MDMX;
2372
2373         if (cpu_has_mips3d)
2374                 elf_hwcap |= HWCAP_MIPS_MIPS3D;
2375
2376         if (cpu_has_smartmips)
2377                 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
2378
2379         if (cpu_has_dsp)
2380                 elf_hwcap |= HWCAP_MIPS_DSP;
2381
2382         if (cpu_has_dsp2)
2383                 elf_hwcap |= HWCAP_MIPS_DSP2;
2384
2385         if (cpu_has_dsp3)
2386                 elf_hwcap |= HWCAP_MIPS_DSP3;
2387
2388         if (cpu_has_mips16e2)
2389                 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
2390
2391         if (cpu_has_loongson_mmi)
2392                 elf_hwcap |= HWCAP_LOONGSON_MMI;
2393
2394         if (cpu_has_loongson_ext)
2395                 elf_hwcap |= HWCAP_LOONGSON_EXT;
2396
2397         if (cpu_has_loongson_ext2)
2398                 elf_hwcap |= HWCAP_LOONGSON_EXT2;
2399
2400         if (cpu_has_vz)
2401                 cpu_probe_vz(c);
2402
2403         cpu_probe_vmbits(c);
2404
2405         /* Synthesize CPUCFG data if running on Loongson processors;
2406          * no-op otherwise.
2407          *
2408          * This looks at previously probed features, so keep this at bottom.
2409          */
2410         loongson3_cpucfg_synthesize_data(c);
2411
2412 #ifdef CONFIG_64BIT
2413         if (cpu == 0)
2414                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2415 #endif
2416 }
2417
2418 void cpu_report(void)
2419 {
2420         struct cpuinfo_mips *c = &current_cpu_data;
2421
2422         pr_info("CPU%d revision is: %08x (%s)\n",
2423                 smp_processor_id(), c->processor_id, cpu_name_string());
2424         if (c->options & MIPS_CPU_FPU)
2425                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2426         if (cpu_has_msa)
2427                 pr_info("MSA revision is: %08x\n", c->msa_id);
2428 }
2429
2430 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2431 {
2432         /* Ensure the core number fits in the field */
2433         WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2434                            MIPS_GLOBALNUMBER_CLUSTER_SHF));
2435
2436         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2437         cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2438 }
2439
2440 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2441 {
2442         /* Ensure the core number fits in the field */
2443         WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2444
2445         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2446         cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2447 }
2448
2449 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2450 {
2451         /* Ensure the VP(E) ID fits in the field */
2452         WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2453
2454         /* Ensure we're not using VP(E)s without support */
2455         WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2456                 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2457
2458         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2459         cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2460 }