2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
11 #ifndef _ASM_STACKFRAME_H
12 #define _ASM_STACKFRAME_H
14 #include <linux/threads.h>
17 #include <asm/asmmacro.h>
18 #include <asm/mipsregs.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/thread_info.h>
22 /* Make the addition of cfi info a little easier. */
23 .macro cfi_rel_offset reg offset=0 docfi=0
25 .cfi_rel_offset \reg, \offset
29 .macro cfi_st reg offset=0 docfi=0
30 LONG_S \reg, \offset(sp)
31 cfi_rel_offset \reg, \offset, \docfi
34 .macro cfi_restore reg offset=0 docfi=0
40 .macro cfi_ld reg offset=0 docfi=0
41 LONG_L \reg, \offset(sp)
42 cfi_restore \reg \offset \docfi
45 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
51 .macro SAVE_AT docfi=0
54 cfi_st $1, PT_R1, \docfi
58 .macro SAVE_TEMP docfi=0
59 #ifdef CONFIG_CPU_HAS_SMARTMIPS
66 #elif !defined(CONFIG_CPU_MIPSR6)
70 cfi_st $8, PT_R8, \docfi
71 cfi_st $9, PT_R9, \docfi
73 cfi_st $10, PT_R10, \docfi
74 cfi_st $11, PT_R11, \docfi
75 cfi_st $12, PT_R12, \docfi
76 #if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
80 cfi_st $13, PT_R13, \docfi
81 cfi_st $14, PT_R14, \docfi
82 cfi_st $15, PT_R15, \docfi
83 cfi_st $24, PT_R24, \docfi
84 #if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
87 #ifdef CONFIG_CPU_CAVIUM_OCTEON
89 * The Octeon multiplier state is affected by general
90 * multiply instructions. It must be saved before and
91 * kernel code might corrupt it
97 .macro SAVE_STATIC docfi=0
98 cfi_st $16, PT_R16, \docfi
99 cfi_st $17, PT_R17, \docfi
100 cfi_st $18, PT_R18, \docfi
101 cfi_st $19, PT_R19, \docfi
102 cfi_st $20, PT_R20, \docfi
103 cfi_st $21, PT_R21, \docfi
104 cfi_st $22, PT_R22, \docfi
105 cfi_st $23, PT_R23, \docfi
106 cfi_st $30, PT_R30, \docfi
110 * get_saved_sp returns the SP for the current CPU by looking in the
111 * kernelsp array for it. If tosp is set, it stores the current sp in
112 * k0 and loads the new value in sp. If not, it clobbers k0 and
113 * stores the new value in k1, leaving sp unaffected.
118 .macro get_saved_sp docfi=0 tosp=0
119 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
120 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
121 lui k1, %hi(kernelsp)
123 lui k1, %highest(kernelsp)
124 daddiu k1, %higher(kernelsp)
126 daddiu k1, %hi(kernelsp)
129 LONG_SRL k0, SMP_CPUID_PTRSHIFT
136 LONG_L sp, %lo(kernelsp)(k1)
138 LONG_L k1, %lo(kernelsp)(k1)
142 .macro set_saved_sp stackp temp temp2
143 ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG
144 LONG_SRL \temp, SMP_CPUID_PTRSHIFT
145 LONG_S \stackp, kernelsp(\temp)
147 #else /* !CONFIG_SMP */
148 /* Uniprocessor variation */
149 .macro get_saved_sp docfi=0 tosp=0
150 #ifdef CONFIG_CPU_JUMP_WORKAROUNDS
152 * Clear BTB (branch target buffer), forbid RAS (return address
153 * stack) to workaround the Out-of-order Issue in Loongson2F
154 * via its diagnostic register.
168 #endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
169 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
170 lui k1, %hi(kernelsp)
172 lui k1, %highest(kernelsp)
173 daddiu k1, %higher(kernelsp)
175 daddiu k1, %hi(kernelsp)
183 LONG_L sp, %lo(kernelsp)(k1)
185 LONG_L k1, %lo(kernelsp)(k1)
189 .macro set_saved_sp stackp temp temp2
190 LONG_S \stackp, kernelsp
194 .macro SAVE_SOME docfi=0
199 sll k0, 3 /* extract cu0 bit */
208 * Flush interAptiv's Return Prediction Stack (RPS) by writing
209 * EntryHi. Toggling Config7.RPS is slower and less portable.
211 * The RPS isn't automatically flushed when exceptions are
212 * taken, which can result in kernel mode speculative accesses
213 * to user addresses if the RPS mispredicts. That's harmless
214 * when user and kernel share the same address space, but with
215 * EVA the same user segments may be unmapped to kernel mode,
216 * even containing sensitive MMIO regions or invalid memory.
218 * This can happen when the kernel sets the return address to
219 * ret_from_* and jr's to the exception handler, which looks
220 * more like a tail call than a function call. If nested calls
221 * don't evict the last user address in the RPS, it will
222 * mispredict the return and fetch from a user controlled
223 * address into the icache.
225 * More recent EVA-capable cores with MAAR to restrict
226 * speculative accesses aren't affected.
232 /* Called from user mode, new stack. */
233 get_saved_sp docfi=\docfi tosp=1
235 #ifdef CONFIG_CPU_DADDI_WORKAROUNDS
239 #ifdef CONFIG_CPU_DADDI_WORKAROUNDS
245 cfi_st k0, PT_R29, \docfi
246 cfi_rel_offset sp, PT_R29, \docfi
247 cfi_st v1, PT_R3, \docfi
249 * You might think that you don't need to save $0,
250 * but the FPU emulator and gdb remote debug stub
251 * need it to operate correctly
255 cfi_st v0, PT_R2, \docfi
256 LONG_S v1, PT_STATUS(sp)
257 cfi_st $4, PT_R4, \docfi
259 cfi_st $5, PT_R5, \docfi
260 LONG_S v1, PT_CAUSE(sp)
261 cfi_st $6, PT_R6, \docfi
262 cfi_st ra, PT_R31, \docfi
264 cfi_st $7, PT_R7, \docfi
266 cfi_st $8, PT_R8, \docfi
267 cfi_st $9, PT_R9, \docfi
269 LONG_S ra, PT_EPC(sp)
271 .cfi_rel_offset ra, PT_EPC
273 cfi_st $25, PT_R25, \docfi
274 cfi_st $28, PT_R28, \docfi
276 /* Set thread_info if we're coming from user mode */
278 sll k0, 3 /* extract cu0 bit */
281 ori $28, sp, _THREAD_MASK
282 xori $28, _THREAD_MASK
283 #ifdef CONFIG_CPU_CAVIUM_OCTEON
285 pref 0, 0($28) /* Prefetch the current pointer */
291 .macro SAVE_ALL docfi=0
298 .macro RESTORE_AT docfi=0
301 cfi_ld $1, PT_R1, \docfi
305 .macro RESTORE_TEMP docfi=0
306 #ifdef CONFIG_CPU_CAVIUM_OCTEON
307 /* Restore the Octeon multiplier state */
308 jal octeon_mult_restore
310 #ifdef CONFIG_CPU_HAS_SMARTMIPS
311 LONG_L $24, PT_ACX(sp)
313 LONG_L $24, PT_HI(sp)
315 LONG_L $24, PT_LO(sp)
317 #elif !defined(CONFIG_CPU_MIPSR6)
318 LONG_L $24, PT_LO(sp)
320 LONG_L $24, PT_HI(sp)
324 cfi_ld $8, PT_R8, \docfi
325 cfi_ld $9, PT_R9, \docfi
327 cfi_ld $10, PT_R10, \docfi
328 cfi_ld $11, PT_R11, \docfi
329 cfi_ld $12, PT_R12, \docfi
330 cfi_ld $13, PT_R13, \docfi
331 cfi_ld $14, PT_R14, \docfi
332 cfi_ld $15, PT_R15, \docfi
333 cfi_ld $24, PT_R24, \docfi
336 .macro RESTORE_STATIC docfi=0
337 cfi_ld $16, PT_R16, \docfi
338 cfi_ld $17, PT_R17, \docfi
339 cfi_ld $18, PT_R18, \docfi
340 cfi_ld $19, PT_R19, \docfi
341 cfi_ld $20, PT_R20, \docfi
342 cfi_ld $21, PT_R21, \docfi
343 cfi_ld $22, PT_R22, \docfi
344 cfi_ld $23, PT_R23, \docfi
345 cfi_ld $30, PT_R30, \docfi
348 .macro RESTORE_SP docfi=0
349 cfi_ld sp, PT_R29, \docfi
352 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
354 .macro RESTORE_SOME docfi=0
359 li v1, ST0_CU1 | ST0_IM
364 LONG_L v0, PT_STATUS(sp)
369 cfi_ld $31, PT_R31, \docfi
370 cfi_ld $28, PT_R28, \docfi
371 cfi_ld $25, PT_R25, \docfi
372 cfi_ld $7, PT_R7, \docfi
373 cfi_ld $6, PT_R6, \docfi
374 cfi_ld $5, PT_R5, \docfi
375 cfi_ld $4, PT_R4, \docfi
376 cfi_ld $3, PT_R3, \docfi
377 cfi_ld $2, PT_R2, \docfi
381 .macro RESTORE_SP_AND_RET docfi=0
384 LONG_L k0, PT_EPC(sp)
392 .macro RESTORE_SOME docfi=0
400 li v1, ST0_CU1 | ST0_FR | ST0_IM
402 LONG_L v0, PT_STATUS(sp)
407 LONG_L v1, PT_EPC(sp)
409 cfi_ld $31, PT_R31, \docfi
410 cfi_ld $28, PT_R28, \docfi
411 cfi_ld $25, PT_R25, \docfi
413 cfi_ld $8, PT_R8, \docfi
414 cfi_ld $9, PT_R9, \docfi
416 cfi_ld $7, PT_R7, \docfi
417 cfi_ld $6, PT_R6, \docfi
418 cfi_ld $5, PT_R5, \docfi
419 cfi_ld $4, PT_R4, \docfi
420 cfi_ld $3, PT_R3, \docfi
421 cfi_ld $2, PT_R2, \docfi
425 .macro RESTORE_SP_AND_RET docfi=0
427 #ifdef CONFIG_CPU_MIPSR6
439 .macro RESTORE_ALL docfi=0
441 RESTORE_STATIC \docfi
448 * Move to kernel mode and disable interrupts.
449 * Set cp0 enable bit as sign that we're running on the kernel stack
453 li t1, ST0_CU0 | STATMASK
461 * Move to kernel mode and enable interrupts.
462 * Set cp0 enable bit as sign that we're running on the kernel stack
466 li t1, ST0_CU0 | STATMASK
468 xori t0, STATMASK & ~1
474 * Just move to kernel mode and leave interrupts as they are. Note
475 * for the R3000 this means copying the previous enable from IEp.
476 * Set cp0 enable bit as sign that we're running on the kernel stack
480 li t1, ST0_CU0 | (STATMASK & ~1)
481 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
487 xori t0, STATMASK & ~1
492 #endif /* _ASM_STACKFRAME_H */