2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2002 by Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 * Copyright (C) 2002 Maciej W. Rozycki
10 #ifndef _ASM_PGTABLE_BITS_H
11 #define _ASM_PGTABLE_BITS_H
15 * Note that we shift the lower 32bits of each EntryLo[01] entry
16 * 6 bits to the left. That way we can convert the PFN into the
17 * physical address by a single 'and' operation and gain 6 additional
18 * bits for storing information which isn't present in a normal
21 * Similar to the Alpha port, we need to keep track of the ref
22 * and mod bits in software. We have a software "yeah you can read
23 * from this page" bit, and a hardware one which actually lets the
24 * process read from the page. On the same token we have a software
25 * writable bit and the real hardware one which actually lets the
26 * process write to the page, this keeps a mod bit via the hardware
29 * Certain revisions of the R4000 and R5000 have a bug where if a
30 * certain sequence occurs in the last 3 instructions of an executable
31 * page, and the following page is not mapped, the cpu can do
32 * unpredictable things. The code (when it is written) to deal with
33 * this problem will be in the update_mmu_cache() code for the r4k.
35 #if defined(CONFIG_XPA)
38 * Page table bit offsets used for 64 bit physical addressing on
42 /* Used by TLB hardware (placed in EntryLo*) */
50 /* Used only by software (masked out before writing EntryLo*) */
51 _PAGE_PRESENT_SHIFT = 24,
59 * Bits for extended EntryLo0/EntryLo1 registers
61 #define _PFNX_MASK 0xffffff
63 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
66 * Page table bit offsets used for 36 bit physical addressing on MIPS32,
67 * for example with Alchemy or Netlogic XLP/XLR.
70 /* Used by TLB hardware (placed in EntryLo*) */
76 /* Used only by software (masked out before writing EntryLo*) */
77 _PAGE_PRESENT_SHIFT = _CACHE_SHIFT + 3,
85 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
87 /* Page table bits used for r3k systems */
89 /* Used only by software (writes to EntryLo ignored) */
97 /* Used by TLB hardware (placed in EntryLo) */
98 _PAGE_GLOBAL_SHIFT = 8,
101 _CACHE_UNCACHED_SHIFT,
106 /* Page table bits used for r4k systems */
108 /* Used only by software (masked out before writing EntryLo*) */
110 #if !defined(CONFIG_CPU_HAS_RIXI)
114 _PAGE_ACCESSED_SHIFT,
115 _PAGE_MODIFIED_SHIFT,
116 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
121 /* Used by TLB hardware (placed in EntryLo*) */
122 #if defined(CONFIG_CPU_HAS_RIXI)
132 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
134 /* Used only by software */
135 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
136 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
137 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
138 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
139 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
140 # define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
142 #define _PAGE_SPECIAL (1 << _PAGE_SPECIAL_SHIFT)
144 /* Used by TLB hardware (placed in EntryLo*) */
145 #if defined(CONFIG_XPA)
146 # define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
147 #elif defined(CONFIG_CPU_HAS_RIXI)
148 # define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
150 #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
151 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
152 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
153 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
154 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
155 # define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
156 # define _CACHE_MASK _CACHE_UNCACHED
157 # define _PFN_SHIFT PAGE_SHIFT
159 # define _CACHE_MASK (7 << _CACHE_SHIFT)
160 # define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
163 #ifndef _PAGE_NO_EXEC
164 #define _PAGE_NO_EXEC 0
167 #define _PAGE_SILENT_READ _PAGE_VALID
168 #define _PAGE_SILENT_WRITE _PAGE_DIRTY
170 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
173 * The final layouts of the PTE bits are:
175 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
176 * 32-bit, R1 or earler: CCC D V G M A W R P
177 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
178 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
183 * pte_to_entrylo converts a page table entry (PTE) into a Mips
186 static inline uint64_t pte_to_entrylo(unsigned long pte_val)
188 #ifdef CONFIG_CPU_HAS_RIXI
192 sa = 31 - _PAGE_NO_READ_SHIFT;
194 sa = 63 - _PAGE_NO_READ_SHIFT;
197 * C has no way to express that this is a DSRL
198 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
199 * in the fast path this is done in assembly
201 return (pte_val >> _PAGE_GLOBAL_SHIFT) |
202 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
206 return pte_val >> _PAGE_GLOBAL_SHIFT;
212 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
214 #define _CACHE_CACHABLE_NONCOHERENT 0
215 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
217 #elif defined(CONFIG_CPU_SB1)
219 /* No penalty for being coherent on the SB1, so just
220 use it for "noncoherent" spaces, too. Shouldn't hurt. */
222 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
224 #elif defined(CONFIG_CPU_LOONGSON3)
226 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */
228 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
229 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
231 #elif defined(CONFIG_MACH_INGENIC)
233 /* Ingenic uses the WA bit to achieve write-combine memory writes */
234 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
238 #ifndef _CACHE_CACHABLE_NO_WA
239 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
241 #ifndef _CACHE_CACHABLE_WA
242 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
244 #ifndef _CACHE_UNCACHED
245 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
247 #ifndef _CACHE_CACHABLE_NONCOHERENT
248 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
250 #ifndef _CACHE_CACHABLE_CE
251 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
253 #ifndef _CACHE_CACHABLE_COW
254 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
256 #ifndef _CACHE_CACHABLE_CUW
257 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
259 #ifndef _CACHE_UNCACHED_ACCELERATED
260 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
263 #define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED)
264 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
266 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
267 _PFN_MASK | _CACHE_MASK)
269 #endif /* _ASM_PGTABLE_BITS_H */