2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
19 #include <asm/isa-rev.h>
23 * The following macros are especially useful for __asm__
30 #define STR(x) __STR(x)
40 #define _ULCAST_ (unsigned long)
41 #define _U64CAST_ (u64)
45 * Coprocessor 0 register names
49 #define CP0_ENTRYLO0 $2
50 #define CP0_ENTRYLO1 $3
52 #define CP0_GLOBALNUMBER $3, 1
53 #define CP0_CONTEXT $4
54 #define CP0_PAGEMASK $5
55 #define CP0_PAGEGRAIN $5, 1
56 #define CP0_SEGCTL0 $5, 2
57 #define CP0_SEGCTL1 $5, 3
58 #define CP0_SEGCTL2 $5, 4
62 #define CP0_BADVADDR $8
63 #define CP0_BADINSTR $8, 1
65 #define CP0_ENTRYHI $10
66 #define CP0_GUESTCTL1 $10, 4
67 #define CP0_GUESTCTL2 $10, 5
68 #define CP0_GUESTCTL3 $10, 6
69 #define CP0_COMPARE $11
70 #define CP0_GUESTCTL0EXT $11, 4
71 #define CP0_STATUS $12
72 #define CP0_GUESTCTL0 $12, 6
73 #define CP0_GTOFFSET $12, 7
77 #define CP0_EBASE $15, 1
78 #define CP0_CMGCRBASE $15, 3
79 #define CP0_CONFIG $16
80 #define CP0_CONFIG3 $16, 3
81 #define CP0_CONFIG5 $16, 5
82 #define CP0_CONFIG6 $16, 6
83 #define CP0_LLADDR $17
84 #define CP0_WATCHLO $18
85 #define CP0_WATCHHI $19
86 #define CP0_XCONTEXT $20
87 #define CP0_FRAMEMASK $21
88 #define CP0_DIAGNOSTIC $22
89 #define CP0_DIAGNOSTIC1 $22, 1
92 #define CP0_PERFORMANCE $25
94 #define CP0_CACHEERR $27
97 #define CP0_ERROREPC $30
98 #define CP0_DESAVE $31
101 * R4640/R4650 cp0 register names. These registers are listed
102 * here only for completeness; without MMU these CPUs are not useable
103 * by Linux. A future ELKS port might take make Linux run on them
107 #define CP0_IBOUND $1
109 #define CP0_DBOUND $3
111 #define CP0_IWATCH $18
112 #define CP0_DWATCH $19
115 * Coprocessor 0 Set 1 register names
117 #define CP0_S1_DERRADDR0 $26
118 #define CP0_S1_DERRADDR1 $27
119 #define CP0_S1_INTCONTROL $20
122 * Coprocessor 0 Set 2 register names
124 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
127 * Coprocessor 0 Set 3 register names
129 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
134 #define CP0_TX39_CACHE $7
137 /* Generic EntryLo bit definitions */
138 #define ENTRYLO_G (_ULCAST_(1) << 0)
139 #define ENTRYLO_V (_ULCAST_(1) << 1)
140 #define ENTRYLO_D (_ULCAST_(1) << 2)
141 #define ENTRYLO_C_SHIFT 3
142 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
144 /* R3000 EntryLo bit definitions */
145 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
146 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
147 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
148 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
150 /* MIPS32/64 EntryLo bit definitions */
151 #define MIPS_ENTRYLO_PFN_SHIFT 6
152 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
153 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
156 * MIPSr6+ GlobalNumber register definitions
158 #define MIPS_GLOBALNUMBER_VP_SHF 0
159 #define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
160 #define MIPS_GLOBALNUMBER_CORE_SHF 8
161 #define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
162 #define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
163 #define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
166 * Values for PageMask register
168 #ifdef CONFIG_CPU_VR41XX
170 /* Why doesn't stupidity hurt ... */
172 #define PM_1K 0x00000000
173 #define PM_4K 0x00001800
174 #define PM_16K 0x00007800
175 #define PM_64K 0x0001f800
176 #define PM_256K 0x0007f800
180 #define PM_4K 0x00000000
181 #define PM_8K 0x00002000
182 #define PM_16K 0x00006000
183 #define PM_32K 0x0000e000
184 #define PM_64K 0x0001e000
185 #define PM_128K 0x0003e000
186 #define PM_256K 0x0007e000
187 #define PM_512K 0x000fe000
188 #define PM_1M 0x001fe000
189 #define PM_2M 0x003fe000
190 #define PM_4M 0x007fe000
191 #define PM_8M 0x00ffe000
192 #define PM_16M 0x01ffe000
193 #define PM_32M 0x03ffe000
194 #define PM_64M 0x07ffe000
195 #define PM_256M 0x1fffe000
196 #define PM_1G 0x7fffe000
201 * Default page size for a given kernel configuration
203 #ifdef CONFIG_PAGE_SIZE_4KB
204 #define PM_DEFAULT_MASK PM_4K
205 #elif defined(CONFIG_PAGE_SIZE_8KB)
206 #define PM_DEFAULT_MASK PM_8K
207 #elif defined(CONFIG_PAGE_SIZE_16KB)
208 #define PM_DEFAULT_MASK PM_16K
209 #elif defined(CONFIG_PAGE_SIZE_32KB)
210 #define PM_DEFAULT_MASK PM_32K
211 #elif defined(CONFIG_PAGE_SIZE_64KB)
212 #define PM_DEFAULT_MASK PM_64K
214 #error Bad page size configuration!
218 * Default huge tlb size for a given kernel configuration
220 #ifdef CONFIG_PAGE_SIZE_4KB
221 #define PM_HUGE_MASK PM_1M
222 #elif defined(CONFIG_PAGE_SIZE_8KB)
223 #define PM_HUGE_MASK PM_4M
224 #elif defined(CONFIG_PAGE_SIZE_16KB)
225 #define PM_HUGE_MASK PM_16M
226 #elif defined(CONFIG_PAGE_SIZE_32KB)
227 #define PM_HUGE_MASK PM_64M
228 #elif defined(CONFIG_PAGE_SIZE_64KB)
229 #define PM_HUGE_MASK PM_256M
230 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
231 #error Bad page size configuration for hugetlbfs!
235 * Wired register bits
237 #define MIPSR6_WIRED_LIMIT_SHIFT 16
238 #define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
239 #define MIPSR6_WIRED_WIRED_SHIFT 0
240 #define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
243 * Values used for computation of new tlb entries
258 #define PG_RIE (_ULCAST_(1) << 31)
259 #define PG_XIE (_ULCAST_(1) << 30)
260 #define PG_ELPA (_ULCAST_(1) << 29)
261 #define PG_ESP (_ULCAST_(1) << 28)
262 #define PG_IEC (_ULCAST_(1) << 27)
264 /* MIPS32/64 EntryHI bit definitions */
265 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
266 #define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
267 #define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
270 * R4x00 interrupt enable / cause bits
272 #define IE_SW0 (_ULCAST_(1) << 8)
273 #define IE_SW1 (_ULCAST_(1) << 9)
274 #define IE_IRQ0 (_ULCAST_(1) << 10)
275 #define IE_IRQ1 (_ULCAST_(1) << 11)
276 #define IE_IRQ2 (_ULCAST_(1) << 12)
277 #define IE_IRQ3 (_ULCAST_(1) << 13)
278 #define IE_IRQ4 (_ULCAST_(1) << 14)
279 #define IE_IRQ5 (_ULCAST_(1) << 15)
282 * R4x00 interrupt cause bits
284 #define C_SW0 (_ULCAST_(1) << 8)
285 #define C_SW1 (_ULCAST_(1) << 9)
286 #define C_IRQ0 (_ULCAST_(1) << 10)
287 #define C_IRQ1 (_ULCAST_(1) << 11)
288 #define C_IRQ2 (_ULCAST_(1) << 12)
289 #define C_IRQ3 (_ULCAST_(1) << 13)
290 #define C_IRQ4 (_ULCAST_(1) << 14)
291 #define C_IRQ5 (_ULCAST_(1) << 15)
294 * Bitfields in the R4xx0 cp0 status register
296 #define ST0_IE 0x00000001
297 #define ST0_EXL 0x00000002
298 #define ST0_ERL 0x00000004
299 #define ST0_KSU 0x00000018
300 # define KSU_USER 0x00000010
301 # define KSU_SUPERVISOR 0x00000008
302 # define KSU_KERNEL 0x00000000
303 #define ST0_UX 0x00000020
304 #define ST0_SX 0x00000040
305 #define ST0_KX 0x00000080
306 #define ST0_DE 0x00010000
307 #define ST0_CE 0x00020000
310 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
311 * cacheops in userspace. This bit exists only on RM7000 and RM9000
314 #define ST0_CO 0x08000000
317 * Bitfields in the R[23]000 cp0 status register.
319 #define ST0_IEC 0x00000001
320 #define ST0_KUC 0x00000002
321 #define ST0_IEP 0x00000004
322 #define ST0_KUP 0x00000008
323 #define ST0_IEO 0x00000010
324 #define ST0_KUO 0x00000020
325 /* bits 6 & 7 are reserved on R[23]000 */
326 #define ST0_ISC 0x00010000
327 #define ST0_SWC 0x00020000
328 #define ST0_CM 0x00080000
331 * Bits specific to the R4640/R4650
333 #define ST0_UM (_ULCAST_(1) << 4)
334 #define ST0_IL (_ULCAST_(1) << 23)
335 #define ST0_DL (_ULCAST_(1) << 24)
338 * Enable the MIPS MDMX and DSP ASEs
340 #define ST0_MX 0x01000000
343 * Status register bits available in all MIPS CPUs.
345 #define ST0_IM 0x0000ff00
346 #define STATUSB_IP0 8
347 #define STATUSF_IP0 (_ULCAST_(1) << 8)
348 #define STATUSB_IP1 9
349 #define STATUSF_IP1 (_ULCAST_(1) << 9)
350 #define STATUSB_IP2 10
351 #define STATUSF_IP2 (_ULCAST_(1) << 10)
352 #define STATUSB_IP3 11
353 #define STATUSF_IP3 (_ULCAST_(1) << 11)
354 #define STATUSB_IP4 12
355 #define STATUSF_IP4 (_ULCAST_(1) << 12)
356 #define STATUSB_IP5 13
357 #define STATUSF_IP5 (_ULCAST_(1) << 13)
358 #define STATUSB_IP6 14
359 #define STATUSF_IP6 (_ULCAST_(1) << 14)
360 #define STATUSB_IP7 15
361 #define STATUSF_IP7 (_ULCAST_(1) << 15)
362 #define STATUSB_IP8 0
363 #define STATUSF_IP8 (_ULCAST_(1) << 0)
364 #define STATUSB_IP9 1
365 #define STATUSF_IP9 (_ULCAST_(1) << 1)
366 #define STATUSB_IP10 2
367 #define STATUSF_IP10 (_ULCAST_(1) << 2)
368 #define STATUSB_IP11 3
369 #define STATUSF_IP11 (_ULCAST_(1) << 3)
370 #define STATUSB_IP12 4
371 #define STATUSF_IP12 (_ULCAST_(1) << 4)
372 #define STATUSB_IP13 5
373 #define STATUSF_IP13 (_ULCAST_(1) << 5)
374 #define STATUSB_IP14 6
375 #define STATUSF_IP14 (_ULCAST_(1) << 6)
376 #define STATUSB_IP15 7
377 #define STATUSF_IP15 (_ULCAST_(1) << 7)
378 #define ST0_CH 0x00040000
379 #define ST0_NMI 0x00080000
380 #define ST0_SR 0x00100000
381 #define ST0_TS 0x00200000
382 #define ST0_BEV 0x00400000
383 #define ST0_RE 0x02000000
384 #define ST0_FR 0x04000000
385 #define ST0_CU 0xf0000000
386 #define ST0_CU0 0x10000000
387 #define ST0_CU1 0x20000000
388 #define ST0_CU2 0x40000000
389 #define ST0_CU3 0x80000000
390 #define ST0_XX 0x80000000 /* MIPS IV naming */
393 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
395 #define INTCTLB_IPFDC 23
396 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
397 #define INTCTLB_IPPCI 26
398 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
399 #define INTCTLB_IPTI 29
400 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
403 * Bitfields and bit numbers in the coprocessor 0 cause register.
405 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
407 #define CAUSEB_EXCCODE 2
408 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
410 #define CAUSEF_IP (_ULCAST_(255) << 8)
412 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
414 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
415 #define CAUSEB_IP2 10
416 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
417 #define CAUSEB_IP3 11
418 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
419 #define CAUSEB_IP4 12
420 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
421 #define CAUSEB_IP5 13
422 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
423 #define CAUSEB_IP6 14
424 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
425 #define CAUSEB_IP7 15
426 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
427 #define CAUSEB_FDCI 21
428 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
430 #define CAUSEF_WP (_ULCAST_(1) << 22)
432 #define CAUSEF_IV (_ULCAST_(1) << 23)
433 #define CAUSEB_PCI 26
434 #define CAUSEF_PCI (_ULCAST_(1) << 26)
436 #define CAUSEF_DC (_ULCAST_(1) << 27)
438 #define CAUSEF_CE (_ULCAST_(3) << 28)
440 #define CAUSEF_TI (_ULCAST_(1) << 30)
442 #define CAUSEF_BD (_ULCAST_(1) << 31)
445 * Cause.ExcCode trap codes.
447 #define EXCCODE_INT 0 /* Interrupt pending */
448 #define EXCCODE_MOD 1 /* TLB modified fault */
449 #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
450 #define EXCCODE_TLBS 3 /* TLB miss on a store */
451 #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
452 #define EXCCODE_ADES 5 /* Address error on a store */
453 #define EXCCODE_IBE 6 /* Bus error on an ifetch */
454 #define EXCCODE_DBE 7 /* Bus error on a load or store */
455 #define EXCCODE_SYS 8 /* System call */
456 #define EXCCODE_BP 9 /* Breakpoint */
457 #define EXCCODE_RI 10 /* Reserved instruction exception */
458 #define EXCCODE_CPU 11 /* Coprocessor unusable */
459 #define EXCCODE_OV 12 /* Arithmetic overflow */
460 #define EXCCODE_TR 13 /* Trap instruction */
461 #define EXCCODE_MSAFPE 14 /* MSA floating point exception */
462 #define EXCCODE_FPE 15 /* Floating point exception */
463 #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
464 #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
465 #define EXCCODE_MSADIS 21 /* MSA disabled exception */
466 #define EXCCODE_MDMX 22 /* MDMX unusable exception */
467 #define EXCCODE_WATCH 23 /* Watch address reference */
468 #define EXCCODE_MCHECK 24 /* Machine check */
469 #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
470 #define EXCCODE_DSPDIS 26 /* DSP disabled exception */
471 #define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
472 #define EXCCODE_CACHEERR 30 /* Parity/ECC occured on a core */
474 /* Implementation specific trap codes used by MIPS cores */
475 #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
477 /* Implementation specific trap codes used by Loongson cores */
478 #define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */
481 * Bits in the coprocessor 0 config register.
484 #define CONF_CM_CACHABLE_NO_WA 0
485 #define CONF_CM_CACHABLE_WA 1
486 #define CONF_CM_UNCACHED 2
487 #define CONF_CM_CACHABLE_NONCOHERENT 3
488 #define CONF_CM_CACHABLE_CE 4
489 #define CONF_CM_CACHABLE_COW 5
490 #define CONF_CM_CACHABLE_CUW 6
491 #define CONF_CM_CACHABLE_ACCELERATED 7
492 #define CONF_CM_CMASK 7
493 #define CONF_BE (_ULCAST_(1) << 15)
495 /* Bits common to various processors. */
496 #define CONF_CU (_ULCAST_(1) << 3)
497 #define CONF_DB (_ULCAST_(1) << 4)
498 #define CONF_IB (_ULCAST_(1) << 5)
499 #define CONF_DC (_ULCAST_(7) << 6)
500 #define CONF_IC (_ULCAST_(7) << 9)
501 #define CONF_EB (_ULCAST_(1) << 13)
502 #define CONF_EM (_ULCAST_(1) << 14)
503 #define CONF_SM (_ULCAST_(1) << 16)
504 #define CONF_SC (_ULCAST_(1) << 17)
505 #define CONF_EW (_ULCAST_(3) << 18)
506 #define CONF_EP (_ULCAST_(15)<< 24)
507 #define CONF_EC (_ULCAST_(7) << 28)
508 #define CONF_CM (_ULCAST_(1) << 31)
510 /* Bits specific to the R4xx0. */
511 #define R4K_CONF_SW (_ULCAST_(1) << 20)
512 #define R4K_CONF_SS (_ULCAST_(1) << 21)
513 #define R4K_CONF_SB (_ULCAST_(3) << 22)
515 /* Bits specific to the R5000. */
516 #define R5K_CONF_SE (_ULCAST_(1) << 12)
517 #define R5K_CONF_SS (_ULCAST_(3) << 20)
519 /* Bits specific to the RM7000. */
520 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
521 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
522 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
523 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
524 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
525 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
527 /* Bits specific to the R10000. */
528 #define R10K_CONF_DN (_ULCAST_(3) << 3)
529 #define R10K_CONF_CT (_ULCAST_(1) << 5)
530 #define R10K_CONF_PE (_ULCAST_(1) << 6)
531 #define R10K_CONF_PM (_ULCAST_(3) << 7)
532 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
533 #define R10K_CONF_SB (_ULCAST_(1) << 13)
534 #define R10K_CONF_SK (_ULCAST_(1) << 14)
535 #define R10K_CONF_SS (_ULCAST_(7) << 16)
536 #define R10K_CONF_SC (_ULCAST_(7) << 19)
537 #define R10K_CONF_DC (_ULCAST_(7) << 26)
538 #define R10K_CONF_IC (_ULCAST_(7) << 29)
540 /* Bits specific to the VR41xx. */
541 #define VR41_CONF_CS (_ULCAST_(1) << 12)
542 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
543 #define VR41_CONF_BP (_ULCAST_(1) << 16)
544 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
545 #define VR41_CONF_AD (_ULCAST_(1) << 23)
547 /* Bits specific to the R30xx. */
548 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
549 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
550 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
551 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
552 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
553 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
554 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
555 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
556 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
558 /* Bits specific to the TX49. */
559 #define TX49_CONF_DC (_ULCAST_(1) << 16)
560 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
561 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
562 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
564 /* Bits specific to the MIPS32/64 PRA. */
565 #define MIPS_CONF_VI (_ULCAST_(1) << 3)
566 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
567 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
568 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
569 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
570 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
571 #define MIPS_CONF_BE (_ULCAST_(1) << 15)
572 #define MIPS_CONF_BM (_ULCAST_(1) << 16)
573 #define MIPS_CONF_MM (_ULCAST_(3) << 17)
574 #define MIPS_CONF_MM_SYSAD (_ULCAST_(1) << 17)
575 #define MIPS_CONF_MM_FULL (_ULCAST_(2) << 17)
576 #define MIPS_CONF_SB (_ULCAST_(1) << 21)
577 #define MIPS_CONF_UDI (_ULCAST_(1) << 22)
578 #define MIPS_CONF_DSP (_ULCAST_(1) << 23)
579 #define MIPS_CONF_ISP (_ULCAST_(1) << 24)
580 #define MIPS_CONF_KU (_ULCAST_(3) << 25)
581 #define MIPS_CONF_K23 (_ULCAST_(3) << 28)
582 #define MIPS_CONF_M (_ULCAST_(1) << 31)
585 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
587 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
588 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
589 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
590 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
591 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
592 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
593 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
594 #define MIPS_CONF1_DA_SHF 7
595 #define MIPS_CONF1_DA_SZ 3
596 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
597 #define MIPS_CONF1_DL_SHF 10
598 #define MIPS_CONF1_DL_SZ 3
599 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
600 #define MIPS_CONF1_DS_SHF 13
601 #define MIPS_CONF1_DS_SZ 3
602 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
603 #define MIPS_CONF1_IA_SHF 16
604 #define MIPS_CONF1_IA_SZ 3
605 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
606 #define MIPS_CONF1_IL_SHF 19
607 #define MIPS_CONF1_IL_SZ 3
608 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
609 #define MIPS_CONF1_IS_SHF 22
610 #define MIPS_CONF1_IS_SZ 3
611 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
612 #define MIPS_CONF1_TLBS_SHIFT (25)
613 #define MIPS_CONF1_TLBS_SIZE (6)
614 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
616 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
617 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
618 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
619 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
620 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
621 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
622 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
623 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
625 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
626 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
627 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
628 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
629 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
630 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
631 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
632 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
633 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
634 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
635 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
636 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
637 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
638 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
639 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
640 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
641 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
642 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
643 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
644 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
645 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
646 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
647 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
648 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
649 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
650 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
651 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
653 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
654 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
655 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
656 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
657 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
658 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
659 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
660 /* bits 10:8 in FTLB-only configurations */
661 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
662 /* bits 12:8 in VTLB-FTLB only configurations */
663 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
664 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
665 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
666 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
667 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
668 #define MIPS_CONF4_KSCREXIST_SHIFT (16)
669 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
670 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
671 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
672 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
673 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
674 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
676 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
677 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
678 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
679 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
680 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
681 #define MIPS_CONF5_VP (_ULCAST_(1) << 7)
682 #define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
683 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
684 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
685 #define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
686 #define MIPS_CONF5_MI (_ULCAST_(1) << 17)
687 #define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
688 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
689 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
690 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
691 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
693 /* Config6 feature bits for proAptiv/P5600 */
695 /* Jump register cache prediction disable */
696 #define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
697 /* MIPSr6 extensions enable */
698 #define MTI_CONF6_R6 (_ULCAST_(1) << 2)
699 /* IFU Performance Control */
700 #define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10)
701 #define MTI_CONF6_SYND (_ULCAST_(1) << 13)
702 /* Sleep state performance counter disable */
703 #define MTI_CONF6_SPCD (_ULCAST_(1) << 14)
704 /* proAptiv FTLB on/off bit */
705 #define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15)
706 /* Disable load/store bonding */
707 #define MTI_CONF6_DLSB (_ULCAST_(1) << 21)
708 /* FTLB probability bits */
709 #define MTI_CONF6_FTLBP_SHIFT (16)
711 /* Config6 feature bits for Loongson-3 */
713 /* Loongson-3 internal timer bit */
714 #define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
715 /* Loongson-3 external timer bit */
716 #define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
717 /* Loongson-3 SFB on/off bit, STFill in manual */
718 #define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8)
719 /* Loongson-3's LL on exclusive cacheline */
720 #define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16)
721 /* Loongson-3's SC has a random delay */
722 #define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17)
723 /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
724 #define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
726 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
728 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
730 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
731 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
733 /* Ingenic HPTLB off bits */
734 #define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
736 /* Ingenic Config7 bits */
737 #define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
739 /* Config7 Bits specific to MIPS Technologies. */
741 /* Performance counters implemented Per TC */
742 #define MTI_CONF7_PTC (_ULCAST_(1) << 19)
744 /* WatchLo* register definitions */
745 #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
747 /* WatchHi* register definitions */
748 #define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
749 #define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
750 #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
751 #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
752 #define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
753 #define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
754 #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
755 #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
756 #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
757 #define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
758 #define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
759 #define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
760 #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
762 /* PerfCnt control register definitions */
763 #define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
764 #define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
765 #define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
766 #define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
767 #define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
768 #define MIPS_PERFCTRL_EVENT_S 5
769 #define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
770 #define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
771 #define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
772 #define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
773 #define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
774 #define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
775 #define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
776 #define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
777 #define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
779 /* PerfCnt control register MT extensions used by MIPS cores */
780 #define MIPS_PERFCTRL_VPEID_S 16
781 #define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
782 #define MIPS_PERFCTRL_TCID_S 22
783 #define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
784 #define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
785 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
786 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
787 #define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
789 /* PerfCnt control register MT extensions used by BMIPS5000 */
790 #define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
792 /* PerfCnt control register MT extensions used by Netlogic XLR */
793 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
795 /* MAAR bit definitions */
796 #define MIPS_MAAR_VH (_U64CAST_(1) << 63)
797 #define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)
798 #define MIPS_MAAR_ADDR_SHIFT 12
799 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
800 #define MIPS_MAAR_VL (_ULCAST_(1) << 0)
802 #define MIPS_MAAR_V (MIPS_MAAR_VH | MIPS_MAAR_VL)
804 #define MIPS_MAAR_V MIPS_MAAR_VL
806 #define MIPS_MAARX_VH (_ULCAST_(1) << 31)
807 #define MIPS_MAARX_ADDR 0xF
808 #define MIPS_MAARX_ADDR_SHIFT 32
810 /* MAARI bit definitions */
811 #define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
813 /* EBase bit definitions */
814 #define MIPS_EBASE_CPUNUM_SHIFT 0
815 #define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
816 #define MIPS_EBASE_WG_SHIFT 11
817 #define MIPS_EBASE_WG (_ULCAST_(1) << 11)
818 #define MIPS_EBASE_BASE_SHIFT 12
819 #define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
821 /* CMGCRBase bit definitions */
822 #define MIPS_CMGCRB_BASE 11
823 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
825 /* LLAddr bit definitions */
826 #define MIPS_LLADDR_LLB_SHIFT 0
827 #define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
830 * Bits in the MIPS32 Memory Segmentation registers.
832 #define MIPS_SEGCFG_PA_SHIFT 9
833 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
834 #define MIPS_SEGCFG_AM_SHIFT 4
835 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
836 #define MIPS_SEGCFG_EU_SHIFT 3
837 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
838 #define MIPS_SEGCFG_C_SHIFT 0
839 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
841 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
842 #define MIPS_SEGCFG_USK _ULCAST_(5)
843 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
844 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
845 #define MIPS_SEGCFG_MSK _ULCAST_(2)
846 #define MIPS_SEGCFG_MK _ULCAST_(1)
847 #define MIPS_SEGCFG_UK _ULCAST_(0)
849 #define MIPS_PWFIELD_GDI_SHIFT 24
850 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
851 #define MIPS_PWFIELD_UDI_SHIFT 18
852 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
853 #define MIPS_PWFIELD_MDI_SHIFT 12
854 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
855 #define MIPS_PWFIELD_PTI_SHIFT 6
856 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
857 #define MIPS_PWFIELD_PTEI_SHIFT 0
858 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
860 #define MIPS_PWSIZE_PS_SHIFT 30
861 #define MIPS_PWSIZE_PS_MASK 0x40000000
862 #define MIPS_PWSIZE_GDW_SHIFT 24
863 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
864 #define MIPS_PWSIZE_UDW_SHIFT 18
865 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
866 #define MIPS_PWSIZE_MDW_SHIFT 12
867 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
868 #define MIPS_PWSIZE_PTW_SHIFT 6
869 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
870 #define MIPS_PWSIZE_PTEW_SHIFT 0
871 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
873 #define MIPS_PWCTL_PWEN_SHIFT 31
874 #define MIPS_PWCTL_PWEN_MASK 0x80000000
875 #define MIPS_PWCTL_XK_SHIFT 28
876 #define MIPS_PWCTL_XK_MASK 0x10000000
877 #define MIPS_PWCTL_XS_SHIFT 27
878 #define MIPS_PWCTL_XS_MASK 0x08000000
879 #define MIPS_PWCTL_XU_SHIFT 26
880 #define MIPS_PWCTL_XU_MASK 0x04000000
881 #define MIPS_PWCTL_DPH_SHIFT 7
882 #define MIPS_PWCTL_DPH_MASK 0x00000080
883 #define MIPS_PWCTL_HUGEPG_SHIFT 6
884 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
885 #define MIPS_PWCTL_PSN_SHIFT 0
886 #define MIPS_PWCTL_PSN_MASK 0x0000003f
888 /* GuestCtl0 fields */
889 #define MIPS_GCTL0_GM_SHIFT 31
890 #define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
891 #define MIPS_GCTL0_RI_SHIFT 30
892 #define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
893 #define MIPS_GCTL0_MC_SHIFT 29
894 #define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
895 #define MIPS_GCTL0_CP0_SHIFT 28
896 #define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
897 #define MIPS_GCTL0_AT_SHIFT 26
898 #define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
899 #define MIPS_GCTL0_GT_SHIFT 25
900 #define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
901 #define MIPS_GCTL0_CG_SHIFT 24
902 #define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
903 #define MIPS_GCTL0_CF_SHIFT 23
904 #define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
905 #define MIPS_GCTL0_G1_SHIFT 22
906 #define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
907 #define MIPS_GCTL0_G0E_SHIFT 19
908 #define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
909 #define MIPS_GCTL0_PT_SHIFT 18
910 #define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
911 #define MIPS_GCTL0_RAD_SHIFT 9
912 #define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
913 #define MIPS_GCTL0_DRG_SHIFT 8
914 #define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
915 #define MIPS_GCTL0_G2_SHIFT 7
916 #define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
917 #define MIPS_GCTL0_GEXC_SHIFT 2
918 #define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
919 #define MIPS_GCTL0_SFC2_SHIFT 1
920 #define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
921 #define MIPS_GCTL0_SFC1_SHIFT 0
922 #define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
924 /* GuestCtl0.AT Guest address translation control */
925 #define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
926 #define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
928 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
929 #define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
930 #define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
931 #define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
932 #define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
933 #define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
934 #define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
935 #define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
937 /* GuestCtl0Ext fields */
938 #define MIPS_GCTL0EXT_RPW_SHIFT 8
939 #define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
940 #define MIPS_GCTL0EXT_NCC_SHIFT 6
941 #define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
942 #define MIPS_GCTL0EXT_CGI_SHIFT 4
943 #define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
944 #define MIPS_GCTL0EXT_FCD_SHIFT 3
945 #define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
946 #define MIPS_GCTL0EXT_OG_SHIFT 2
947 #define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
948 #define MIPS_GCTL0EXT_BG_SHIFT 1
949 #define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
950 #define MIPS_GCTL0EXT_MG_SHIFT 0
951 #define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
953 /* GuestCtl0Ext.RPW Root page walk configuration */
954 #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
955 #define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
956 #define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
958 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
959 #define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
960 #define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
962 /* GuestCtl1 fields */
963 #define MIPS_GCTL1_ID_SHIFT 0
964 #define MIPS_GCTL1_ID_WIDTH 8
965 #define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
966 #define MIPS_GCTL1_RID_SHIFT 16
967 #define MIPS_GCTL1_RID_WIDTH 8
968 #define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
969 #define MIPS_GCTL1_EID_SHIFT 24
970 #define MIPS_GCTL1_EID_WIDTH 8
971 #define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
973 /* GuestID reserved for root context */
974 #define MIPS_GCTL1_ROOT_GUESTID 0
976 /* CDMMBase register bit definitions */
977 #define MIPS_CDMMBASE_SIZE_SHIFT 0
978 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
979 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
980 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
981 #define MIPS_CDMMBASE_ADDR_SHIFT 11
982 #define MIPS_CDMMBASE_ADDR_START 15
984 /* RDHWR register numbers */
985 #define MIPS_HWR_CPUNUM 0 /* CPU number */
986 #define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
987 #define MIPS_HWR_CC 2 /* Cycle counter */
988 #define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
989 #define MIPS_HWR_ULR 29 /* UserLocal */
990 #define MIPS_HWR_IMPL1 30 /* Implementation dependent */
991 #define MIPS_HWR_IMPL2 31 /* Implementation dependent */
993 /* Bits in HWREna register */
994 #define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
995 #define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
996 #define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
997 #define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
998 #define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
999 #define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
1000 #define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
1003 * Bitfields in the TX39 family CP0 Configuration Register 3
1005 #define TX39_CONF_ICS_SHIFT 19
1006 #define TX39_CONF_ICS_MASK 0x00380000
1007 #define TX39_CONF_ICS_1KB 0x00000000
1008 #define TX39_CONF_ICS_2KB 0x00080000
1009 #define TX39_CONF_ICS_4KB 0x00100000
1010 #define TX39_CONF_ICS_8KB 0x00180000
1011 #define TX39_CONF_ICS_16KB 0x00200000
1013 #define TX39_CONF_DCS_SHIFT 16
1014 #define TX39_CONF_DCS_MASK 0x00070000
1015 #define TX39_CONF_DCS_1KB 0x00000000
1016 #define TX39_CONF_DCS_2KB 0x00010000
1017 #define TX39_CONF_DCS_4KB 0x00020000
1018 #define TX39_CONF_DCS_8KB 0x00030000
1019 #define TX39_CONF_DCS_16KB 0x00040000
1021 #define TX39_CONF_CWFON 0x00004000
1022 #define TX39_CONF_WBON 0x00002000
1023 #define TX39_CONF_RF_SHIFT 10
1024 #define TX39_CONF_RF_MASK 0x00000c00
1025 #define TX39_CONF_DOZE 0x00000200
1026 #define TX39_CONF_HALT 0x00000100
1027 #define TX39_CONF_LOCK 0x00000080
1028 #define TX39_CONF_ICE 0x00000020
1029 #define TX39_CONF_DCE 0x00000010
1030 #define TX39_CONF_IRSIZE_SHIFT 2
1031 #define TX39_CONF_IRSIZE_MASK 0x0000000c
1032 #define TX39_CONF_DRSIZE_SHIFT 0
1033 #define TX39_CONF_DRSIZE_MASK 0x00000003
1036 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
1038 /* Disable Branch Target Address Cache */
1039 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
1040 /* Enable Branch Prediction Global History */
1041 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
1042 /* Disable Branch Return Cache */
1043 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
1046 #define LOONGSON_DIAG_BTB (_ULCAST_(1) << 1)
1048 #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
1050 #define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
1051 /* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
1052 #define LOONGSON_DIAG_UCAC (_ULCAST_(1) << 8)
1054 #define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
1056 #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
1059 * Diag1 (GSCause in Loongson-speak) fields
1061 /* Loongson-specific exception code (GSExcCode) */
1062 #define LOONGSON_DIAG1_EXCCODE_SHIFT 2
1063 #define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)
1065 /* CvmCtl register field definitions */
1066 #define CVMCTL_IPPCI_SHIFT 7
1067 #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1068 #define CVMCTL_IPTI_SHIFT 4
1069 #define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1071 /* CvmMemCtl2 register field definitions */
1072 #define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1074 /* CvmVMConfig register field definitions */
1075 #define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1076 #define CVMVMCONF_MMUSIZEM1_S 12
1077 #define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1078 #define CVMVMCONF_RMMUSIZEM1_S 0
1079 #define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1082 * Coprocessor 1 (FPU) register names
1084 #define CP1_REVISION $0
1087 #define CP1_FCCR $25
1088 #define CP1_FEXR $26
1089 #define CP1_FENR $28
1090 #define CP1_STATUS $31
1094 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1096 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
1097 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
1098 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1099 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1100 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
1101 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
1102 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1103 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1104 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1105 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1108 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1110 #define MIPS_FCCR_CONDX_S 0
1111 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1112 #define MIPS_FCCR_COND0_S 0
1113 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1114 #define MIPS_FCCR_COND1_S 1
1115 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1116 #define MIPS_FCCR_COND2_S 2
1117 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1118 #define MIPS_FCCR_COND3_S 3
1119 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1120 #define MIPS_FCCR_COND4_S 4
1121 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1122 #define MIPS_FCCR_COND5_S 5
1123 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1124 #define MIPS_FCCR_COND6_S 6
1125 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1126 #define MIPS_FCCR_COND7_S 7
1127 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1130 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1132 #define MIPS_FENR_FS_S 2
1133 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1136 * FPU Status Register Values
1138 #define FPU_CSR_COND_S 23 /* $fcc0 */
1139 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1141 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1142 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1144 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1145 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1146 #define FPU_CSR_COND1_S 25 /* $fcc1 */
1147 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1148 #define FPU_CSR_COND2_S 26 /* $fcc2 */
1149 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1150 #define FPU_CSR_COND3_S 27 /* $fcc3 */
1151 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1152 #define FPU_CSR_COND4_S 28 /* $fcc4 */
1153 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1154 #define FPU_CSR_COND5_S 29 /* $fcc5 */
1155 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1156 #define FPU_CSR_COND6_S 30 /* $fcc6 */
1157 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1158 #define FPU_CSR_COND7_S 31 /* $fcc7 */
1159 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1162 * Bits 22:20 of the FPU Status Register will be read as 0,
1163 * and should be written as zero.
1164 * MAC2008 was removed in Release 5 so we still treat it as
1167 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1169 #define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1170 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1171 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1174 * X the exception cause indicator
1175 * E the exception enable
1176 * S the sticky/flag bit
1178 #define FPU_CSR_ALL_X 0x0003f000
1179 #define FPU_CSR_UNI_X 0x00020000
1180 #define FPU_CSR_INV_X 0x00010000
1181 #define FPU_CSR_DIV_X 0x00008000
1182 #define FPU_CSR_OVF_X 0x00004000
1183 #define FPU_CSR_UDF_X 0x00002000
1184 #define FPU_CSR_INE_X 0x00001000
1186 #define FPU_CSR_ALL_E 0x00000f80
1187 #define FPU_CSR_INV_E 0x00000800
1188 #define FPU_CSR_DIV_E 0x00000400
1189 #define FPU_CSR_OVF_E 0x00000200
1190 #define FPU_CSR_UDF_E 0x00000100
1191 #define FPU_CSR_INE_E 0x00000080
1193 #define FPU_CSR_ALL_S 0x0000007c
1194 #define FPU_CSR_INV_S 0x00000040
1195 #define FPU_CSR_DIV_S 0x00000020
1196 #define FPU_CSR_OVF_S 0x00000010
1197 #define FPU_CSR_UDF_S 0x00000008
1198 #define FPU_CSR_INE_S 0x00000004
1200 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1201 #define FPU_CSR_RM 0x00000003
1202 #define FPU_CSR_RN 0x0 /* nearest */
1203 #define FPU_CSR_RZ 0x1 /* towards zero */
1204 #define FPU_CSR_RU 0x2 /* towards +Infinity */
1205 #define FPU_CSR_RD 0x3 /* towards -Infinity */
1208 #ifndef __ASSEMBLY__
1211 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1213 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1214 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1215 #define get_isa16_mode(x) ((x) & 0x1)
1216 #define msk_isa16_mode(x) ((x) & ~0x1)
1217 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1219 #define get_isa16_mode(x) 0
1220 #define msk_isa16_mode(x) (x)
1221 #define set_isa16_mode(x) do { } while(0)
1225 * microMIPS instructions can be 16-bit or 32-bit in length. This
1226 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1228 static inline int mm_insn_16bit(u16 insn)
1230 u16 opcode = (insn >> 10) & 0x7;
1232 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1236 * Helper macros for generating raw instruction encodings in inline asm.
1238 #ifdef CONFIG_CPU_MICROMIPS
1239 #define _ASM_INSN16_IF_MM(_enc) \
1241 ".hword (" #_enc ")\n\t"
1242 #define _ASM_INSN32_IF_MM(_enc) \
1244 ".hword ((" #_enc ") >> 16)\n\t" \
1245 ".hword ((" #_enc ") & 0xffff)\n\t"
1247 #define _ASM_INSN_IF_MIPS(_enc) \
1249 ".word (" #_enc ")\n\t"
1252 #ifndef _ASM_INSN16_IF_MM
1253 #define _ASM_INSN16_IF_MM(_enc)
1255 #ifndef _ASM_INSN32_IF_MM
1256 #define _ASM_INSN32_IF_MM(_enc)
1258 #ifndef _ASM_INSN_IF_MIPS
1259 #define _ASM_INSN_IF_MIPS(_enc)
1263 * parse_r var, r - Helper assembler macro for parsing register names.
1265 * This converts the register name in $n form provided in \r to the
1266 * corresponding register number, which is assigned to the variable \var. It is
1267 * needed to allow explicit encoding of instructions in inline assembly where
1268 * registers are chosen by the compiler in $n form, allowing us to avoid using
1269 * fixed register numbers.
1271 * It also allows newer instructions (not implemented by the assembler) to be
1272 * transparently implemented using assembler macros, instead of needing separate
1273 * cases depending on toolchain support.
1275 * Simple usage example:
1276 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1279 * ".word (0x41606000 | (__rt << 16))"
1283 /* Match an individual register number and assign to \var */
1284 #define _IFC_REG(n) \
1285 ".ifc \\r, $" #n "\n\t" \
1286 "\\var = " #n "\n\t" \
1289 __asm__(".macro parse_r var r\n\t"
1291 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1292 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
1293 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
1294 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1295 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1296 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1297 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1298 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1300 ".error \"Unable to parse register name \\r\"\n\t"
1307 * C macros for generating assembler macros for common instruction formats.
1309 * The names of the operands can be chosen by the caller, and the encoding of
1310 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1311 * the ENC encodings.
1314 /* Instructions with no operands */
1315 #define _ASM_MACRO_0(OP, ENC) \
1316 __asm__(".macro " #OP "\n\t" \
1320 /* Instructions with 1 register operand & 1 immediate operand */
1321 #define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
1322 __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
1323 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1327 /* Instructions with 2 register operands */
1328 #define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1329 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1330 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1331 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1335 /* Instructions with 3 register operands */
1336 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1337 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1338 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1339 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1340 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1344 /* Instructions with 2 register operands and 1 optional select operand */
1345 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1346 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1347 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1348 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1353 * TLB Invalidate Flush
1355 static inline void tlbinvf(void)
1357 __asm__ __volatile__(
1359 ".set noreorder\n\t"
1361 _ASM_INSN_IF_MIPS(0x42000004)
1362 _ASM_INSN32_IF_MM(0x0000537c)
1368 * Functions to access the R10000 performance counters. These are basically
1369 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1370 * performance counter number encoded into bits 1 ... 5 of the instruction.
1371 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1372 * disassembler these will look like an access to sel 0 or 1.
1374 #define read_r10k_perf_cntr(counter) \
1376 unsigned int __res; \
1377 __asm__ __volatile__( \
1385 #define write_r10k_perf_cntr(counter,val) \
1387 __asm__ __volatile__( \
1390 : "r" (val), "i" (counter)); \
1393 #define read_r10k_perf_event(counter) \
1395 unsigned int __res; \
1396 __asm__ __volatile__( \
1404 #define write_r10k_perf_cntl(counter,val) \
1406 __asm__ __volatile__( \
1409 : "r" (val), "i" (counter)); \
1414 * Macros to access the system control coprocessor
1417 #define ___read_32bit_c0_register(source, sel, vol) \
1418 ({ unsigned int __res; \
1421 "mfc0\t%0, " #source "\n\t" \
1426 ".set\tmips32\n\t" \
1427 "mfc0\t%0, " #source ", " #sel "\n\t" \
1433 #define ___read_64bit_c0_register(source, sel, vol) \
1434 ({ unsigned long long __res; \
1435 if (sizeof(unsigned long) == 4) \
1436 __res = __read_64bit_c0_split(source, sel, vol); \
1437 else if (sel == 0) \
1441 "dmfc0\t%0, " #source "\n\t" \
1447 ".set\tmips64\n\t" \
1448 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1454 #define __read_32bit_c0_register(source, sel) \
1455 ___read_32bit_c0_register(source, sel, __volatile__)
1457 #define __read_const_32bit_c0_register(source, sel) \
1458 ___read_32bit_c0_register(source, sel,)
1460 #define __read_64bit_c0_register(source, sel) \
1461 ___read_64bit_c0_register(source, sel, __volatile__)
1463 #define __read_const_64bit_c0_register(source, sel) \
1464 ___read_64bit_c0_register(source, sel,)
1466 #define __write_32bit_c0_register(register, sel, value) \
1469 __asm__ __volatile__( \
1470 "mtc0\t%z0, " #register "\n\t" \
1471 : : "Jr" ((unsigned int)(value))); \
1473 __asm__ __volatile__( \
1475 ".set\tmips32\n\t" \
1476 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1478 : : "Jr" ((unsigned int)(value))); \
1481 #define __write_64bit_c0_register(register, sel, value) \
1483 if (sizeof(unsigned long) == 4) \
1484 __write_64bit_c0_split(register, sel, value); \
1485 else if (sel == 0) \
1486 __asm__ __volatile__( \
1489 "dmtc0\t%z0, " #register "\n\t" \
1491 : : "Jr" (value)); \
1493 __asm__ __volatile__( \
1495 ".set\tmips64\n\t" \
1496 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1498 : : "Jr" (value)); \
1501 #define __read_ulong_c0_register(reg, sel) \
1502 ((sizeof(unsigned long) == 4) ? \
1503 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1504 (unsigned long) __read_64bit_c0_register(reg, sel))
1506 #define __read_const_ulong_c0_register(reg, sel) \
1507 ((sizeof(unsigned long) == 4) ? \
1508 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1509 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1511 #define __write_ulong_c0_register(reg, sel, val) \
1513 if (sizeof(unsigned long) == 4) \
1514 __write_32bit_c0_register(reg, sel, val); \
1516 __write_64bit_c0_register(reg, sel, val); \
1520 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1522 #define __read_32bit_c0_ctrl_register(source) \
1523 ({ unsigned int __res; \
1524 __asm__ __volatile__( \
1525 "cfc0\t%0, " #source "\n\t" \
1530 #define __write_32bit_c0_ctrl_register(register, value) \
1532 __asm__ __volatile__( \
1533 "ctc0\t%z0, " #register "\n\t" \
1534 : : "Jr" ((unsigned int)(value))); \
1538 * These versions are only needed for systems with more than 38 bits of
1539 * physical address space running the 32-bit kernel. That's none atm :-)
1541 #define __read_64bit_c0_split(source, sel, vol) \
1543 unsigned long long __val; \
1544 unsigned long __flags; \
1546 local_irq_save(__flags); \
1550 ".set\tmips64\n\t" \
1551 "dmfc0\t%L0, " #source "\n\t" \
1552 "dsra\t%M0, %L0, 32\n\t" \
1553 "sll\t%L0, %L0, 0\n\t" \
1559 ".set\tmips64\n\t" \
1560 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1561 "dsra\t%M0, %L0, 32\n\t" \
1562 "sll\t%L0, %L0, 0\n\t" \
1565 local_irq_restore(__flags); \
1570 #define __write_64bit_c0_split(source, sel, val) \
1572 unsigned long long __tmp = (val); \
1573 unsigned long __flags; \
1575 local_irq_save(__flags); \
1576 if (MIPS_ISA_REV >= 2) \
1577 __asm__ __volatile__( \
1579 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1580 "dins\t%L0, %M0, 32, 32\n\t" \
1581 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1584 else if (sel == 0) \
1585 __asm__ __volatile__( \
1587 ".set\tmips64\n\t" \
1588 "dsll\t%L0, %L0, 32\n\t" \
1589 "dsrl\t%L0, %L0, 32\n\t" \
1590 "dsll\t%M0, %M0, 32\n\t" \
1591 "or\t%L0, %L0, %M0\n\t" \
1592 "dmtc0\t%L0, " #source "\n\t" \
1596 __asm__ __volatile__( \
1598 ".set\tmips64\n\t" \
1599 "dsll\t%L0, %L0, 32\n\t" \
1600 "dsrl\t%L0, %L0, 32\n\t" \
1601 "dsll\t%M0, %M0, 32\n\t" \
1602 "or\t%L0, %L0, %M0\n\t" \
1603 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1606 local_irq_restore(__flags); \
1609 #ifndef TOOLCHAIN_SUPPORTS_XPA
1610 _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1611 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1612 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1613 _ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1614 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1615 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1616 #define _ASM_SET_XPA ""
1617 #else /* !TOOLCHAIN_SUPPORTS_XPA */
1618 #define _ASM_SET_XPA ".set\txpa\n\t"
1621 #define __readx_32bit_c0_register(source, sel) \
1623 unsigned int __res; \
1625 __asm__ __volatile__( \
1627 " .set mips32r2 \n" \
1629 " mfhc0 %0, " #source ", %1 \n" \
1636 #define __writex_32bit_c0_register(register, sel, value) \
1638 __asm__ __volatile__( \
1640 " .set mips32r2 \n" \
1642 " mthc0 %z0, " #register ", %1 \n" \
1645 : "Jr" (value), "i" (sel)); \
1648 #define read_c0_index() __read_32bit_c0_register($0, 0)
1649 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1651 #define read_c0_random() __read_32bit_c0_register($1, 0)
1652 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1654 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1655 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1657 #define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1658 #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1660 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1661 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1663 #define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1664 #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1666 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1667 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1669 #define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1671 #define read_c0_context() __read_ulong_c0_register($4, 0)
1672 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1674 #define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1675 #define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1677 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1678 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1680 #define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1681 #define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1683 #define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
1684 #define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
1686 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1687 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1689 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1690 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1692 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1693 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1695 #define read_c0_info() __read_32bit_c0_register($7, 0)
1697 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1698 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1700 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1701 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1703 #define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1704 #define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1706 #define read_c0_count() __read_32bit_c0_register($9, 0)
1707 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1709 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1710 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1712 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1713 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1715 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1716 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1718 #define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1719 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1721 #define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1722 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1724 #define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1725 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1727 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1728 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1730 #define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1731 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1733 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1734 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1736 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1737 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1739 #define read_c0_status() __read_32bit_c0_register($12, 0)
1741 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1743 #define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1744 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1746 #define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1747 #define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1749 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1750 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1752 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1753 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1755 #define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1757 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1759 #define read_c0_config() __read_32bit_c0_register($16, 0)
1760 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1761 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1762 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1763 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1764 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1765 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1766 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1767 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1768 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1769 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1770 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1771 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1772 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1773 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1774 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1776 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1777 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1778 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1779 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1780 #define readx_c0_maar() __readx_32bit_c0_register($17, 1)
1781 #define writex_c0_maar(val) __writex_32bit_c0_register($17, 1, val)
1782 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1783 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1786 * The WatchLo register. There may be up to 8 of them.
1788 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1789 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1790 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1791 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1792 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1793 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1794 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1795 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1796 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1797 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1798 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1799 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1800 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1801 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1802 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1803 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1806 * The WatchHi register. There may be up to 8 of them.
1808 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1809 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1810 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1811 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1812 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1813 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1814 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1815 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1817 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1818 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1819 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1820 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1821 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1822 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1823 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1824 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1826 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1827 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1829 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1830 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1832 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1833 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1835 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1836 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1838 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1839 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1840 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1842 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1843 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1845 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1846 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1848 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1849 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1851 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1852 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1854 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1855 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1857 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1858 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1860 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1861 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1864 * MIPS32 / MIPS64 performance counters
1866 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1867 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1868 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1869 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1870 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1871 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1872 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1873 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1874 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1875 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1876 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1877 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1878 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1879 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1880 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1881 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1882 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1883 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1884 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1885 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1886 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1887 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1888 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1889 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1891 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1892 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1894 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1895 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1897 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1899 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1900 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1902 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1903 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1905 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1906 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1908 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1909 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1911 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1912 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1914 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1915 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1917 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1918 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1921 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1922 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1924 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1925 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1927 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1928 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1930 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1931 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1933 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1934 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1936 #define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1937 #define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1939 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1940 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1943 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1944 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1946 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1947 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1949 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1950 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1952 /* Hardware Page Table Walker */
1953 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1954 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1956 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1957 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1959 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1960 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1962 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1963 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1965 #define read_c0_pgd() __read_64bit_c0_register($9, 7)
1966 #define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1968 #define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1969 #define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1971 /* Cavium OCTEON (cnMIPS) */
1972 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1973 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1975 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1976 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1978 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1979 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1981 #define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1982 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1984 #define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1985 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1988 * The cacheerr registers are not standardized. On OCTEON, they are
1991 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1992 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1994 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1995 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1998 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1999 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
2001 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
2002 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
2004 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
2005 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
2008 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
2009 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
2011 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
2012 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
2014 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
2015 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
2017 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
2018 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
2020 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
2021 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
2024 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
2025 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
2027 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
2028 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
2030 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
2031 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
2033 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
2034 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
2036 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
2037 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
2039 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
2040 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
2042 /* Ingenic page ctrl register */
2043 #define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
2046 * Macros to access the guest system control coprocessor
2049 #ifndef TOOLCHAIN_SUPPORTS_VIRT
2050 _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
2051 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
2052 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
2053 _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
2054 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
2055 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
2056 _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
2057 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
2058 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2059 _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
2060 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
2061 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2062 _ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
2063 _ASM_INSN32_IF_MM(0x0000017c));
2064 _ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
2065 _ASM_INSN32_IF_MM(0x0000117c));
2066 _ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
2067 _ASM_INSN32_IF_MM(0x0000217c));
2068 _ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
2069 _ASM_INSN32_IF_MM(0x0000317c));
2070 _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
2071 _ASM_INSN32_IF_MM(0x0000517c));
2072 #define _ASM_SET_VIRT ""
2073 #else /* !TOOLCHAIN_SUPPORTS_VIRT */
2074 #define _ASM_SET_VIRT ".set\tvirt\n\t"
2077 #define __read_32bit_gc0_register(source, sel) \
2079 __asm__ __volatile__( \
2081 ".set\tmips32r2\n\t" \
2083 "mfgc0\t%0, " #source ", %1\n\t" \
2090 #define __read_64bit_gc0_register(source, sel) \
2091 ({ unsigned long long __res; \
2092 __asm__ __volatile__( \
2094 ".set\tmips64r2\n\t" \
2096 "dmfgc0\t%0, " #source ", %1\n\t" \
2103 #define __write_32bit_gc0_register(register, sel, value) \
2105 __asm__ __volatile__( \
2107 ".set\tmips32r2\n\t" \
2109 "mtgc0\t%z0, " #register ", %1\n\t" \
2111 : : "Jr" ((unsigned int)(value)), \
2115 #define __write_64bit_gc0_register(register, sel, value) \
2117 __asm__ __volatile__( \
2119 ".set\tmips64r2\n\t" \
2121 "dmtgc0\t%z0, " #register ", %1\n\t" \
2127 #define __read_ulong_gc0_register(reg, sel) \
2128 ((sizeof(unsigned long) == 4) ? \
2129 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2130 (unsigned long) __read_64bit_gc0_register(reg, sel))
2132 #define __write_ulong_gc0_register(reg, sel, val) \
2134 if (sizeof(unsigned long) == 4) \
2135 __write_32bit_gc0_register(reg, sel, val); \
2137 __write_64bit_gc0_register(reg, sel, val); \
2140 #define read_gc0_index() __read_32bit_gc0_register($0, 0)
2141 #define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2143 #define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2144 #define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2146 #define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2147 #define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2149 #define read_gc0_context() __read_ulong_gc0_register($4, 0)
2150 #define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2152 #define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2153 #define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2155 #define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2156 #define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2158 #define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2159 #define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2161 #define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2162 #define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2164 #define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2165 #define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2167 #define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2168 #define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2170 #define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2171 #define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2173 #define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2174 #define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2176 #define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2177 #define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2179 #define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2180 #define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2182 #define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2183 #define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2185 #define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2186 #define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2188 #define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2189 #define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2191 #define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2192 #define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2194 #define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2195 #define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2197 #define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2198 #define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2200 #define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2201 #define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2203 #define read_gc0_count() __read_32bit_gc0_register($9, 0)
2205 #define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2206 #define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2208 #define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2209 #define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2211 #define read_gc0_status() __read_32bit_gc0_register($12, 0)
2212 #define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2214 #define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2215 #define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2217 #define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2218 #define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2220 #define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2221 #define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2223 #define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2225 #define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2226 #define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2228 #define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2229 #define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2231 #define read_gc0_config() __read_32bit_gc0_register($16, 0)
2232 #define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2233 #define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2234 #define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2235 #define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2236 #define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2237 #define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2238 #define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2239 #define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2240 #define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2241 #define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2242 #define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2243 #define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2244 #define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2245 #define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2246 #define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2248 #define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2249 #define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2251 #define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2252 #define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2253 #define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2254 #define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2255 #define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2256 #define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2257 #define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2258 #define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2259 #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2260 #define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2261 #define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2262 #define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2263 #define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2264 #define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2265 #define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2266 #define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2268 #define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2269 #define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2270 #define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2271 #define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2272 #define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2273 #define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2274 #define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2275 #define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2276 #define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2277 #define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2278 #define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2279 #define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2280 #define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2281 #define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2282 #define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2283 #define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2285 #define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2286 #define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2288 #define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2289 #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2290 #define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2291 #define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2292 #define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2293 #define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2294 #define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2295 #define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2296 #define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2297 #define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2298 #define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2299 #define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2300 #define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2301 #define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2302 #define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2303 #define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2304 #define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2305 #define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2306 #define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2307 #define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2308 #define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2309 #define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2310 #define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2311 #define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2313 #define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2314 #define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2316 #define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2317 #define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2318 #define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2319 #define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2320 #define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2321 #define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2322 #define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2323 #define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2324 #define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2325 #define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2326 #define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2327 #define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2329 /* Cavium OCTEON (cnMIPS) */
2330 #define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2331 #define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2333 #define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2334 #define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2336 #define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2337 #define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2339 #define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2340 #define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2343 * Macros to access the floating point coprocessor control registers
2345 #define _read_32bit_cp1_register(source, gas_hardfloat) \
2347 unsigned int __res; \
2349 __asm__ __volatile__( \
2351 " .set reorder \n" \
2352 " # gas fails to assemble cfc1 for some archs, \n" \
2353 " # like Octeon. \n" \
2355 " "STR(gas_hardfloat)" \n" \
2356 " cfc1 %0,"STR(source)" \n" \
2362 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2364 __asm__ __volatile__( \
2366 " .set reorder \n" \
2367 " "STR(gas_hardfloat)" \n" \
2368 " ctc1 %0,"STR(dest)" \n" \
2373 #ifdef GAS_HAS_SET_HARDFLOAT
2374 #define read_32bit_cp1_register(source) \
2375 _read_32bit_cp1_register(source, .set hardfloat)
2376 #define write_32bit_cp1_register(dest, val) \
2377 _write_32bit_cp1_register(dest, val, .set hardfloat)
2379 #define read_32bit_cp1_register(source) \
2380 _read_32bit_cp1_register(source, )
2381 #define write_32bit_cp1_register(dest, val) \
2382 _write_32bit_cp1_register(dest, val, )
2385 #ifdef TOOLCHAIN_SUPPORTS_DSP
2386 #define rddsp(mask) \
2388 unsigned int __dspctl; \
2390 __asm__ __volatile__( \
2392 " .set " MIPS_ISA_LEVEL " \n" \
2394 " rddsp %0, %x1 \n" \
2401 #define wrdsp(val, mask) \
2403 __asm__ __volatile__( \
2405 " .set " MIPS_ISA_LEVEL " \n" \
2407 " wrdsp %0, %x1 \n" \
2410 : "r" (val), "i" (mask)); \
2418 " .set " MIPS_ISA_LEVEL " \n" \
2420 " mflo %0, $ac0 \n" \
2431 " .set " MIPS_ISA_LEVEL " \n" \
2433 " mflo %0, $ac1 \n" \
2444 " .set " MIPS_ISA_LEVEL " \n" \
2446 " mflo %0, $ac2 \n" \
2457 " .set " MIPS_ISA_LEVEL " \n" \
2459 " mflo %0, $ac3 \n" \
2470 " .set " MIPS_ISA_LEVEL " \n" \
2472 " mfhi %0, $ac0 \n" \
2483 " .set " MIPS_ISA_LEVEL " \n" \
2485 " mfhi %0, $ac1 \n" \
2496 " .set " MIPS_ISA_LEVEL " \n" \
2498 " mfhi %0, $ac2 \n" \
2509 " .set " MIPS_ISA_LEVEL " \n" \
2511 " mfhi %0, $ac3 \n" \
2522 " .set " MIPS_ISA_LEVEL " \n" \
2524 " mtlo %0, $ac0 \n" \
2534 " .set " MIPS_ISA_LEVEL " \n" \
2536 " mtlo %0, $ac1 \n" \
2546 " .set " MIPS_ISA_LEVEL " \n" \
2548 " mtlo %0, $ac2 \n" \
2558 " .set " MIPS_ISA_LEVEL " \n" \
2560 " mtlo %0, $ac3 \n" \
2570 " .set " MIPS_ISA_LEVEL " \n" \
2572 " mthi %0, $ac0 \n" \
2582 " .set " MIPS_ISA_LEVEL " \n" \
2584 " mthi %0, $ac1 \n" \
2594 " .set " MIPS_ISA_LEVEL " \n" \
2596 " mthi %0, $ac2 \n" \
2606 " .set " MIPS_ISA_LEVEL " \n" \
2608 " mthi %0, $ac3 \n" \
2616 #define rddsp(mask) \
2618 unsigned int __res; \
2620 __asm__ __volatile__( \
2623 " # rddsp $1, %x1 \n" \
2624 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2625 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2633 #define wrdsp(val, mask) \
2635 __asm__ __volatile__( \
2639 " # wrdsp $1, %x1 \n" \
2640 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2641 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2644 : "r" (val), "i" (mask)); \
2647 #define _dsp_mfxxx(ins) \
2649 unsigned long __treg; \
2651 __asm__ __volatile__( \
2654 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2655 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2663 #define _dsp_mtxxx(val, ins) \
2665 __asm__ __volatile__( \
2669 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2670 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2673 : "r" (val), "i" (ins)); \
2676 #ifdef CONFIG_CPU_MICROMIPS
2678 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2679 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2681 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2682 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2684 #else /* !CONFIG_CPU_MICROMIPS */
2686 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2687 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2689 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2690 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2692 #endif /* CONFIG_CPU_MICROMIPS */
2694 #define mflo0() _dsp_mflo(0)
2695 #define mflo1() _dsp_mflo(1)
2696 #define mflo2() _dsp_mflo(2)
2697 #define mflo3() _dsp_mflo(3)
2699 #define mfhi0() _dsp_mfhi(0)
2700 #define mfhi1() _dsp_mfhi(1)
2701 #define mfhi2() _dsp_mfhi(2)
2702 #define mfhi3() _dsp_mfhi(3)
2704 #define mtlo0(x) _dsp_mtlo(x, 0)
2705 #define mtlo1(x) _dsp_mtlo(x, 1)
2706 #define mtlo2(x) _dsp_mtlo(x, 2)
2707 #define mtlo3(x) _dsp_mtlo(x, 3)
2709 #define mthi0(x) _dsp_mthi(x, 0)
2710 #define mthi1(x) _dsp_mthi(x, 1)
2711 #define mthi2(x) _dsp_mthi(x, 2)
2712 #define mthi3(x) _dsp_mthi(x, 3)
2719 * It is responsibility of the caller to take care of any TLB hazards.
2721 static inline void tlb_probe(void)
2723 __asm__ __volatile__(
2724 ".set noreorder\n\t"
2729 static inline void tlb_read(void)
2731 #if MIPS34K_MISSED_ITLB_WAR
2734 __asm__ __volatile__(
2736 " .set noreorder \n"
2739 " .word 0x41610001 # dvpe $1 \n"
2745 instruction_hazard();
2748 __asm__ __volatile__(
2749 ".set noreorder\n\t"
2753 #if MIPS34K_MISSED_ITLB_WAR
2754 if ((res & _ULCAST_(1)))
2755 __asm__ __volatile__(
2757 " .set noreorder \n"
2760 " .word 0x41600021 # evpe \n"
2766 static inline void tlb_write_indexed(void)
2768 __asm__ __volatile__(
2769 ".set noreorder\n\t"
2774 static inline void tlb_write_random(void)
2776 __asm__ __volatile__(
2777 ".set noreorder\n\t"
2783 * Guest TLB operations.
2785 * It is responsibility of the caller to take care of any TLB hazards.
2787 static inline void guest_tlb_probe(void)
2789 __asm__ __volatile__(
2791 ".set noreorder\n\t"
2797 static inline void guest_tlb_read(void)
2799 __asm__ __volatile__(
2801 ".set noreorder\n\t"
2807 static inline void guest_tlb_write_indexed(void)
2809 __asm__ __volatile__(
2811 ".set noreorder\n\t"
2817 static inline void guest_tlb_write_random(void)
2819 __asm__ __volatile__(
2821 ".set noreorder\n\t"
2828 * Guest TLB Invalidate Flush
2830 static inline void guest_tlbinvf(void)
2832 __asm__ __volatile__(
2834 ".set noreorder\n\t"
2841 * Manipulate bits in a register.
2843 #define __BUILD_SET_COMMON(name) \
2844 static inline unsigned int \
2845 set_##name(unsigned int set) \
2847 unsigned int res, new; \
2849 res = read_##name(); \
2851 write_##name(new); \
2856 static inline unsigned int \
2857 clear_##name(unsigned int clear) \
2859 unsigned int res, new; \
2861 res = read_##name(); \
2862 new = res & ~clear; \
2863 write_##name(new); \
2868 static inline unsigned int \
2869 change_##name(unsigned int change, unsigned int val) \
2871 unsigned int res, new; \
2873 res = read_##name(); \
2874 new = res & ~change; \
2875 new |= (val & change); \
2876 write_##name(new); \
2882 * Manipulate bits in a c0 register.
2884 #define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2886 __BUILD_SET_C0(status)
2887 __BUILD_SET_C0(cause)
2888 __BUILD_SET_C0(config)
2889 __BUILD_SET_C0(config5)
2890 __BUILD_SET_C0(config6)
2891 __BUILD_SET_C0(config7)
2892 __BUILD_SET_C0(diag)
2893 __BUILD_SET_C0(intcontrol)
2894 __BUILD_SET_C0(intctl)
2895 __BUILD_SET_C0(srsmap)
2896 __BUILD_SET_C0(pagegrain)
2897 __BUILD_SET_C0(guestctl0)
2898 __BUILD_SET_C0(guestctl0ext)
2899 __BUILD_SET_C0(guestctl1)
2900 __BUILD_SET_C0(guestctl2)
2901 __BUILD_SET_C0(guestctl3)
2902 __BUILD_SET_C0(brcm_config_0)
2903 __BUILD_SET_C0(brcm_bus_pll)
2904 __BUILD_SET_C0(brcm_reset)
2905 __BUILD_SET_C0(brcm_cmt_intr)
2906 __BUILD_SET_C0(brcm_cmt_ctrl)
2907 __BUILD_SET_C0(brcm_config)
2908 __BUILD_SET_C0(brcm_mode)
2911 * Manipulate bits in a guest c0 register.
2913 #define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2915 __BUILD_SET_GC0(wired)
2916 __BUILD_SET_GC0(status)
2917 __BUILD_SET_GC0(cause)
2918 __BUILD_SET_GC0(ebase)
2919 __BUILD_SET_GC0(config1)
2922 * Return low 10 bits of ebase.
2923 * Note that under KVM (MIPSVZ) this returns vcpu id.
2925 static inline unsigned int get_ebase_cpunum(void)
2927 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2930 #endif /* !__ASSEMBLY__ */
2932 #endif /* _ASM_MIPSREGS_H */