arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <asm/hazards.h>
  18 #include <asm/war.h>
  19
  20 /*
  21  * The following macros are especially useful for __asm__
  22  * inline assembler.
  23  */
  24 #ifndef __STR
  25 #define __STR(x) #x
  26 #endif
  27 #ifndef STR
  28 #define STR(x) __STR(x)
  29 #endif
  30
  31 /*
  32  *  Configure language
  33  */
  34 #ifdef __ASSEMBLY__
  35 #define _ULCAST_
  36 #else
  37 #define _ULCAST_ (unsigned long)
  38 #endif
  39
  40 /*
  41  * Coprocessor 0 register names
  42  */
  43 #define CP0_INDEX $0
  44 #define CP0_RANDOM $1
  45 #define CP0_ENTRYLO0 $2
  46 #define CP0_ENTRYLO1 $3
  47 #define CP0_CONF $3
  48 #define CP0_CONTEXT $4
  49 #define CP0_PAGEMASK $5
  50 #define CP0_WIRED $6
  51 #define CP0_INFO $7
  52 #define CP0_BADVADDR $8
  53 #define CP0_COUNT $9
  54 #define CP0_ENTRYHI $10
  55 #define CP0_COMPARE $11
  56 #define CP0_STATUS $12
  57 #define CP0_CAUSE $13
  58 #define CP0_EPC $14
  59 #define CP0_PRID $15
  60 #define CP0_CONFIG $16
  61 #define CP0_LLADDR $17
  62 #define CP0_WATCHLO $18
  63 #define CP0_WATCHHI $19
  64 #define CP0_XCONTEXT $20
  65 #define CP0_FRAMEMASK $21
  66 #define CP0_DIAGNOSTIC $22
  67 #define CP0_DEBUG $23
  68 #define CP0_DEPC $24
  69 #define CP0_PERFORMANCE $25
  70 #define CP0_ECC $26
  71 #define CP0_CACHEERR $27
  72 #define CP0_TAGLO $28
  73 #define CP0_TAGHI $29
  74 #define CP0_ERROREPC $30
  75 #define CP0_DESAVE $31
  76
  77 /*
  78  * R4640/R4650 cp0 register names.  These registers are listed
  79  * here only for completeness; without MMU these CPUs are not useable
  80  * by Linux.  A future ELKS port might take make Linux run on them
  81  * though ...
  82  */
  83 #define CP0_IBASE $0
  84 #define CP0_IBOUND $1
  85 #define CP0_DBASE $2
  86 #define CP0_DBOUND $3
  87 #define CP0_CALG $17
  88 #define CP0_IWATCH $18
  89 #define CP0_DWATCH $19
  90
  91 /*
  92  * Coprocessor 0 Set 1 register names
  93  */
  94 #define CP0_S1_DERRADDR0  $26
  95 #define CP0_S1_DERRADDR1  $27
  96 #define CP0_S1_INTCONTROL $20
  97
  98 /*
  99  * Coprocessor 0 Set 2 register names
 100  */
 101 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 102
 103 /*
 104  * Coprocessor 0 Set 3 register names
 105  */
 106 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 107
 108 /*
 109  *  TX39 Series
 110  */
 111 #define CP0_TX39_CACHE  $7
 112
 113 /*
 114  * Coprocessor 1 (FPU) register names
 115  */
 116 #define CP1_REVISION   $0
 117 #define CP1_STATUS     $31
 118
 119 /*
 120  * FPU Status Register Values
 121  */
 122 /*
 123  * Status Register Values
 124  */
 125
 126 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 127 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 128 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 129 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 130 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 131 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 132 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 133 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 134 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 135 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 136
 137 /*
 138  * Bits 18 - 20 of the FPU Status Register will be read as 0,
 139  * and should be written as zero.
 140  */
 141 #define FPU_CSR_RSVD    0x001c0000
 142
 143 /*
 144  * X the exception cause indicator
 145  * E the exception enable
 146  * S the sticky/flag bit
 147 */
 148 #define FPU_CSR_ALL_X   0x0003f000
 149 #define FPU_CSR_UNI_X   0x00020000
 150 #define FPU_CSR_INV_X   0x00010000
 151 #define FPU_CSR_DIV_X   0x00008000
 152 #define FPU_CSR_OVF_X   0x00004000
 153 #define FPU_CSR_UDF_X   0x00002000
 154 #define FPU_CSR_INE_X   0x00001000
 155
 156 #define FPU_CSR_ALL_E   0x00000f80
 157 #define FPU_CSR_INV_E   0x00000800
 158 #define FPU_CSR_DIV_E   0x00000400
 159 #define FPU_CSR_OVF_E   0x00000200
 160 #define FPU_CSR_UDF_E   0x00000100
 161 #define FPU_CSR_INE_E   0x00000080
 162
 163 #define FPU_CSR_ALL_S   0x0000007c
 164 #define FPU_CSR_INV_S   0x00000040
 165 #define FPU_CSR_DIV_S   0x00000020
 166 #define FPU_CSR_OVF_S   0x00000010
 167 #define FPU_CSR_UDF_S   0x00000008
 168 #define FPU_CSR_INE_S   0x00000004
 169
 170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 171 #define FPU_CSR_RM      0x00000003
 172 #define FPU_CSR_RN      0x0     /* nearest */
 173 #define FPU_CSR_RZ      0x1     /* towards zero */
 174 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 175 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 176
 177
 178 /*
 179  * Values for PageMask register
 180  */
 181 #ifdef CONFIG_CPU_VR41XX
 182
 183 /* Why doesn't stupidity hurt ... */
 184
 185 #define PM_1K           0x00000000
 186 #define PM_4K           0x00001800
 187 #define PM_16K          0x00007800
 188 #define PM_64K          0x0001f800
 189 #define PM_256K         0x0007f800
 190
 191 #else
 192
 193 #define PM_4K           0x00000000
 194 #define PM_8K           0x00002000
 195 #define PM_16K          0x00006000
 196 #define PM_32K          0x0000e000
 197 #define PM_64K          0x0001e000
 198 #define PM_128K         0x0003e000
 199 #define PM_256K         0x0007e000
 200 #define PM_512K         0x000fe000
 201 #define PM_1M           0x001fe000
 202 #define PM_2M           0x003fe000
 203 #define PM_4M           0x007fe000
 204 #define PM_8M           0x00ffe000
 205 #define PM_16M          0x01ffe000
 206 #define PM_32M          0x03ffe000
 207 #define PM_64M          0x07ffe000
 208 #define PM_256M         0x1fffe000
 209 #define PM_1G           0x7fffe000
 210
 211 #endif
 212
 213 /*
 214  * Default page size for a given kernel configuration
 215  */
 216 #ifdef CONFIG_PAGE_SIZE_4KB
 217 #define PM_DEFAULT_MASK PM_4K
 218 #elif defined(CONFIG_PAGE_SIZE_8KB)
 219 #define PM_DEFAULT_MASK PM_8K
 220 #elif defined(CONFIG_PAGE_SIZE_16KB)
 221 #define PM_DEFAULT_MASK PM_16K
 222 #elif defined(CONFIG_PAGE_SIZE_32KB)
 223 #define PM_DEFAULT_MASK PM_32K
 224 #elif defined(CONFIG_PAGE_SIZE_64KB)
 225 #define PM_DEFAULT_MASK PM_64K
 226 #else
 227 #error Bad page size configuration!
 228 #endif
 229
 230 /*
 231  * Default huge tlb size for a given kernel configuration
 232  */
 233 #ifdef CONFIG_PAGE_SIZE_4KB
 234 #define PM_HUGE_MASK    PM_1M
 235 #elif defined(CONFIG_PAGE_SIZE_8KB)
 236 #define PM_HUGE_MASK    PM_4M
 237 #elif defined(CONFIG_PAGE_SIZE_16KB)
 238 #define PM_HUGE_MASK    PM_16M
 239 #elif defined(CONFIG_PAGE_SIZE_32KB)
 240 #define PM_HUGE_MASK    PM_64M
 241 #elif defined(CONFIG_PAGE_SIZE_64KB)
 242 #define PM_HUGE_MASK    PM_256M
 243 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 244 #error Bad page size configuration for hugetlbfs!
 245 #endif
 246
 247 /*
 248  * Values used for computation of new tlb entries
 249  */
 250 #define PL_4K           12
 251 #define PL_16K          14
 252 #define PL_64K          16
 253 #define PL_256K         18
 254 #define PL_1M           20
 255 #define PL_4M           22
 256 #define PL_16M          24
 257 #define PL_64M          26
 258 #define PL_256M         28
 259
 260 /*
 261  * PageGrain bits
 262  */
 263 #define PG_RIE          (_ULCAST_(1) <<  31)
 264 #define PG_XIE          (_ULCAST_(1) <<  30)
 265 #define PG_ELPA         (_ULCAST_(1) <<  29)
 266 #define PG_ESP          (_ULCAST_(1) <<  28)
 267
 268 /*
 269  * R4x00 interrupt enable / cause bits
 270  */
 271 #define IE_SW0          (_ULCAST_(1) <<  8)
 272 #define IE_SW1          (_ULCAST_(1) <<  9)
 273 #define IE_IRQ0         (_ULCAST_(1) << 10)
 274 #define IE_IRQ1         (_ULCAST_(1) << 11)
 275 #define IE_IRQ2         (_ULCAST_(1) << 12)
 276 #define IE_IRQ3         (_ULCAST_(1) << 13)
 277 #define IE_IRQ4         (_ULCAST_(1) << 14)
 278 #define IE_IRQ5         (_ULCAST_(1) << 15)
 279
 280 /*
 281  * R4x00 interrupt cause bits
 282  */
 283 #define C_SW0           (_ULCAST_(1) <<  8)
 284 #define C_SW1           (_ULCAST_(1) <<  9)
 285 #define C_IRQ0          (_ULCAST_(1) << 10)
 286 #define C_IRQ1          (_ULCAST_(1) << 11)
 287 #define C_IRQ2          (_ULCAST_(1) << 12)
 288 #define C_IRQ3          (_ULCAST_(1) << 13)
 289 #define C_IRQ4          (_ULCAST_(1) << 14)
 290 #define C_IRQ5          (_ULCAST_(1) << 15)
 291
 292 /*
 293  * Bitfields in the R4xx0 cp0 status register
 294  */
 295 #define ST0_IE                  0x00000001
 296 #define ST0_EXL                 0x00000002
 297 #define ST0_ERL                 0x00000004
 298 #define ST0_KSU                 0x00000018
 299 #  define KSU_USER              0x00000010
 300 #  define KSU_SUPERVISOR        0x00000008
 301 #  define KSU_KERNEL            0x00000000
 302 #define ST0_UX                  0x00000020
 303 #define ST0_SX                  0x00000040
 304 #define ST0_KX                  0x00000080
 305 #define ST0_DE                  0x00010000
 306 #define ST0_CE                  0x00020000
 307
 308 /*
 309  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 310  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 311  * processors.
 312  */
 313 #define ST0_CO                  0x08000000
 314
 315 /*
 316  * Bitfields in the R[23]000 cp0 status register.
 317  */
 318 #define ST0_IEC                 0x00000001
 319 #define ST0_KUC                 0x00000002
 320 #define ST0_IEP                 0x00000004
 321 #define ST0_KUP                 0x00000008
 322 #define ST0_IEO                 0x00000010
 323 #define ST0_KUO                 0x00000020
 324 /* bits 6 & 7 are reserved on R[23]000 */
 325 #define ST0_ISC                 0x00010000
 326 #define ST0_SWC                 0x00020000
 327 #define ST0_CM                  0x00080000
 328
 329 /*
 330  * Bits specific to the R4640/R4650
 331  */
 332 #define ST0_UM                  (_ULCAST_(1) <<  4)
 333 #define ST0_IL                  (_ULCAST_(1) << 23)
 334 #define ST0_DL                  (_ULCAST_(1) << 24)
 335
 336 /*
 337  * Enable the MIPS MDMX and DSP ASEs
 338  */
 339 #define ST0_MX                  0x01000000
 340
 341 /*
 342  * Bitfields in the TX39 family CP0 Configuration Register 3
 343  */
 344 #define TX39_CONF_ICS_SHIFT     19
 345 #define TX39_CONF_ICS_MASK      0x00380000
 346 #define TX39_CONF_ICS_1KB       0x00000000
 347 #define TX39_CONF_ICS_2KB       0x00080000
 348 #define TX39_CONF_ICS_4KB       0x00100000
 349 #define TX39_CONF_ICS_8KB       0x00180000
 350 #define TX39_CONF_ICS_16KB      0x00200000
 351
 352 #define TX39_CONF_DCS_SHIFT     16
 353 #define TX39_CONF_DCS_MASK      0x00070000
 354 #define TX39_CONF_DCS_1KB       0x00000000
 355 #define TX39_CONF_DCS_2KB       0x00010000
 356 #define TX39_CONF_DCS_4KB       0x00020000
 357 #define TX39_CONF_DCS_8KB       0x00030000
 358 #define TX39_CONF_DCS_16KB      0x00040000
 359
 360 #define TX39_CONF_CWFON         0x00004000
 361 #define TX39_CONF_WBON          0x00002000
 362 #define TX39_CONF_RF_SHIFT      10
 363 #define TX39_CONF_RF_MASK       0x00000c00
 364 #define TX39_CONF_DOZE          0x00000200
 365 #define TX39_CONF_HALT          0x00000100
 366 #define TX39_CONF_LOCK          0x00000080
 367 #define TX39_CONF_ICE           0x00000020
 368 #define TX39_CONF_DCE           0x00000010
 369 #define TX39_CONF_IRSIZE_SHIFT  2
 370 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 371 #define TX39_CONF_DRSIZE_SHIFT  0
 372 #define TX39_CONF_DRSIZE_MASK   0x00000003
 373
 374 /*
 375  * Status register bits available in all MIPS CPUs.
 376  */
 377 #define ST0_IM                  0x0000ff00
 378 #define  STATUSB_IP0            8
 379 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 380 #define  STATUSB_IP1            9
 381 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 382 #define  STATUSB_IP2            10
 383 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 384 #define  STATUSB_IP3            11
 385 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 386 #define  STATUSB_IP4            12
 387 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 388 #define  STATUSB_IP5            13
 389 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 390 #define  STATUSB_IP6            14
 391 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 392 #define  STATUSB_IP7            15
 393 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 394 #define  STATUSB_IP8            0
 395 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 396 #define  STATUSB_IP9            1
 397 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 398 #define  STATUSB_IP10           2
 399 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 400 #define  STATUSB_IP11           3
 401 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 402 #define  STATUSB_IP12           4
 403 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 404 #define  STATUSB_IP13           5
 405 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 406 #define  STATUSB_IP14           6
 407 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 408 #define  STATUSB_IP15           7
 409 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 410 #define ST0_CH                  0x00040000
 411 #define ST0_NMI                 0x00080000
 412 #define ST0_SR                  0x00100000
 413 #define ST0_TS                  0x00200000
 414 #define ST0_BEV                 0x00400000
 415 #define ST0_RE                  0x02000000
 416 #define ST0_FR                  0x04000000
 417 #define ST0_CU                  0xf0000000
 418 #define ST0_CU0                 0x10000000
 419 #define ST0_CU1                 0x20000000
 420 #define ST0_CU2                 0x40000000
 421 #define ST0_CU3                 0x80000000
 422 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 423
 424 /*
 425  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 426  *
 427  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 428  */
 429 #define INTCTLB_IPPCI           26
 430 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 431 #define INTCTLB_IPTI            29
 432 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 433
 434 /*
 435  * Bitfields and bit numbers in the coprocessor 0 cause register.
 436  *
 437  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 438  */
 439 #define  CAUSEB_EXCCODE         2
 440 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 441 #define  CAUSEB_IP              8
 442 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 443 #define  CAUSEB_IP0             8
 444 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 445 #define  CAUSEB_IP1             9
 446 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 447 #define  CAUSEB_IP2             10
 448 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 449 #define  CAUSEB_IP3             11
 450 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 451 #define  CAUSEB_IP4             12
 452 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 453 #define  CAUSEB_IP5             13
 454 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 455 #define  CAUSEB_IP6             14
 456 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 457 #define  CAUSEB_IP7             15
 458 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 459 #define  CAUSEB_IV              23
 460 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 461 #define  CAUSEB_PCI             26
 462 #define  CAUSEF_PCI             (_ULCAST_(1)   << 26)
 463 #define  CAUSEB_CE              28
 464 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 465 #define  CAUSEB_TI              30
 466 #define  CAUSEF_TI              (_ULCAST_(1)   << 30)
 467 #define  CAUSEB_BD              31
 468 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 469
 470 /*
 471  * Bits in the coprocessor 0 config register.
 472  */
 473 /* Generic bits.  */
 474 #define CONF_CM_CACHABLE_NO_WA          0
 475 #define CONF_CM_CACHABLE_WA             1
 476 #define CONF_CM_UNCACHED                2
 477 #define CONF_CM_CACHABLE_NONCOHERENT    3
 478 #define CONF_CM_CACHABLE_CE             4
 479 #define CONF_CM_CACHABLE_COW            5
 480 #define CONF_CM_CACHABLE_CUW            6
 481 #define CONF_CM_CACHABLE_ACCELERATED    7
 482 #define CONF_CM_CMASK                   7
 483 #define CONF_BE                 (_ULCAST_(1) << 15)
 484
 485 /* Bits common to various processors.  */
 486 #define CONF_CU                 (_ULCAST_(1) <<  3)
 487 #define CONF_DB                 (_ULCAST_(1) <<  4)
 488 #define CONF_IB                 (_ULCAST_(1) <<  5)
 489 #define CONF_DC                 (_ULCAST_(7) <<  6)
 490 #define CONF_IC                 (_ULCAST_(7) <<  9)
 491 #define CONF_EB                 (_ULCAST_(1) << 13)
 492 #define CONF_EM                 (_ULCAST_(1) << 14)
 493 #define CONF_SM                 (_ULCAST_(1) << 16)
 494 #define CONF_SC                 (_ULCAST_(1) << 17)
 495 #define CONF_EW                 (_ULCAST_(3) << 18)
 496 #define CONF_EP                 (_ULCAST_(15)<< 24)
 497 #define CONF_EC                 (_ULCAST_(7) << 28)
 498 #define CONF_CM                 (_ULCAST_(1) << 31)
 499
 500 /* Bits specific to the R4xx0.  */
 501 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 502 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 503 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 504
 505 /* Bits specific to the R5000.  */
 506 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 507 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 508
 509 /* Bits specific to the RM7000.  */
 510 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 511 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 512 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 513 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 514 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 515 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 516
 517 /* Bits specific to the R10000.  */
 518 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 519 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 520 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 521 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 522 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 523 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 524 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 525 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 526 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 527 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 528 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 529
 530 /* Bits specific to the VR41xx.  */
 531 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 532 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 533 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 534 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 535 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 536
 537 /* Bits specific to the R30xx.  */
 538 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 539 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 540 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 541 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 542 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 543 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 544 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 545 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 546 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 547
 548 /* Bits specific to the TX49.  */
 549 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 550 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 551 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 552 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 553
 554 /* Bits specific to the MIPS32/64 PRA.  */
 555 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 556 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 557 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 558 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 559
 560 /*
 561  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 562  */
 563 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 564 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 565 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 566 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 567 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 568 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 569 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 570 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 571 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 572 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 573 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 574 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 575 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 576 #define MIPS_CONF1_TLBS_SHIFT   (25)
 577 #define MIPS_CONF1_TLBS_SIZE    (6)
 578 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 579
 580 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 581 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 582 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 583 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 584 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 585 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 586 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 587 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 588
 589 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 590 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 591 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 592 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 593 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 594 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 595 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 596 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 597 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 598 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 599 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 600 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 601 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 602 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 603 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 604 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 605 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 606 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 607 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 608 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 609 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 610 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 611 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 612 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 613 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 614 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 615 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 616
 617 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 618 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 619 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 620 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 621 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 622 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 623 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 624 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 625 /* bits 10:8 in FTLB-only configurations */
 626 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 627 /* bits 12:8 in VTLB-FTLB only configurations */
 628 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 629 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 630 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 631 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 632 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 633 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 634 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 635 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 636 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 637 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 638 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 639
 640 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 641 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 642 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 643 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 644 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 645 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 646
 647 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 648
 649 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 650
 651 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 652
 653 /*  EntryHI bit definition */
 654 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 655
 656 /*
 657  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 658  */
 659 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 660 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 661 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 662 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 663 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 664 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 665 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 666
 667 #ifndef __ASSEMBLY__
 668
 669 /*
 670  * Macros for handling the ISA mode bit for microMIPS.
 671  */
 672 #define get_isa16_mode(x)               ((x) & 0x1)
 673 #define msk_isa16_mode(x)               ((x) & ~0x1)
 674 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 675
 676 /*
 677  * microMIPS instructions can be 16-bit or 32-bit in length. This
 678  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 679  */
 680 static inline int mm_insn_16bit(u16 insn)
 681 {
 682         u16 opcode = (insn >> 10) & 0x7;
 683
 684         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 685 }
 686
 687 /*
 688  * Functions to access the R10000 performance counters.  These are basically
 689  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 690  * performance counter number encoded into bits 1 ... 5 of the instruction.
 691  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 692  * disassembler these will look like an access to sel 0 or 1.
 693  */
 694 #define read_r10k_perf_cntr(counter)                            \
 695 ({                                                              \
 696         unsigned int __res;                                     \
 697         __asm__ __volatile__(                                   \
 698         "mfpc\t%0, %1"                                          \
 699         : "=r" (__res)                                          \
 700         : "i" (counter));                                       \
 701                                                                 \
 702         __res;                                                  \
 703 })
 704
 705 #define write_r10k_perf_cntr(counter,val)                       \
 706 do {                                                            \
 707         __asm__ __volatile__(                                   \
 708         "mtpc\t%0, %1"                                          \
 709         :                                                       \
 710         : "r" (val), "i" (counter));                            \
 711 } while (0)
 712
 713 #define read_r10k_perf_event(counter)                           \
 714 ({                                                              \
 715         unsigned int __res;                                     \
 716         __asm__ __volatile__(                                   \
 717         "mfps\t%0, %1"                                          \
 718         : "=r" (__res)                                          \
 719         : "i" (counter));                                       \
 720                                                                 \
 721         __res;                                                  \
 722 })
 723
 724 #define write_r10k_perf_cntl(counter,val)                       \
 725 do {                                                            \
 726         __asm__ __volatile__(                                   \
 727         "mtps\t%0, %1"                                          \
 728         :                                                       \
 729         : "r" (val), "i" (counter));                            \
 730 } while (0)
 731
 732
 733 /*
 734  * Macros to access the system control coprocessor
 735  */
 736
 737 #define __read_32bit_c0_register(source, sel)                           \
 738 ({ int __res;                                                           \
 739         if (sel == 0)                                                   \
 740                 __asm__ __volatile__(                                   \
 741                         "mfc0\t%0, " #source "\n\t"                     \
 742                         : "=r" (__res));                                \
 743         else                                                            \
 744                 __asm__ __volatile__(                                   \
 745                         ".set\tmips32\n\t"                              \
 746                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 747                         ".set\tmips0\n\t"                               \
 748                         : "=r" (__res));                                \
 749         __res;                                                          \
 750 })
 751
 752 #define __read_64bit_c0_register(source, sel)                           \
 753 ({ unsigned long long __res;                                            \
 754         if (sizeof(unsigned long) == 4)                                 \
 755                 __res = __read_64bit_c0_split(source, sel);             \
 756         else if (sel == 0)                                              \
 757                 __asm__ __volatile__(                                   \
 758                         ".set\tmips3\n\t"                               \
 759                         "dmfc0\t%0, " #source "\n\t"                    \
 760                         ".set\tmips0"                                   \
 761                         : "=r" (__res));                                \
 762         else                                                            \
 763                 __asm__ __volatile__(                                   \
 764                         ".set\tmips64\n\t"                              \
 765                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 766                         ".set\tmips0"                                   \
 767                         : "=r" (__res));                                \
 768         __res;                                                          \
 769 })
 770
 771 #define __write_32bit_c0_register(register, sel, value)                 \
 772 do {                                                                    \
 773         if (sel == 0)                                                   \
 774                 __asm__ __volatile__(                                   \
 775                         "mtc0\t%z0, " #register "\n\t"                  \
 776                         : : "Jr" ((unsigned int)(value)));              \
 777         else                                                            \
 778                 __asm__ __volatile__(                                   \
 779                         ".set\tmips32\n\t"                              \
 780                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 781                         ".set\tmips0"                                   \
 782                         : : "Jr" ((unsigned int)(value)));              \
 783 } while (0)
 784
 785 #define __write_64bit_c0_register(register, sel, value)                 \
 786 do {                                                                    \
 787         if (sizeof(unsigned long) == 4)                                 \
 788                 __write_64bit_c0_split(register, sel, value);           \
 789         else if (sel == 0)                                              \
 790                 __asm__ __volatile__(                                   \
 791                         ".set\tmips3\n\t"                               \
 792                         "dmtc0\t%z0, " #register "\n\t"                 \
 793                         ".set\tmips0"                                   \
 794                         : : "Jr" (value));                              \
 795         else                                                            \
 796                 __asm__ __volatile__(                                   \
 797                         ".set\tmips64\n\t"                              \
 798                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 799                         ".set\tmips0"                                   \
 800                         : : "Jr" (value));                              \
 801 } while (0)
 802
 803 #define __read_ulong_c0_register(reg, sel)                              \
 804         ((sizeof(unsigned long) == 4) ?                                 \
 805         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 806         (unsigned long) __read_64bit_c0_register(reg, sel))
 807
 808 #define __write_ulong_c0_register(reg, sel, val)                        \
 809 do {                                                                    \
 810         if (sizeof(unsigned long) == 4)                                 \
 811                 __write_32bit_c0_register(reg, sel, val);               \
 812         else                                                            \
 813                 __write_64bit_c0_register(reg, sel, val);               \
 814 } while (0)
 815
 816 /*
 817  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 818  */
 819 #define __read_32bit_c0_ctrl_register(source)                           \
 820 ({ int __res;                                                           \
 821         __asm__ __volatile__(                                           \
 822                 "cfc0\t%0, " #source "\n\t"                             \
 823                 : "=r" (__res));                                        \
 824         __res;                                                          \
 825 })
 826
 827 #define __write_32bit_c0_ctrl_register(register, value)                 \
 828 do {                                                                    \
 829         __asm__ __volatile__(                                           \
 830                 "ctc0\t%z0, " #register "\n\t"                          \
 831                 : : "Jr" ((unsigned int)(value)));                      \
 832 } while (0)
 833
 834 /*
 835  * These versions are only needed for systems with more than 38 bits of
 836  * physical address space running the 32-bit kernel.  That's none atm :-)
 837  */
 838 #define __read_64bit_c0_split(source, sel)                              \
 839 ({                                                                      \
 840         unsigned long long __val;                                       \
 841         unsigned long __flags;                                          \
 842                                                                         \
 843         local_irq_save(__flags);                                        \
 844         if (sel == 0)                                                   \
 845                 __asm__ __volatile__(                                   \
 846                         ".set\tmips64\n\t"                              \
 847                         "dmfc0\t%M0, " #source "\n\t"                   \
 848                         "dsll\t%L0, %M0, 32\n\t"                        \
 849                         "dsra\t%M0, %M0, 32\n\t"                        \
 850                         "dsra\t%L0, %L0, 32\n\t"                        \
 851                         ".set\tmips0"                                   \
 852                         : "=r" (__val));                                \
 853         else                                                            \
 854                 __asm__ __volatile__(                                   \
 855                         ".set\tmips64\n\t"                              \
 856                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 857                         "dsll\t%L0, %M0, 32\n\t"                        \
 858                         "dsra\t%M0, %M0, 32\n\t"                        \
 859                         "dsra\t%L0, %L0, 32\n\t"                        \
 860                         ".set\tmips0"                                   \
 861                         : "=r" (__val));                                \
 862         local_irq_restore(__flags);                                     \
 863                                                                         \
 864         __val;                                                          \
 865 })
 866
 867 #define __write_64bit_c0_split(source, sel, val)                        \
 868 do {                                                                    \
 869         unsigned long __flags;                                          \
 870                                                                         \
 871         local_irq_save(__flags);                                        \
 872         if (sel == 0)                                                   \
 873                 __asm__ __volatile__(                                   \
 874                         ".set\tmips64\n\t"                              \
 875                         "dsll\t%L0, %L0, 32\n\t"                        \
 876                         "dsrl\t%L0, %L0, 32\n\t"                        \
 877                         "dsll\t%M0, %M0, 32\n\t"                        \
 878                         "or\t%L0, %L0, %M0\n\t"                         \
 879                         "dmtc0\t%L0, " #source "\n\t"                   \
 880                         ".set\tmips0"                                   \
 881                         : : "r" (val));                                 \
 882         else                                                            \
 883                 __asm__ __volatile__(                                   \
 884                         ".set\tmips64\n\t"                              \
 885                         "dsll\t%L0, %L0, 32\n\t"                        \
 886                         "dsrl\t%L0, %L0, 32\n\t"                        \
 887                         "dsll\t%M0, %M0, 32\n\t"                        \
 888                         "or\t%L0, %L0, %M0\n\t"                         \
 889                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
 890                         ".set\tmips0"                                   \
 891                         : : "r" (val));                                 \
 892         local_irq_restore(__flags);                                     \
 893 } while (0)
 894
 895 #define read_c0_index()         __read_32bit_c0_register($0, 0)
 896 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
 897
 898 #define read_c0_random()        __read_32bit_c0_register($1, 0)
 899 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
 900
 901 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
 902 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 903
 904 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
 905 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 906
 907 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 908 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
 909
 910 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 911 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 912
 913 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
 914 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
 915
 916 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 917 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 918
 919 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
 920 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
 921
 922 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
 923 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
 924
 925 #define read_c0_info()          __read_32bit_c0_register($7, 0)
 926
 927 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
 928 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
 929
 930 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
 931 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
 932
 933 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 934 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
 935
 936 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
 937 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
 938
 939 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
 940 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
 941
 942 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 943 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 944
 945 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 946 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 947
 948 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
 949 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
 950
 951 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
 952 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
 953
 954 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 955 #ifdef CONFIG_MIPS_MT_SMTC
 956 #define write_c0_status(val)                                            \
 957 do {                                                                    \
 958         __write_32bit_c0_register($12, 0, val);                         \
 959         __ehb();                                                        \
 960 } while (0)
 961 #else
 962 /*
 963  * Legacy non-SMTC code, which may be hazardous
 964  * but which might not support EHB
 965  */
 966 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
 967 #endif /* CONFIG_MIPS_MT_SMTC */
 968
 969 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
 970 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
 971
 972 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
 973 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
 974
 975 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
 976
 977 #define read_c0_config()        __read_32bit_c0_register($16, 0)
 978 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 979 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 980 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
 981 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
 982 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
 983 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
 984 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
 985 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
 986 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 987 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 988 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
 989 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
 990 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
 991 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
 992 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 993
 994 /*
 995  * The WatchLo register.  There may be up to 8 of them.
 996  */
 997 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
 998 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
 999 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1000 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1001 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1002 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1003 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1004 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1005 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1006 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1007 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1008 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1009 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1010 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1011 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1012 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1013
1014 /*
1015  * The WatchHi register.  There may be up to 8 of them.
1016  */
1017 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1018 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1019 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1020 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1021 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1022 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1023 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1024 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1025
1026 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1027 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1028 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1029 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1030 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1031 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1032 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1033 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1034
1035 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1036 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1037
1038 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1039 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1040
1041 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1042 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1043
1044 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1045 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1046
1047 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1048 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1049
1050 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1051 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1052
1053 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1054 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1055
1056 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1057 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1058
1059 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1060 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1061
1062 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1063 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1064
1065 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1066 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1067
1068 /*
1069  * MIPS32 / MIPS64 performance counters
1070  */
1071 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1072 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1073 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1074 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1075 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1076 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1077 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1078 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1079 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1080 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1081 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1082 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1083 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1084 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1085 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1086 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1087 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1088 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1089 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1090 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1091 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1092 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1093 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1094 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1095
1096 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1097 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1098
1099 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1100 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1101
1102 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1103
1104 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1105 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1106
1107 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1108 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1109
1110 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1111 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1112
1113 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1114 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1115
1116 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1117 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1118
1119 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1120 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1121
1122 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1123 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1124
1125 /* MIPSR2 */
1126 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1127 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1128
1129 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1130 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1131
1132 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1133 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1134
1135 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1136 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1137
1138 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1139 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1140
1141
1142 /* Cavium OCTEON (cnMIPS) */
1143 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1144 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1145
1146 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1147 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1148
1149 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1150 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1151 /*
1152  * The cacheerr registers are not standardized.  On OCTEON, they are
1153  * 64 bits wide.
1154  */
1155 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1156 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1157
1158 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1159 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1160
1161 /* BMIPS3300 */
1162 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1163 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1164
1165 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1166 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1167
1168 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1169 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1170
1171 /* BMIPS43xx */
1172 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1173 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1174
1175 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1176 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1177
1178 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1179 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1180
1181 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1182 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1183
1184 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1185 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1186
1187 /* BMIPS5000 */
1188 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1189 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1190
1191 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1192 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1193
1194 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1195 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1196
1197 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1198 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1199
1200 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1201 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1202
1203 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1204 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1205
1206 /*
1207  * Macros to access the floating point coprocessor control registers
1208  */
1209 #define read_32bit_cp1_register(source)                                 \
1210 ({                                                                      \
1211         int __res;                                                      \
1212                                                                         \
1213         __asm__ __volatile__(                                           \
1214         "       .set    push                                    \n"     \
1215         "       .set    reorder                                 \n"     \
1216         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1217         "       # like Octeon.                                  \n"     \
1218         "       .set    mips1                                   \n"     \
1219         "       cfc1    %0,"STR(source)"                        \n"     \
1220         "       .set    pop                                     \n"     \
1221         : "=r" (__res));                                                \
1222         __res;                                                          \
1223 })
1224
1225 #ifdef HAVE_AS_DSP
1226 #define rddsp(mask)                                                     \
1227 ({                                                                      \
1228         unsigned int __dspctl;                                          \
1229                                                                         \
1230         __asm__ __volatile__(                                           \
1231         "       .set push                                       \n"     \
1232         "       .set dsp                                        \n"     \
1233         "       rddsp   %0, %x1                                 \n"     \
1234         "       .set pop                                        \n"     \
1235         : "=r" (__dspctl)                                               \
1236         : "i" (mask));                                                  \
1237         __dspctl;                                                       \
1238 })
1239
1240 #define wrdsp(val, mask)                                                \
1241 do {                                                                    \
1242         __asm__ __volatile__(                                           \
1243         "       .set push                                       \n"     \
1244         "       .set dsp                                        \n"     \
1245         "       wrdsp   %0, %x1                                 \n"     \
1246         "       .set pop                                        \n"     \
1247         :                                                               \
1248         : "r" (val), "i" (mask));                                       \
1249 } while (0)
1250
1251 #define mflo0()                                                         \
1252 ({                                                                      \
1253         long mflo0;                                                     \
1254         __asm__(                                                        \
1255         "       .set push                                       \n"     \
1256         "       .set dsp                                        \n"     \
1257         "       mflo %0, $ac0                                   \n"     \
1258         "       .set pop                                        \n"     \
1259         : "=r" (mflo0));                                                \
1260         mflo0;                                                          \
1261 })
1262
1263 #define mflo1()                                                         \
1264 ({                                                                      \
1265         long mflo1;                                                     \
1266         __asm__(                                                        \
1267         "       .set push                                       \n"     \
1268         "       .set dsp                                        \n"     \
1269         "       mflo %0, $ac1                                   \n"     \
1270         "       .set pop                                        \n"     \
1271         : "=r" (mflo1));                                                \
1272         mflo1;                                                          \
1273 })
1274
1275 #define mflo2()                                                         \
1276 ({                                                                      \
1277         long mflo2;                                                     \
1278         __asm__(                                                        \
1279         "       .set push                                       \n"     \
1280         "       .set dsp                                        \n"     \
1281         "       mflo %0, $ac2                                   \n"     \
1282         "       .set pop                                        \n"     \
1283         : "=r" (mflo2));                                                \
1284         mflo2;                                                          \
1285 })
1286
1287 #define mflo3()                                                         \
1288 ({                                                                      \
1289         long mflo3;                                                     \
1290         __asm__(                                                        \
1291         "       .set push                                       \n"     \
1292         "       .set dsp                                        \n"     \
1293         "       mflo %0, $ac3                                   \n"     \
1294         "       .set pop                                        \n"     \
1295         : "=r" (mflo3));                                                \
1296         mflo3;                                                          \
1297 })
1298
1299 #define mfhi0()                                                         \
1300 ({                                                                      \
1301         long mfhi0;                                                     \
1302         __asm__(                                                        \
1303         "       .set push                                       \n"     \
1304         "       .set dsp                                        \n"     \
1305         "       mfhi %0, $ac0                                   \n"     \
1306         "       .set pop                                        \n"     \
1307         : "=r" (mfhi0));                                                \
1308         mfhi0;                                                          \
1309 })
1310
1311 #define mfhi1()                                                         \
1312 ({                                                                      \
1313         long mfhi1;                                                     \
1314         __asm__(                                                        \
1315         "       .set push                                       \n"     \
1316         "       .set dsp                                        \n"     \
1317         "       mfhi %0, $ac1                                   \n"     \
1318         "       .set pop                                        \n"     \
1319         : "=r" (mfhi1));                                                \
1320         mfhi1;                                                          \
1321 })
1322
1323 #define mfhi2()                                                         \
1324 ({                                                                      \
1325         long mfhi2;                                                     \
1326         __asm__(                                                        \
1327         "       .set push                                       \n"     \
1328         "       .set dsp                                        \n"     \
1329         "       mfhi %0, $ac2                                   \n"     \
1330         "       .set pop                                        \n"     \
1331         : "=r" (mfhi2));                                                \
1332         mfhi2;                                                          \
1333 })
1334
1335 #define mfhi3()                                                         \
1336 ({                                                                      \
1337         long mfhi3;                                                     \
1338         __asm__(                                                        \
1339         "       .set push                                       \n"     \
1340         "       .set dsp                                        \n"     \
1341         "       mfhi %0, $ac3                                   \n"     \
1342         "       .set pop                                        \n"     \
1343         : "=r" (mfhi3));                                                \
1344         mfhi3;                                                          \
1345 })
1346
1347
1348 #define mtlo0(x)                                                        \
1349 ({                                                                      \
1350         __asm__(                                                        \
1351         "       .set push                                       \n"     \
1352         "       .set dsp                                        \n"     \
1353         "       mtlo %0, $ac0                                   \n"     \
1354         "       .set pop                                        \n"     \
1355         :                                                               \
1356         : "r" (x));                                                     \
1357 })
1358
1359 #define mtlo1(x)                                                        \
1360 ({                                                                      \
1361         __asm__(                                                        \
1362         "       .set push                                       \n"     \
1363         "       .set dsp                                        \n"     \
1364         "       mtlo %0, $ac1                                   \n"     \
1365         "       .set pop                                        \n"     \
1366         :                                                               \
1367         : "r" (x));                                                     \
1368 })
1369
1370 #define mtlo2(x)                                                        \
1371 ({                                                                      \
1372         __asm__(                                                        \
1373         "       .set push                                       \n"     \
1374         "       .set dsp                                        \n"     \
1375         "       mtlo %0, $ac2                                   \n"     \
1376         "       .set pop                                        \n"     \
1377         :                                                               \
1378         : "r" (x));                                                     \
1379 })
1380
1381 #define mtlo3(x)                                                        \
1382 ({                                                                      \
1383         __asm__(                                                        \
1384         "       .set push                                       \n"     \
1385         "       .set dsp                                        \n"     \
1386         "       mtlo %0, $ac3                                   \n"     \
1387         "       .set pop                                        \n"     \
1388         :                                                               \
1389         : "r" (x));                                                     \
1390 })
1391
1392 #define mthi0(x)                                                        \
1393 ({                                                                      \
1394         __asm__(                                                        \
1395         "       .set push                                       \n"     \
1396         "       .set dsp                                        \n"     \
1397         "       mthi %0, $ac0                                   \n"     \
1398         "       .set pop                                        \n"     \
1399         :                                                               \
1400         : "r" (x));                                                     \
1401 })
1402
1403 #define mthi1(x)                                                        \
1404 ({                                                                      \
1405         __asm__(                                                        \
1406         "       .set push                                       \n"     \
1407         "       .set dsp                                        \n"     \
1408         "       mthi %0, $ac1                                   \n"     \
1409         "       .set pop                                        \n"     \
1410         :                                                               \
1411         : "r" (x));                                                     \
1412 })
1413
1414 #define mthi2(x)                                                        \
1415 ({                                                                      \
1416         __asm__(                                                        \
1417         "       .set push                                       \n"     \
1418         "       .set dsp                                        \n"     \
1419         "       mthi %0, $ac2                                   \n"     \
1420         "       .set pop                                        \n"     \
1421         :                                                               \
1422         : "r" (x));                                                     \
1423 })
1424
1425 #define mthi3(x)                                                        \
1426 ({                                                                      \
1427         __asm__(                                                        \
1428         "       .set push                                       \n"     \
1429         "       .set dsp                                        \n"     \
1430         "       mthi %0, $ac3                                   \n"     \
1431         "       .set pop                                        \n"     \
1432         :                                                               \
1433         : "r" (x));                                                     \
1434 })
1435
1436 #else
1437
1438 #ifdef CONFIG_CPU_MICROMIPS
1439 #define rddsp(mask)                                                     \
1440 ({                                                                      \
1441         unsigned int __res;                                             \
1442                                                                         \
1443         __asm__ __volatile__(                                           \
1444         "       .set    push                                    \n"     \
1445         "       .set    noat                                    \n"     \
1446         "       # rddsp $1, %x1                                 \n"     \
1447         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1448         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1449         "       move    %0, $1                                  \n"     \
1450         "       .set    pop                                     \n"     \
1451         : "=r" (__res)                                                  \
1452         : "i" (mask));                                                  \
1453         __res;                                                          \
1454 })
1455
1456 #define wrdsp(val, mask)                                                \
1457 do {                                                                    \
1458         __asm__ __volatile__(                                           \
1459         "       .set    push                                    \n"     \
1460         "       .set    noat                                    \n"     \
1461         "       move    $1, %0                                  \n"     \
1462         "       # wrdsp $1, %x1                                 \n"     \
1463         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1464         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1465         "       .set    pop                                     \n"     \
1466         :                                                               \
1467         : "r" (val), "i" (mask));                                       \
1468 } while (0)
1469
1470 #define _umips_dsp_mfxxx(ins)                                           \
1471 ({                                                                      \
1472         unsigned long __treg;                                           \
1473                                                                         \
1474         __asm__ __volatile__(                                           \
1475         "       .set    push                                    \n"     \
1476         "       .set    noat                                    \n"     \
1477         "       .hword  0x0001                                  \n"     \
1478         "       .hword  %x1                                     \n"     \
1479         "       move    %0, $1                                  \n"     \
1480         "       .set    pop                                     \n"     \
1481         : "=r" (__treg)                                                 \
1482         : "i" (ins));                                                   \
1483         __treg;                                                         \
1484 })
1485
1486 #define _umips_dsp_mtxxx(val, ins)                                      \
1487 do {                                                                    \
1488         __asm__ __volatile__(                                           \
1489         "       .set    push                                    \n"     \
1490         "       .set    noat                                    \n"     \
1491         "       move    $1, %0                                  \n"     \
1492         "       .hword  0x0001                                  \n"     \
1493         "       .hword  %x1                                     \n"     \
1494         "       .set    pop                                     \n"     \
1495         :                                                               \
1496         : "r" (val), "i" (ins));                                        \
1497 } while (0)
1498
1499 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1500 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1501
1502 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1503 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1504
1505 #define mflo0() _umips_dsp_mflo(0)
1506 #define mflo1() _umips_dsp_mflo(1)
1507 #define mflo2() _umips_dsp_mflo(2)
1508 #define mflo3() _umips_dsp_mflo(3)
1509
1510 #define mfhi0() _umips_dsp_mfhi(0)
1511 #define mfhi1() _umips_dsp_mfhi(1)
1512 #define mfhi2() _umips_dsp_mfhi(2)
1513 #define mfhi3() _umips_dsp_mfhi(3)
1514
1515 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1516 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1517 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1518 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1519
1520 #define mthi0(x) _umips_dsp_mthi(x, 0)
1521 #define mthi1(x) _umips_dsp_mthi(x, 1)
1522 #define mthi2(x) _umips_dsp_mthi(x, 2)
1523 #define mthi3(x) _umips_dsp_mthi(x, 3)
1524
1525 #else  /* !CONFIG_CPU_MICROMIPS */
1526 #define rddsp(mask)                                                     \
1527 ({                                                                      \
1528         unsigned int __res;                                             \
1529                                                                         \
1530         __asm__ __volatile__(                                           \
1531         "       .set    push                            \n"             \
1532         "       .set    noat                            \n"             \
1533         "       # rddsp $1, %x1                         \n"             \
1534         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1535         "       move    %0, $1                          \n"             \
1536         "       .set    pop                             \n"             \
1537         : "=r" (__res)                                                  \
1538         : "i" (mask));                                                  \
1539         __res;                                                          \
1540 })
1541
1542 #define wrdsp(val, mask)                                                \
1543 do {                                                                    \
1544         __asm__ __volatile__(                                           \
1545         "       .set    push                                    \n"     \
1546         "       .set    noat                                    \n"     \
1547         "       move    $1, %0                                  \n"     \
1548         "       # wrdsp $1, %x1                                 \n"     \
1549         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1550         "       .set    pop                                     \n"     \
1551         :                                                               \
1552         : "r" (val), "i" (mask));                                       \
1553 } while (0)
1554
1555 #define _dsp_mfxxx(ins)                                                 \
1556 ({                                                                      \
1557         unsigned long __treg;                                           \
1558                                                                         \
1559         __asm__ __volatile__(                                           \
1560         "       .set    push                                    \n"     \
1561         "       .set    noat                                    \n"     \
1562         "       .word   (0x00000810 | %1)                       \n"     \
1563         "       move    %0, $1                                  \n"     \
1564         "       .set    pop                                     \n"     \
1565         : "=r" (__treg)                                                 \
1566         : "i" (ins));                                                   \
1567         __treg;                                                         \
1568 })
1569
1570 #define _dsp_mtxxx(val, ins)                                            \
1571 do {                                                                    \
1572         __asm__ __volatile__(                                           \
1573         "       .set    push                                    \n"     \
1574         "       .set    noat                                    \n"     \
1575         "       move    $1, %0                                  \n"     \
1576         "       .word   (0x00200011 | %1)                       \n"     \
1577         "       .set    pop                                     \n"     \
1578         :                                                               \
1579         : "r" (val), "i" (ins));                                        \
1580 } while (0)
1581
1582 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1583 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1584
1585 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1586 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1587
1588 #define mflo0() _dsp_mflo(0)
1589 #define mflo1() _dsp_mflo(1)
1590 #define mflo2() _dsp_mflo(2)
1591 #define mflo3() _dsp_mflo(3)
1592
1593 #define mfhi0() _dsp_mfhi(0)
1594 #define mfhi1() _dsp_mfhi(1)
1595 #define mfhi2() _dsp_mfhi(2)
1596 #define mfhi3() _dsp_mfhi(3)
1597
1598 #define mtlo0(x) _dsp_mtlo(x, 0)
1599 #define mtlo1(x) _dsp_mtlo(x, 1)
1600 #define mtlo2(x) _dsp_mtlo(x, 2)
1601 #define mtlo3(x) _dsp_mtlo(x, 3)
1602
1603 #define mthi0(x) _dsp_mthi(x, 0)
1604 #define mthi1(x) _dsp_mthi(x, 1)
1605 #define mthi2(x) _dsp_mthi(x, 2)
1606 #define mthi3(x) _dsp_mthi(x, 3)
1607
1608 #endif /* CONFIG_CPU_MICROMIPS */
1609 #endif
1610
1611 /*
1612  * TLB operations.
1613  *
1614  * It is responsibility of the caller to take care of any TLB hazards.
1615  */
1616 static inline void tlb_probe(void)
1617 {
1618         __asm__ __volatile__(
1619                 ".set noreorder\n\t"
1620                 "tlbp\n\t"
1621                 ".set reorder");
1622 }
1623
1624 static inline void tlb_read(void)
1625 {
1626 #if MIPS34K_MISSED_ITLB_WAR
1627         int res = 0;
1628
1629         __asm__ __volatile__(
1630         "       .set    push                                    \n"
1631         "       .set    noreorder                               \n"
1632         "       .set    noat                                    \n"
1633         "       .set    mips32r2                                \n"
1634         "       .word   0x41610001              # dvpe $1       \n"
1635         "       move    %0, $1                                  \n"
1636         "       ehb                                             \n"
1637         "       .set    pop                                     \n"
1638         : "=r" (res));
1639
1640         instruction_hazard();
1641 #endif
1642
1643         __asm__ __volatile__(
1644                 ".set noreorder\n\t"
1645                 "tlbr\n\t"
1646                 ".set reorder");
1647
1648 #if MIPS34K_MISSED_ITLB_WAR
1649         if ((res & _ULCAST_(1)))
1650                 __asm__ __volatile__(
1651                 "       .set    push                            \n"
1652                 "       .set    noreorder                       \n"
1653                 "       .set    noat                            \n"
1654                 "       .set    mips32r2                        \n"
1655                 "       .word   0x41600021      # evpe          \n"
1656                 "       ehb                                     \n"
1657                 "       .set    pop                             \n");
1658 #endif
1659 }
1660
1661 static inline void tlb_write_indexed(void)
1662 {
1663         __asm__ __volatile__(
1664                 ".set noreorder\n\t"
1665                 "tlbwi\n\t"
1666                 ".set reorder");
1667 }
1668
1669 static inline void tlb_write_random(void)
1670 {
1671         __asm__ __volatile__(
1672                 ".set noreorder\n\t"
1673                 "tlbwr\n\t"
1674                 ".set reorder");
1675 }
1676
1677 /*
1678  * Manipulate bits in a c0 register.
1679  */
1680 #ifndef CONFIG_MIPS_MT_SMTC
1681 /*
1682  * SMTC Linux requires shutting-down microthread scheduling
1683  * during CP0 register read-modify-write sequences.
1684  */
1685 #define __BUILD_SET_C0(name)                                    \
1686 static inline unsigned int                                      \
1687 set_c0_##name(unsigned int set)                                 \
1688 {                                                               \
1689         unsigned int res, new;                                  \
1690                                                                 \
1691         res = read_c0_##name();                                 \
1692         new = res | set;                                        \
1693         write_c0_##name(new);                                   \
1694                                                                 \
1695         return res;                                             \
1696 }                                                               \
1697                                                                 \
1698 static inline unsigned int                                      \
1699 clear_c0_##name(unsigned int clear)                             \
1700 {                                                               \
1701         unsigned int res, new;                                  \
1702                                                                 \
1703         res = read_c0_##name();                                 \
1704         new = res & ~clear;                                     \
1705         write_c0_##name(new);                                   \
1706                                                                 \
1707         return res;                                             \
1708 }                                                               \
1709                                                                 \
1710 static inline unsigned int                                      \
1711 change_c0_##name(unsigned int change, unsigned int val)         \
1712 {                                                               \
1713         unsigned int res, new;                                  \
1714                                                                 \
1715         res = read_c0_##name();                                 \
1716         new = res & ~change;                                    \
1717         new |= (val & change);                                  \
1718         write_c0_##name(new);                                   \
1719                                                                 \
1720         return res;                                             \
1721 }
1722
1723 #else /* SMTC versions that manage MT scheduling */
1724
1725 #include <linux/irqflags.h>
1726
1727 /*
1728  * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1729  * header file recursion.
1730  */
1731 static inline unsigned int __dmt(void)
1732 {
1733         int res;
1734
1735         __asm__ __volatile__(
1736         "       .set    push                                            \n"
1737         "       .set    mips32r2                                        \n"
1738         "       .set    noat                                            \n"
1739         "       .word   0x41610BC1                      # dmt $1        \n"
1740         "       ehb                                                     \n"
1741         "       move    %0, $1                                          \n"
1742         "       .set    pop                                             \n"
1743         : "=r" (res));
1744
1745         instruction_hazard();
1746
1747         return res;
1748 }
1749
1750 #define __VPECONTROL_TE_SHIFT   15
1751 #define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
1752
1753 #define __EMT_ENABLE            __VPECONTROL_TE
1754
1755 static inline void __emt(unsigned int previous)
1756 {
1757         if ((previous & __EMT_ENABLE))
1758                 __asm__ __volatile__(
1759                 "       .set    mips32r2                                \n"
1760                 "       .word   0x41600be1              # emt           \n"
1761                 "       ehb                                             \n"
1762                 "       .set    mips0                                   \n");
1763 }
1764
1765 static inline void __ehb(void)
1766 {
1767         __asm__ __volatile__(
1768         "       .set    mips32r2                                        \n"
1769         "       ehb                                                     \n"             "       .set    mips0                                           \n");
1770 }
1771
1772 /*
1773  * Note that local_irq_save/restore affect TC-specific IXMT state,
1774  * not Status.IE as in non-SMTC kernel.
1775  */
1776
1777 #define __BUILD_SET_C0(name)                                    \
1778 static inline unsigned int                                      \
1779 set_c0_##name(unsigned int set)                                 \
1780 {                                                               \
1781         unsigned int res;                                       \
1782         unsigned int new;                                       \
1783         unsigned int omt;                                       \
1784         unsigned long flags;                                    \
1785                                                                 \
1786         local_irq_save(flags);                                  \
1787         omt = __dmt();                                          \
1788         res = read_c0_##name();                                 \
1789         new = res | set;                                        \
1790         write_c0_##name(new);                                   \
1791         __emt(omt);                                             \
1792         local_irq_restore(flags);                               \
1793                                                                 \
1794         return res;                                             \
1795 }                                                               \
1796                                                                 \
1797 static inline unsigned int                                      \
1798 clear_c0_##name(unsigned int clear)                             \
1799 {                                                               \
1800         unsigned int res;                                       \
1801         unsigned int new;                                       \
1802         unsigned int omt;                                       \
1803         unsigned long flags;                                    \
1804                                                                 \
1805         local_irq_save(flags);                                  \
1806         omt = __dmt();                                          \
1807         res = read_c0_##name();                                 \
1808         new = res & ~clear;                                     \
1809         write_c0_##name(new);                                   \
1810         __emt(omt);                                             \
1811         local_irq_restore(flags);                               \
1812                                                                 \
1813         return res;                                             \
1814 }                                                               \
1815                                                                 \
1816 static inline unsigned int                                      \
1817 change_c0_##name(unsigned int change, unsigned int newbits)     \
1818 {                                                               \
1819         unsigned int res;                                       \
1820         unsigned int new;                                       \
1821         unsigned int omt;                                       \
1822         unsigned long flags;                                    \
1823                                                                 \
1824         local_irq_save(flags);                                  \
1825                                                                 \
1826         omt = __dmt();                                          \
1827         res = read_c0_##name();                                 \
1828         new = res & ~change;                                    \
1829         new |= (newbits & change);                              \
1830         write_c0_##name(new);                                   \
1831         __emt(omt);                                             \
1832         local_irq_restore(flags);                               \
1833                                                                 \
1834         return res;                                             \
1835 }
1836 #endif
1837
1838 __BUILD_SET_C0(status)
1839 __BUILD_SET_C0(cause)
1840 __BUILD_SET_C0(config)
1841 __BUILD_SET_C0(intcontrol)
1842 __BUILD_SET_C0(intctl)
1843 __BUILD_SET_C0(srsmap)
1844 __BUILD_SET_C0(brcm_config_0)
1845 __BUILD_SET_C0(brcm_bus_pll)
1846 __BUILD_SET_C0(brcm_reset)
1847 __BUILD_SET_C0(brcm_cmt_intr)
1848 __BUILD_SET_C0(brcm_cmt_ctrl)
1849 __BUILD_SET_C0(brcm_config)
1850 __BUILD_SET_C0(brcm_mode)
1851
1852 #endif /* !__ASSEMBLY__ */
1853
1854 #endif /* _ASM_MIPSREGS_H */