arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Defines for the MSP interrupt controller.
   4  *
   5  * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
   6  * Author: Carsten Langgaard, carstenl@mips.com
   7  *
   8  * ########################################################################
   9  *
  10  * ########################################################################
  11  */
  12
  13 #ifndef _MSP_CIC_INT_H
  14 #define _MSP_CIC_INT_H
  15
  16 /*
  17  * The PMC-Sierra CIC interrupts are all centrally managed by the
  18  * CIC sub-system.
  19  * We attempt to keep the interrupt numbers as consistent as possible
  20  * across all of the MSP devices, but some differences will creep in ...
  21  * The interrupts which are directly forwarded to the MIPS core interrupts
  22  * are assigned interrupts in the range 0-7, interrupts cascaded through
  23  * the CIC are assigned interrupts 8-39.  The cascade occurs on C_IRQ4
  24  * (MSP_INT_CIC).  Currently we don't really distinguish between VPE1
  25  * and VPE0 (or thread contexts for that matter).  Will have to fix.
  26  * The PER interrupts are assigned interrupts in the range 40-71.
  27 */
  28
  29
  30 /*
  31  * IRQs directly forwarded to the CPU
  32  */
  33 #define MSP_MIPS_INTBASE        0
  34 #define MSP_INT_SW0             0       /* IRQ for swint0,       C_SW0  */
  35 #define MSP_INT_SW1             1       /* IRQ for swint1,       C_SW1  */
  36 #define MSP_INT_MAC0            2       /* IRQ for MAC 0,        C_IRQ0 */
  37 #define MSP_INT_MAC1            3       /* IRQ for MAC 1,        C_IRQ1 */
  38 #define MSP_INT_USB             4       /* IRQ for USB,          C_IRQ2 */
  39 #define MSP_INT_SAR             5       /* IRQ for ADSL2+ SAR,   C_IRQ3 */
  40 #define MSP_INT_CIC             6       /* IRQ for CIC block,    C_IRQ4 */
  41 #define MSP_INT_SEC             7       /* IRQ for Sec engine,   C_IRQ5 */
  42
  43 /*
  44  * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
  45  * These defines should be tied to the register definitions for the CIC
  46  * interrupt routine.  For now, just use hard-coded values.
  47  */
  48 #define MSP_CIC_INTBASE         (MSP_MIPS_INTBASE + 8)
  49 #define MSP_INT_EXT0            (MSP_CIC_INTBASE + 0)
  50                                         /* External interrupt 0         */
  51 #define MSP_INT_EXT1            (MSP_CIC_INTBASE + 1)
  52                                         /* External interrupt 1         */
  53 #define MSP_INT_EXT2            (MSP_CIC_INTBASE + 2)
  54                                         /* External interrupt 2         */
  55 #define MSP_INT_EXT3            (MSP_CIC_INTBASE + 3)
  56                                         /* External interrupt 3         */
  57 #define MSP_INT_CPUIF           (MSP_CIC_INTBASE + 4)
  58                                         /* CPU interface interrupt      */
  59 #define MSP_INT_EXT4            (MSP_CIC_INTBASE + 5)
  60                                         /* External interrupt 4         */
  61 #define MSP_INT_CIC_USB         (MSP_CIC_INTBASE + 6)
  62                                         /* Cascaded IRQ for USB         */
  63 #define MSP_INT_MBOX            (MSP_CIC_INTBASE + 7)
  64                                         /* Sec engine mailbox IRQ       */
  65 #define MSP_INT_EXT5            (MSP_CIC_INTBASE + 8)
  66                                         /* External interrupt 5         */
  67 #define MSP_INT_TDM             (MSP_CIC_INTBASE + 9)
  68                                         /* TDM interrupt                */
  69 #define MSP_INT_CIC_MAC0        (MSP_CIC_INTBASE + 10)
  70                                         /* Cascaded IRQ for MAC 0       */
  71 #define MSP_INT_CIC_MAC1        (MSP_CIC_INTBASE + 11)
  72                                         /* Cascaded IRQ for MAC 1       */
  73 #define MSP_INT_CIC_SEC         (MSP_CIC_INTBASE + 12)
  74                                         /* Cascaded IRQ for sec engine  */
  75 #define MSP_INT_PER             (MSP_CIC_INTBASE + 13)
  76                                         /* Peripheral interrupt         */
  77 #define MSP_INT_TIMER0          (MSP_CIC_INTBASE + 14)
  78                                         /* SLP timer 0                  */
  79 #define MSP_INT_TIMER1          (MSP_CIC_INTBASE + 15)
  80                                         /* SLP timer 1                  */
  81 #define MSP_INT_TIMER2          (MSP_CIC_INTBASE + 16)
  82                                         /* SLP timer 2                  */
  83 #define MSP_INT_VPE0_TIMER      (MSP_CIC_INTBASE + 17)
  84                                         /* VPE0 MIPS timer              */
  85 #define MSP_INT_BLKCP           (MSP_CIC_INTBASE + 18)
  86                                         /* Block Copy                   */
  87 #define MSP_INT_UART0           (MSP_CIC_INTBASE + 19)
  88                                         /* UART 0                       */
  89 #define MSP_INT_PCI             (MSP_CIC_INTBASE + 20)
  90                                         /* PCI subsystem                */
  91 #define MSP_INT_EXT6            (MSP_CIC_INTBASE + 21)
  92                                         /* External interrupt 5         */
  93 #define MSP_INT_PCI_MSI         (MSP_CIC_INTBASE + 22)
  94                                         /* PCI Message Signal           */
  95 #define MSP_INT_CIC_SAR         (MSP_CIC_INTBASE + 23)
  96                                         /* Cascaded ADSL2+ SAR IRQ      */
  97 #define MSP_INT_DSL             (MSP_CIC_INTBASE + 24)
  98                                         /* ADSL2+ IRQ                   */
  99 #define MSP_INT_CIC_ERR         (MSP_CIC_INTBASE + 25)
 100                                         /* SLP error condition          */
 101 #define MSP_INT_VPE1_TIMER      (MSP_CIC_INTBASE + 26)
 102                                         /* VPE1 MIPS timer              */
 103 #define MSP_INT_VPE0_PC         (MSP_CIC_INTBASE + 27)
 104                                         /* VPE0 Performance counter     */
 105 #define MSP_INT_VPE1_PC         (MSP_CIC_INTBASE + 28)
 106                                         /* VPE1 Performance counter     */
 107 #define MSP_INT_EXT7            (MSP_CIC_INTBASE + 29)
 108                                         /* External interrupt 5         */
 109 #define MSP_INT_VPE0_SW         (MSP_CIC_INTBASE + 30)
 110                                         /* VPE0 Software interrupt      */
 111 #define MSP_INT_VPE1_SW         (MSP_CIC_INTBASE + 31)
 112                                         /* VPE0 Software interrupt      */
 113
 114 /*
 115  * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
 116  */
 117 #define MSP_PER_INTBASE         (MSP_CIC_INTBASE + 32)
 118 /* Reserved                                        0-1                  */
 119 #define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
 120                                         /* UART 1                       */
 121 /* Reserved                                        3-5                  */
 122 #define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
 123                                         /* 2-wire                       */
 124 #define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
 125                                         /* Peripheral timer block out 0 */
 126 #define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
 127                                         /* Peripheral timer block out 1 */
 128 /* Reserved                                        9                    */
 129 #define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
 130                                         /* SPI RX complete              */
 131 #define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
 132                                         /* SPI TX complete              */
 133 #define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
 134                                         /* GPIO                         */
 135 #define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
 136                                         /* Peripheral error             */
 137 /* Reserved                                        14-31                */
 138
 139 #endif /* !_MSP_CIC_INT_H */