1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2009 Lemote, Inc.
4 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
7 #ifndef __ASM_MACH_LOONGSON2EF_LOONGSON_H
8 #define __ASM_MACH_LOONGSON2EF_LOONGSON_H
11 #include <linux/init.h>
12 #include <linux/irq.h>
14 /* loongson internal northbridge initialization */
15 extern void bonito_irq_init(void);
17 /* machine-specific reboot/halt operation */
18 extern void mach_prepare_reboot(void);
19 extern void mach_prepare_shutdown(void);
21 /* environment arguments from bootloader */
22 extern u32 cpu_clock_freq;
23 extern u32 memsize, highmemsize;
24 extern const struct plat_smp_ops loongson3_smp_ops;
26 /* loongson-specific command line, env and memory initialization */
27 extern void __init prom_init_memory(void);
28 extern void __init prom_init_machtype(void);
29 extern void __init prom_init_env(void);
30 #ifdef CONFIG_LOONGSON_UART_BASE
31 extern unsigned long _loongson_uart_base, loongson_uart_base;
32 extern void prom_init_loongson_uart_base(void);
35 static inline void prom_init_uart_base(void)
37 #ifdef CONFIG_LOONGSON_UART_BASE
38 prom_init_loongson_uart_base();
42 /* irq operation functions */
43 extern void bonito_irqdispatch(void);
44 extern void __init bonito_irq_init(void);
45 extern void __init mach_init_irq(void);
46 extern void mach_irq_dispatch(unsigned int pending);
47 extern int mach_i8259_irq(void);
49 /* We need this in some places... */
52 for (x = 0; x < 100000; x++) \
53 __asm__ __volatile__(""); \
56 #define LOONGSON_REG(x) \
57 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
59 #define LOONGSON_IRQ_BASE 32
60 #define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
62 #include <linux/interrupt.h>
63 static inline void do_perfcnt_IRQ(void)
65 #if IS_ENABLED(CONFIG_OPROFILE)
66 do_IRQ(LOONGSON2_PERFCNT_IRQ);
70 #define LOONGSON_FLASH_BASE 0x1c000000
71 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
72 #define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
74 #define LOONGSON_LIO0_BASE 0x1e000000
75 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
76 #define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
78 #define LOONGSON_BOOT_BASE 0x1fc00000
79 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
80 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
81 #define LOONGSON_REG_BASE 0x1fe00000
82 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
83 #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
85 #define LOONGSON_LIO1_BASE 0x1ff00000
86 #define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
87 #define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
89 #define LOONGSON_PCILO0_BASE 0x10000000
90 #define LOONGSON_PCILO1_BASE 0x14000000
91 #define LOONGSON_PCILO2_BASE 0x18000000
92 #define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
93 #define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
94 #define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
96 #define LOONGSON_PCICFG_BASE 0x1fe80000
97 #define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
98 #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
99 #define LOONGSON_PCIIO_BASE 0x1fd00000
101 #define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
102 #define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
104 /* Loongson Register Bases */
106 #define LOONGSON_PCICONFIGBASE 0x00
107 #define LOONGSON_REGBASE 0x100
109 /* PCI Configuration Registers */
111 #define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
112 #define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
113 #define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
114 #define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
115 #define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
116 #define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
117 #define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
118 #define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
119 #define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
120 #define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
121 #define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
122 #define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
124 #define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
126 #define LOONGSON_PCICMD_PERR_CLR 0x80000000
127 #define LOONGSON_PCICMD_SERR_CLR 0x40000000
128 #define LOONGSON_PCICMD_MABORT_CLR 0x20000000
129 #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
130 #define LOONGSON_PCICMD_TABORT_CLR 0x08000000
131 #define LOONGSON_PCICMD_MPERR_CLR 0x01000000
132 #define LOONGSON_PCICMD_PERRRESPEN 0x00000040
133 #define LOONGSON_PCICMD_ASTEPEN 0x00000080
134 #define LOONGSON_PCICMD_SERREN 0x00000100
135 #define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
136 #define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
138 /* Loongson h/w Configuration */
140 #define LOONGSON_GENCFG_OFFSET 0x4
141 #define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
143 #define LOONGSON_GENCFG_DEBUGMODE 0x00000001
144 #define LOONGSON_GENCFG_SNOOPEN 0x00000002
145 #define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
147 #define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
148 #define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
149 #define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
150 #define LOONGSON_GENCFG_BYTESWAP 0x00000040
152 #define LOONGSON_GENCFG_UNCACHED 0x00000080
153 #define LOONGSON_GENCFG_PREFETCHEN 0x00000100
154 #define LOONGSON_GENCFG_WBEHINDEN 0x00000200
155 #define LOONGSON_GENCFG_CACHEALG 0x00000c00
156 #define LOONGSON_GENCFG_CACHEALG_SHIFT 10
157 #define LOONGSON_GENCFG_PCIQUEUE 0x00001000
158 #define LOONGSON_GENCFG_CACHESTOP 0x00002000
159 #define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
160 #define LOONGSON_GENCFG_BUSERREN 0x00008000
161 #define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
162 #define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
164 /* PCI address map control */
166 #define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
167 #define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
168 #define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
170 /* GPIO Regs - r/w */
172 #define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
173 #define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
175 /* ICU Configuration Regs - r/w */
177 #define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
178 #define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
179 #define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
181 /* ICU Enable Regs - IntEn & IntISR are r/o. */
183 #define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
184 #define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
185 #define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
186 #define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
189 #define LOONGSON_ICU_MBOXES 0x0000000f
190 #define LOONGSON_ICU_MBOXES_SHIFT 0
191 #define LOONGSON_ICU_DMARDY 0x00000010
192 #define LOONGSON_ICU_DMAEMPTY 0x00000020
193 #define LOONGSON_ICU_COPYRDY 0x00000040
194 #define LOONGSON_ICU_COPYEMPTY 0x00000080
195 #define LOONGSON_ICU_COPYERR 0x00000100
196 #define LOONGSON_ICU_PCIIRQ 0x00000200
197 #define LOONGSON_ICU_MASTERERR 0x00000400
198 #define LOONGSON_ICU_SYSTEMERR 0x00000800
199 #define LOONGSON_ICU_DRAMPERR 0x00001000
200 #define LOONGSON_ICU_RETRYERR 0x00002000
201 #define LOONGSON_ICU_GPIOS 0x01ff0000
202 #define LOONGSON_ICU_GPIOS_SHIFT 16
203 #define LOONGSON_ICU_GPINS 0x7e000000
204 #define LOONGSON_ICU_GPINS_SHIFT 25
205 #define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
206 #define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
207 #define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
209 /* PCI prefetch window base & mask */
211 #define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
212 #define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
213 #define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
214 #define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
218 #define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
219 #define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
220 #define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
221 #define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
222 #define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
223 #define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
225 /* PXArb Config & Status */
227 #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
228 #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
230 /* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
231 #define LOONGSON_CHIPCFG (void __iomem *)TO_UNCAC(0x1fc00180)
235 #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
236 #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
237 #define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
238 #define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
239 #define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
240 #define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
241 #define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
242 #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
243 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
245 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
246 #include <linux/cpufreq.h>
247 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
251 * address windows configuration module
253 * loongson2e do not have this module
255 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
257 /* address window config module base address */
258 #define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
259 #define LOONGSON_ADDRWINCFG_SIZE 0x180
261 extern unsigned long _loongson_addrwincfg_base;
262 #define LOONGSON_ADDRWINCFG(offset) \
263 (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
265 #define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
266 #define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
267 #define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
268 #define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
270 #define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
271 #define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
272 #define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
273 #define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
275 #define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
276 #define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
277 #define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
278 #define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
280 #define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
281 #define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
282 #define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
283 #define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
285 #define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
286 #define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
287 #define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
288 #define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
290 #define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
291 #define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
292 #define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
293 #define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
295 #define ADDRWIN_WIN0 0
296 #define ADDRWIN_WIN1 1
297 #define ADDRWIN_WIN2 2
298 #define ADDRWIN_WIN3 3
300 #define ADDRWIN_MAP_DST_DDR 0
301 #define ADDRWIN_MAP_DST_PCI 1
302 #define ADDRWIN_MAP_DST_LIO 1
309 * dst: map destination
312 #define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
313 s##_WIN##w##_BASE = (src); \
314 s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
315 s##_WIN##w##_MASK = ~(size-1); \
318 #define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
319 LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
320 #define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
321 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
322 #define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
323 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
325 #endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
327 #endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */