MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
[linux-2.6-microblaze.git] / arch / mips / include / asm / mach-ip30 / war.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
4  */
5 #ifndef __ASM_MIPS_MACH_IP30_WAR_H
6 #define __ASM_MIPS_MACH_IP30_WAR_H
7
8 #define R4600_V2_HIT_CACHEOP_WAR        0
9 #define BCM1250_M3_WAR                  0
10 #define SIBYTE_1956_WAR                 0
11 #define MIPS4K_ICACHE_REFILL_WAR        0
12 #define MIPS_CACHE_SYNC_WAR             0
13 #define TX49XX_ICACHE_INDEX_INV_WAR     0
14 #define ICACHE_REFILLS_WORKAROUND_WAR   0
15 #ifdef CONFIG_CPU_R10000
16 #define R10000_LLSC_WAR                 1
17 #else
18 #define R10000_LLSC_WAR                 0
19 #endif
20 #define MIPS34K_MISSED_ITLB_WAR         0
21
22 #endif /* __ASM_MIPS_MACH_IP30_WAR_H */