2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2005-2008 Cavium Networks, Inc
8 #ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
9 #define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
12 #define CP0_CYCLE_COUNTER $9, 6
13 #define CP0_CVMCTL_REG $9, 7
14 #define CP0_CVMMEMCTL_REG $11,7
15 #define CP0_PRID_REG $15, 0
16 #define CP0_PRID_OCTEON_PASS1 0x000d0000
17 #define CP0_PRID_OCTEON_CN30XX 0x000d0200
19 .macro kernel_entry_setup
20 # Registers set by bootloader:
21 # (only 32 bits set by bootloader, all addresses are physical
22 # addresses, and need to have the appropriate memory region set
25 # a1 = argv (kseg0 compat addr)
26 # a2 = 1 if init core, zero otherwise
27 # a3 = address of boot descriptor block
30 # Read the cavium mem control register
31 dmfc0 v0, CP0_CVMMEMCTL_REG
32 # Clear the lower 6 bits, the CVMSEG size
34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
37 # Disable unaligned load/store support but leave HW fixup enabled
38 # Needed for octeon specific memcpy
41 # Read the processor ID register
43 # Disable instruction prefetching (Octeon Pass1 errata)
45 # Skip reenable of prefetching for Octeon Pass1
46 beq v1, CP0_PRID_OCTEON_PASS1, skip
48 # Reenable instruction prefetching, not on Pass1
50 # Strip off pass number off of processor id
53 # CN30XX needs some extra stuff turned off for better performance
54 bne v1, CP0_PRID_OCTEON_CN30XX, skip
56 # CN30XX Use random Icache replacement
58 # CN30XX Disable instruction prefetching
61 # First clear off CvmCtl[IPPCI] bit and move the performance
62 # counters interrupt to IRQ 6
69 xor t1, t1, 0x9000 # 63-P1
72 xor t1, t1, 0x9008 # 63-P2
75 xor t1, t1, 0x9100 # 68-P1
78 xor t1, t1, 0x9200 # 66-PX
79 bnez t1, 5f # Skip WAR for others.
81 slti t1, t1, 2 # 66-P1.2 and later good.
84 4: # core-16057 work around
85 or v0, v0, 0x2000 # Set IPREF bit.
87 5: # No core-16057 work around
88 # Write the cavium control register
89 dmtc0 v0, CP0_CVMCTL_REG
91 # Flush dcache after config change
95 # Jump the master to kernel_entry
96 bne a2, zero, octeon_main_processor
102 # All cores other than the master need to wait here for SMP bootstrap
106 # This is the variable where the next core to boot os stored
107 PTR_LA t0, octeon_processor_boot
108 octeon_spin_wait_boot:
109 # Get the core id of the next to be booted
111 # Keep looping if it isn't me
112 bne t1, v0, octeon_spin_wait_boot
114 # Get my GP from the global variable
115 PTR_LA t0, octeon_processor_gp
117 # Get my SP from the global variable
118 PTR_LA t0, octeon_processor_sp
120 # Set the SP global variable to zero so the master knows we've started
128 # Jump to the normal Linux SMP entry point
131 #else /* CONFIG_SMP */
134 # Someone tried to boot SMP with a non SMP kernel. All extra cores
139 b octeon_wait_forever
142 #endif /* CONFIG_SMP */
143 octeon_main_processor:
148 * Do SMP slave processor setup necessary before we can savely execute C code.
150 .macro smp_slave_setup
153 #endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */