2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
13 #include <linux/cpumask.h>
14 #include <linux/mutex.h>
15 #include <linux/hrtimer.h>
16 #include <linux/interrupt.h>
17 #include <linux/types.h>
18 #include <linux/kvm.h>
19 #include <linux/kvm_types.h>
20 #include <linux/threads.h>
21 #include <linux/spinlock.h>
24 #include <asm/mipsregs.h>
26 #include <kvm/iodev.h>
28 /* MIPS KVM register ids */
29 #define MIPS_CP0_32(_R, _S) \
30 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
32 #define MIPS_CP0_64(_R, _S) \
33 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
35 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
36 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
37 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
38 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
39 #define KVM_REG_MIPS_CP0_CONTEXTCONFIG MIPS_CP0_32(4, 1)
40 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
41 #define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3)
42 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
43 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
44 #define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2)
45 #define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3)
46 #define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4)
47 #define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5)
48 #define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6)
49 #define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7)
50 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
51 #define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6)
52 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
53 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
54 #define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1)
55 #define KVM_REG_MIPS_CP0_BADINSTRP MIPS_CP0_32(8, 2)
56 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
57 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
58 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
59 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
60 #define KVM_REG_MIPS_CP0_INTCTL MIPS_CP0_32(12, 1)
61 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
62 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
63 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
64 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
65 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
66 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
67 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
68 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
69 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
70 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
71 #define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6)
72 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
73 #define KVM_REG_MIPS_CP0_MAARI MIPS_CP0_64(17, 2)
74 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
75 #define KVM_REG_MIPS_CP0_DIAG MIPS_CP0_32(22, 0)
76 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
77 #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
78 #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3)
79 #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4)
80 #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5)
81 #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6)
82 #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7)
85 #define KVM_MAX_VCPUS 16
86 /* memory slots that does not exposed to userspace */
87 #define KVM_PRIVATE_MEM_SLOTS 0
89 #define KVM_HALT_POLL_NS_DEFAULT 500000
91 extern unsigned long GUESTID_MASK;
92 extern unsigned long GUESTID_FIRST_VERSION;
93 extern unsigned long GUESTID_VERSION_MASK;
95 #define KVM_INVALID_ADDR 0xdeadbeef
98 * EVA has overlapping user & kernel address spaces, so user VAs may be >
99 * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
103 #define KVM_HVA_ERR_BAD (-1UL)
104 #define KVM_HVA_ERR_RO_BAD (-2UL)
106 static inline bool kvm_is_error_hva(unsigned long addr)
108 return IS_ERR_VALUE(addr);
112 ulong remote_tlb_flush;
115 struct kvm_vcpu_stat {
120 u64 cop_unusable_exits;
122 u64 tlbmiss_ld_exits;
123 u64 tlbmiss_st_exits;
124 u64 addrerr_st_exits;
125 u64 addrerr_ld_exits;
127 u64 resvd_inst_exits;
128 u64 break_inst_exits;
132 u64 msa_disabled_exits;
133 u64 flush_dcache_exits;
142 #ifdef CONFIG_CPU_LOONGSON64
145 u64 halt_successful_poll;
146 u64 halt_attempted_poll;
147 u64 halt_poll_success_ns;
148 u64 halt_poll_fail_ns;
149 u64 halt_poll_invalid;
153 struct kvm_arch_memory_slot {
156 #ifdef CONFIG_CPU_LOONGSON64
165 struct loongson_kvm_ipi;
167 struct ipi_io_device {
169 struct loongson_kvm_ipi *ipi;
170 struct kvm_io_device device;
173 struct loongson_kvm_ipi {
176 struct ipi_state ipistate[16];
177 struct ipi_io_device dev_ipi[4];
182 /* Guest physical mm */
183 struct mm_struct gpa_mm;
184 /* Mask of CPUs needing GPA ASID flush */
185 cpumask_t asid_flush_mask;
186 #ifdef CONFIG_CPU_LOONGSON64
187 struct loongson_kvm_ipi ipi;
191 #define N_MIPS_COPROC_REGS 32
192 #define N_MIPS_COPROC_SEL 8
195 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
196 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
197 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
202 * Coprocessor 0 register names
204 #define MIPS_CP0_TLB_INDEX 0
205 #define MIPS_CP0_TLB_RANDOM 1
206 #define MIPS_CP0_TLB_LOW 2
207 #define MIPS_CP0_TLB_LO0 2
208 #define MIPS_CP0_TLB_LO1 3
209 #define MIPS_CP0_TLB_CONTEXT 4
210 #define MIPS_CP0_TLB_PG_MASK 5
211 #define MIPS_CP0_TLB_WIRED 6
212 #define MIPS_CP0_HWRENA 7
213 #define MIPS_CP0_BAD_VADDR 8
214 #define MIPS_CP0_COUNT 9
215 #define MIPS_CP0_TLB_HI 10
216 #define MIPS_CP0_COMPARE 11
217 #define MIPS_CP0_STATUS 12
218 #define MIPS_CP0_CAUSE 13
219 #define MIPS_CP0_EXC_PC 14
220 #define MIPS_CP0_PRID 15
221 #define MIPS_CP0_CONFIG 16
222 #define MIPS_CP0_LLADDR 17
223 #define MIPS_CP0_WATCH_LO 18
224 #define MIPS_CP0_WATCH_HI 19
225 #define MIPS_CP0_TLB_XCONTEXT 20
226 #define MIPS_CP0_DIAG 22
227 #define MIPS_CP0_ECC 26
228 #define MIPS_CP0_CACHE_ERR 27
229 #define MIPS_CP0_TAG_LO 28
230 #define MIPS_CP0_TAG_HI 29
231 #define MIPS_CP0_ERROR_PC 30
232 #define MIPS_CP0_DEBUG 23
233 #define MIPS_CP0_DEPC 24
234 #define MIPS_CP0_PERFCNT 25
235 #define MIPS_CP0_ERRCTL 26
236 #define MIPS_CP0_DATA_LO 28
237 #define MIPS_CP0_DATA_HI 29
238 #define MIPS_CP0_DESAVE 31
240 #define MIPS_CP0_CONFIG_SEL 0
241 #define MIPS_CP0_CONFIG1_SEL 1
242 #define MIPS_CP0_CONFIG2_SEL 2
243 #define MIPS_CP0_CONFIG3_SEL 3
244 #define MIPS_CP0_CONFIG4_SEL 4
245 #define MIPS_CP0_CONFIG5_SEL 5
247 #define MIPS_CP0_GUESTCTL2 10
248 #define MIPS_CP0_GUESTCTL2_SEL 5
249 #define MIPS_CP0_GTOFFSET 12
250 #define MIPS_CP0_GTOFFSET_SEL 7
253 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
254 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
256 #define RESUME_GUEST 0
257 #define RESUME_GUEST_DR RESUME_FLAG_DR
258 #define RESUME_HOST RESUME_FLAG_HOST
260 enum emulation_result {
261 EMULATE_DONE, /* no further processing */
262 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
263 EMULATE_FAIL, /* can't emulate this instruction */
264 EMULATE_WAIT, /* WAIT instruction */
266 EMULATE_EXCEPT, /* A guest exception has been generated */
267 EMULATE_HYPERCALL, /* HYPCALL instruction */
270 #if defined(CONFIG_64BIT)
271 #define VPN2_MASK GENMASK(cpu_vmbits - 1, 13)
273 #define VPN2_MASK 0xffffe000
275 #define KVM_ENTRYHI_ASID cpu_asid_mask(&boot_cpu_data)
276 #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
277 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
278 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
279 #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1)
280 #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
281 #define TLB_IS_DIRTY(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D)
282 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
283 ((y) & VPN2_MASK & ~(x).tlb_mask))
284 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
285 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
287 struct kvm_mips_tlb {
293 #define KVM_MIPS_AUX_FPU 0x1
294 #define KVM_MIPS_AUX_MSA 0x2
296 struct kvm_vcpu_arch {
298 int (*vcpu_run)(struct kvm_vcpu *vcpu);
300 /* Host registers preserved across guest mode execution */
301 unsigned long host_stack;
302 unsigned long host_gp;
303 unsigned long host_pgd;
304 unsigned long host_entryhi;
306 /* Host CP0 registers used when handling exits from guest */
307 unsigned long host_cp0_badvaddr;
308 unsigned long host_cp0_epc;
310 u32 host_cp0_guestctl0;
311 u32 host_cp0_badinstr;
312 u32 host_cp0_badinstrp;
315 unsigned long gprs[32];
321 struct mips_fpu_struct fpu;
322 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
323 unsigned int aux_inuse;
326 struct mips_coproc *cop0;
328 /* Resume PC after MMIO completion */
330 /* GPR used as IO source/target */
333 struct hrtimer comparecount_timer;
334 /* Count timer control KVM register */
336 /* Count bias from the raw time */
338 /* Frequency of timer in Hz */
340 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
343 ktime_t count_resume;
344 /* Period of timer tick in ns */
347 /* Bitmask of exceptions that are pending */
348 unsigned long pending_exceptions;
350 /* Bitmask of pending exceptions to be cleared */
351 unsigned long pending_exceptions_clr;
353 /* Cache some mmu pages needed inside spinlock regions */
354 struct kvm_mmu_memory_cache mmu_page_cache;
356 /* vcpu's vzguestid is different on each host cpu in an smp system */
357 u32 vzguestid[NR_CPUS];
359 /* wired guest TLB entries */
360 struct kvm_mips_tlb *wired_tlb;
361 unsigned int wired_tlb_limit;
362 unsigned int wired_tlb_used;
364 /* emulated guest MAAR registers */
365 unsigned long maar[6];
367 /* Last CPU the VCPU state was loaded on */
369 /* Last CPU the VCPU actually executed guest code on */
379 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
384 __asm__ __volatile__(
386 " .set "MIPS_ISA_ARCH_LEVEL" \n"
391 : "=&r" (temp), "+m" (*reg)
393 } while (unlikely(!temp));
396 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
401 __asm__ __volatile__(
403 " .set "MIPS_ISA_ARCH_LEVEL" \n"
408 : "=&r" (temp), "+m" (*reg)
410 } while (unlikely(!temp));
413 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
414 unsigned long change,
419 __asm__ __volatile__(
421 " .set "MIPS_ISA_ARCH_LEVEL" \n"
427 : "=&r" (temp), "+m" (*reg)
428 : "r" (~change), "r" (val & change));
429 } while (unlikely(!temp));
432 /* Guest register types, used in accessor build below */
434 #define __KVMTl unsigned long
437 * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg()
438 * These operate on the saved guest C0 state in RAM.
441 /* Generate saved context simple accessors */
442 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \
443 static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \
445 return cop0->reg[(_reg)][(sel)]; \
447 static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0, \
450 cop0->reg[(_reg)][(sel)] = val; \
453 /* Generate saved context bitwise modifiers */
454 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \
455 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \
458 cop0->reg[(_reg)][(sel)] |= val; \
460 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \
463 cop0->reg[(_reg)][(sel)] &= ~val; \
465 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \
469 unsigned long _mask = mask; \
470 cop0->reg[(_reg)][(sel)] &= ~_mask; \
471 cop0->reg[(_reg)][(sel)] |= val & _mask; \
474 /* Generate saved context atomic bitwise modifiers */
475 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \
476 static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \
479 _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
481 static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \
484 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
486 static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \
490 _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \
495 * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg()
496 * These operate on the VZ guest C0 context in hardware.
499 /* Generate VZ guest context simple accessors */
500 #define __BUILD_KVM_RW_VZ(name, type, _reg, sel) \
501 static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \
503 return read_gc0_##name(); \
505 static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0, \
508 write_gc0_##name(val); \
511 /* Generate VZ guest context bitwise modifiers */
512 #define __BUILD_KVM_SET_VZ(name, type, _reg, sel) \
513 static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0, \
516 set_gc0_##name(val); \
518 static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0, \
521 clear_gc0_##name(val); \
523 static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0, \
527 change_gc0_##name(mask, val); \
530 /* Generate VZ guest context save/restore to/from saved context */
531 #define __BUILD_KVM_SAVE_VZ(name, _reg, sel) \
532 static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0) \
534 write_gc0_##name(cop0->reg[(_reg)][(sel)]); \
536 static inline void kvm_save_gc0_##name(struct mips_coproc *cop0) \
538 cop0->reg[(_reg)][(sel)] = read_gc0_##name(); \
542 * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2()
543 * These wrap a set of operations to provide them with a different name.
546 /* Generate simple accessor wrapper */
547 #define __BUILD_KVM_RW_WRAP(name1, name2, type) \
548 static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0) \
550 return kvm_read_##name2(cop0); \
552 static inline void kvm_write_##name1(struct mips_coproc *cop0, \
555 kvm_write_##name2(cop0, val); \
558 /* Generate bitwise modifier wrapper */
559 #define __BUILD_KVM_SET_WRAP(name1, name2, type) \
560 static inline void kvm_set_##name1(struct mips_coproc *cop0, \
563 kvm_set_##name2(cop0, val); \
565 static inline void kvm_clear_##name1(struct mips_coproc *cop0, \
568 kvm_clear_##name2(cop0, val); \
570 static inline void kvm_change_##name1(struct mips_coproc *cop0, \
574 kvm_change_##name2(cop0, mask, val); \
578 * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg()
579 * These generate accessors operating on the saved context in RAM, and wrap them
580 * with the common guest C0 accessors (for use by common emulation code).
583 #define __BUILD_KVM_RW_SW(name, type, _reg, sel) \
584 __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \
585 __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type)
587 #define __BUILD_KVM_SET_SW(name, type, _reg, sel) \
588 __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \
589 __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
591 #define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel) \
592 __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \
593 __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
596 * VZ (hardware assisted virtualisation)
597 * These macros use the active guest state in VZ mode (hardware registers),
601 * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg()
602 * These generate accessors operating on the VZ guest context in hardware, and
603 * wrap them with the common guest C0 accessors (for use by common emulation
606 * Accessors operating on the saved context in RAM are also generated to allow
607 * convenient explicit saving and restoring of the state.
610 #define __BUILD_KVM_RW_HW(name, type, _reg, sel) \
611 __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \
612 __BUILD_KVM_RW_VZ(name, type, _reg, sel) \
613 __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type) \
614 __BUILD_KVM_SAVE_VZ(name, _reg, sel)
616 #define __BUILD_KVM_SET_HW(name, type, _reg, sel) \
617 __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \
618 __BUILD_KVM_SET_VZ(name, type, _reg, sel) \
619 __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type)
622 * We can't do atomic modifications of COP0 state if hardware can modify it.
623 * Races must be handled explicitly.
625 #define __BUILD_KVM_ATOMIC_HW __BUILD_KVM_SET_HW
628 * Define accessors for CP0 registers that are accessible to the guest. These
629 * are primarily used by common emulation code, which may need to access the
630 * registers differently depending on the implementation.
632 * fns_hw/sw name type reg num select
634 __BUILD_KVM_RW_HW(index, 32, MIPS_CP0_TLB_INDEX, 0)
635 __BUILD_KVM_RW_HW(entrylo0, l, MIPS_CP0_TLB_LO0, 0)
636 __BUILD_KVM_RW_HW(entrylo1, l, MIPS_CP0_TLB_LO1, 0)
637 __BUILD_KVM_RW_HW(context, l, MIPS_CP0_TLB_CONTEXT, 0)
638 __BUILD_KVM_RW_HW(contextconfig, 32, MIPS_CP0_TLB_CONTEXT, 1)
639 __BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT, 2)
640 __BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3)
641 __BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0)
642 __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1)
643 __BUILD_KVM_RW_HW(segctl0, l, MIPS_CP0_TLB_PG_MASK, 2)
644 __BUILD_KVM_RW_HW(segctl1, l, MIPS_CP0_TLB_PG_MASK, 3)
645 __BUILD_KVM_RW_HW(segctl2, l, MIPS_CP0_TLB_PG_MASK, 4)
646 __BUILD_KVM_RW_HW(pwbase, l, MIPS_CP0_TLB_PG_MASK, 5)
647 __BUILD_KVM_RW_HW(pwfield, l, MIPS_CP0_TLB_PG_MASK, 6)
648 __BUILD_KVM_RW_HW(pwsize, l, MIPS_CP0_TLB_PG_MASK, 7)
649 __BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0)
650 __BUILD_KVM_RW_HW(pwctl, 32, MIPS_CP0_TLB_WIRED, 6)
651 __BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0)
652 __BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR, 0)
653 __BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR, 1)
654 __BUILD_KVM_RW_HW(badinstrp, 32, MIPS_CP0_BAD_VADDR, 2)
655 __BUILD_KVM_RW_SW(count, 32, MIPS_CP0_COUNT, 0)
656 __BUILD_KVM_RW_HW(entryhi, l, MIPS_CP0_TLB_HI, 0)
657 __BUILD_KVM_RW_HW(compare, 32, MIPS_CP0_COMPARE, 0)
658 __BUILD_KVM_RW_HW(status, 32, MIPS_CP0_STATUS, 0)
659 __BUILD_KVM_RW_HW(intctl, 32, MIPS_CP0_STATUS, 1)
660 __BUILD_KVM_RW_HW(cause, 32, MIPS_CP0_CAUSE, 0)
661 __BUILD_KVM_RW_HW(epc, l, MIPS_CP0_EXC_PC, 0)
662 __BUILD_KVM_RW_SW(prid, 32, MIPS_CP0_PRID, 0)
663 __BUILD_KVM_RW_HW(ebase, l, MIPS_CP0_PRID, 1)
664 __BUILD_KVM_RW_HW(config, 32, MIPS_CP0_CONFIG, 0)
665 __BUILD_KVM_RW_HW(config1, 32, MIPS_CP0_CONFIG, 1)
666 __BUILD_KVM_RW_HW(config2, 32, MIPS_CP0_CONFIG, 2)
667 __BUILD_KVM_RW_HW(config3, 32, MIPS_CP0_CONFIG, 3)
668 __BUILD_KVM_RW_HW(config4, 32, MIPS_CP0_CONFIG, 4)
669 __BUILD_KVM_RW_HW(config5, 32, MIPS_CP0_CONFIG, 5)
670 __BUILD_KVM_RW_HW(config6, 32, MIPS_CP0_CONFIG, 6)
671 __BUILD_KVM_RW_HW(config7, 32, MIPS_CP0_CONFIG, 7)
672 __BUILD_KVM_RW_SW(maari, l, MIPS_CP0_LLADDR, 2)
673 __BUILD_KVM_RW_HW(xcontext, l, MIPS_CP0_TLB_XCONTEXT, 0)
674 __BUILD_KVM_RW_HW(errorepc, l, MIPS_CP0_ERROR_PC, 0)
675 __BUILD_KVM_RW_HW(kscratch1, l, MIPS_CP0_DESAVE, 2)
676 __BUILD_KVM_RW_HW(kscratch2, l, MIPS_CP0_DESAVE, 3)
677 __BUILD_KVM_RW_HW(kscratch3, l, MIPS_CP0_DESAVE, 4)
678 __BUILD_KVM_RW_HW(kscratch4, l, MIPS_CP0_DESAVE, 5)
679 __BUILD_KVM_RW_HW(kscratch5, l, MIPS_CP0_DESAVE, 6)
680 __BUILD_KVM_RW_HW(kscratch6, l, MIPS_CP0_DESAVE, 7)
682 /* Bitwise operations (on HW state) */
683 __BUILD_KVM_SET_HW(status, 32, MIPS_CP0_STATUS, 0)
684 /* Cause can be modified asynchronously from hardirq hrtimer callback */
685 __BUILD_KVM_ATOMIC_HW(cause, 32, MIPS_CP0_CAUSE, 0)
686 __BUILD_KVM_SET_HW(ebase, l, MIPS_CP0_PRID, 1)
688 /* Bitwise operations (on saved state) */
689 __BUILD_KVM_SET_SAVED(config, 32, MIPS_CP0_CONFIG, 0)
690 __BUILD_KVM_SET_SAVED(config1, 32, MIPS_CP0_CONFIG, 1)
691 __BUILD_KVM_SET_SAVED(config2, 32, MIPS_CP0_CONFIG, 2)
692 __BUILD_KVM_SET_SAVED(config3, 32, MIPS_CP0_CONFIG, 3)
693 __BUILD_KVM_SET_SAVED(config4, 32, MIPS_CP0_CONFIG, 4)
694 __BUILD_KVM_SET_SAVED(config5, 32, MIPS_CP0_CONFIG, 5)
698 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
700 return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
704 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
706 return kvm_mips_guest_can_have_fpu(vcpu) &&
707 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
710 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
712 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
716 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
718 return kvm_mips_guest_can_have_msa(vcpu) &&
719 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
722 struct kvm_mips_callbacks {
723 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
724 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
725 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
726 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
727 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
728 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
729 int (*handle_syscall)(struct kvm_vcpu *vcpu);
730 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
731 int (*handle_break)(struct kvm_vcpu *vcpu);
732 int (*handle_trap)(struct kvm_vcpu *vcpu);
733 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
734 int (*handle_fpe)(struct kvm_vcpu *vcpu);
735 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
736 int (*handle_guest_exit)(struct kvm_vcpu *vcpu);
737 int (*hardware_enable)(void);
738 void (*hardware_disable)(void);
739 int (*check_extension)(struct kvm *kvm, long ext);
740 int (*vcpu_init)(struct kvm_vcpu *vcpu);
741 void (*vcpu_uninit)(struct kvm_vcpu *vcpu);
742 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
743 void (*flush_shadow_all)(struct kvm *kvm);
745 * Must take care of flushing any cached GPA PTEs (e.g. guest entries in
746 * VZ root TLB, or T&E GVA page tables and corresponding root TLB
749 void (*flush_shadow_memslot)(struct kvm *kvm,
750 const struct kvm_memory_slot *slot);
751 gpa_t (*gva_to_gpa)(gva_t gva);
752 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
753 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
754 void (*queue_io_int)(struct kvm_vcpu *vcpu,
755 struct kvm_mips_interrupt *irq);
756 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
757 struct kvm_mips_interrupt *irq);
758 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
760 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
762 unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
763 int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
764 int (*get_one_reg)(struct kvm_vcpu *vcpu,
765 const struct kvm_one_reg *reg, s64 *v);
766 int (*set_one_reg)(struct kvm_vcpu *vcpu,
767 const struct kvm_one_reg *reg, s64 v);
768 int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
769 int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu);
770 int (*vcpu_run)(struct kvm_vcpu *vcpu);
771 void (*vcpu_reenter)(struct kvm_vcpu *vcpu);
773 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
774 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
776 /* Debug: dump vcpu state */
777 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
779 extern int kvm_mips_handle_exit(struct kvm_vcpu *vcpu);
781 /* Building of entry/exception code */
782 int kvm_mips_entry_setup(void);
783 void *kvm_mips_build_vcpu_run(void *addr);
784 void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler);
785 void *kvm_mips_build_exception(void *addr, void *handler);
786 void *kvm_mips_build_exit(void *addr);
788 /* FPU/MSA context management */
789 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
790 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
791 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
792 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
793 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
794 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
795 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
796 void kvm_own_fpu(struct kvm_vcpu *vcpu);
797 void kvm_own_msa(struct kvm_vcpu *vcpu);
798 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
799 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
802 int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
803 struct kvm_vcpu *vcpu, bool write_fault);
805 int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
806 int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
808 void kvm_vz_local_flush_roottlb_all_guests(void);
809 void kvm_vz_local_flush_guesttlb_all(void);
810 void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index,
812 void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
814 #ifdef CONFIG_CPU_LOONGSON64
815 void kvm_loongson_clear_guest_vtlb(void);
816 void kvm_loongson_clear_guest_ftlb(void);
821 bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
822 int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
823 pgd_t *kvm_pgd_alloc(void);
824 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
826 #define KVM_ARCH_WANT_MMU_NOTIFIER
827 int kvm_unmap_hva_range(struct kvm *kvm,
828 unsigned long start, unsigned long end, unsigned flags);
829 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
830 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
831 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
834 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
835 int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
836 int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
839 * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
840 * @vcpu: Virtual CPU.
842 * Returns: Whether the TLBL exception was likely due to an instruction
843 * fetch fault rather than a data load fault.
845 static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
847 unsigned long badvaddr = vcpu->host_cp0_badvaddr;
848 unsigned long epc = msk_isa16_mode(vcpu->pc);
849 u32 cause = vcpu->host_cp0_cause;
855 * Branches may be 32-bit or 16-bit instructions.
856 * This isn't exact, but we don't really support MIPS16 or microMIPS yet
859 if ((cause & CAUSEF_BD) && badvaddr - epc <= 4)
865 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu);
867 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
868 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
869 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
870 void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz);
871 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
872 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
873 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
874 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
875 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
876 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
878 /* fairly internal functions requiring some care to use */
879 int kvm_mips_count_disabled(struct kvm_vcpu *vcpu);
880 ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count);
881 int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
882 u32 count, int min_drift);
884 void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu);
885 void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu);
887 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
889 struct kvm_vcpu *vcpu);
890 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
892 struct kvm_vcpu *vcpu);
895 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu);
897 /* Hypercalls (hypcall.c) */
899 enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
900 union mips_instruction inst);
901 int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
904 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
905 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
906 extern int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
907 struct kvm_mips_interrupt *irq);
909 static inline void kvm_arch_hardware_unsetup(void) {}
910 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
911 static inline void kvm_arch_free_memslot(struct kvm *kvm,
912 struct kvm_memory_slot *slot) {}
913 static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {}
914 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
915 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
916 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
917 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
919 #endif /* __MIPS_KVM_HOST_H__ */