2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
10 #ifndef _ASM_HAZARDS_H
11 #define _ASM_HAZARDS_H
13 #include <linux/stringify.h>
14 #include <asm/compiler.h>
25 #if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
26 !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)
29 * MIPSR2 defines ehb for hazard avoidance
32 #define __mtc0_tlbw_hazard \
35 #define __mtc0_tlbr_hazard \
38 #define __tlbw_use_hazard \
41 #define __tlb_read_hazard \
44 #define __tlb_probe_hazard \
47 #define __irq_enable_hazard \
50 #define __irq_disable_hazard \
53 #define __back_to_back_c0_hazard \
57 * gcc has a tradition of misscompiling the previous construct using the
58 * address of a label as argument to inline assembler. Gas otoh has the
59 * annoying difference between la and dla which are only usable for 32-bit
60 * rsp. 64-bit code, so can't be used without conditional compilation.
61 * The alternative is switching the assembler to 64-bit code which happens
62 * to work right even for 32-bit code...
64 #define instruction_hazard() \
68 __asm__ __volatile__( \
70 " .set "MIPS_ISA_LEVEL" \n" \
78 #elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
79 defined(CONFIG_CPU_BMIPS)
82 * These are slightly complicated by the fact that we guarantee R1 kernels to
83 * run fine on R2 processors.
86 #define __mtc0_tlbw_hazard \
91 #define __mtc0_tlbr_hazard \
96 #define __tlbw_use_hazard \
102 #define __tlb_read_hazard \
108 #define __tlb_probe_hazard \
114 #define __irq_enable_hazard \
120 #define __irq_disable_hazard \
126 #define __back_to_back_c0_hazard \
133 * gcc has a tradition of misscompiling the previous construct using the
134 * address of a label as argument to inline assembler. Gas otoh has the
135 * annoying difference between la and dla which are only usable for 32-bit
136 * rsp. 64-bit code, so can't be used without conditional compilation.
137 * The alternative is switching the assembler to 64-bit code which happens
138 * to work right even for 32-bit code...
140 #define __instruction_hazard() \
144 __asm__ __volatile__( \
146 " .set mips64r2 \n" \
154 #define instruction_hazard() \
156 if (cpu_has_mips_r2_r6) \
157 __instruction_hazard(); \
160 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
161 defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
162 defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
165 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
168 #define __mtc0_tlbw_hazard
170 #define __mtc0_tlbr_hazard
172 #define __tlbw_use_hazard
174 #define __tlb_read_hazard
176 #define __tlb_probe_hazard
178 #define __irq_enable_hazard
180 #define __irq_disable_hazard
182 #define __back_to_back_c0_hazard
184 #define instruction_hazard() do { } while (0)
186 #elif defined(CONFIG_CPU_SB1)
189 * Mostly like R4000 for historic reasons
191 #define __mtc0_tlbw_hazard
193 #define __mtc0_tlbr_hazard
195 #define __tlbw_use_hazard
197 #define __tlb_read_hazard
199 #define __tlb_probe_hazard
201 #define __irq_enable_hazard
203 #define __irq_disable_hazard \
208 #define __back_to_back_c0_hazard
210 #define instruction_hazard() do { } while (0)
215 * Finally the catchall case for all other processors including R4000, R4400,
216 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
218 * The taken branch will result in a two cycle penalty for the two killed
219 * instructions on R4000 / R4400. Other processors only have a single cycle
220 * hazard so this is nice trick to have an optimal code for a range of
223 #define __mtc0_tlbw_hazard \
227 #define __mtc0_tlbr_hazard \
231 #define __tlbw_use_hazard \
236 #define __tlb_read_hazard \
241 #define __tlb_probe_hazard \
246 #define __irq_enable_hazard \
251 #define __irq_disable_hazard \
256 #define __back_to_back_c0_hazard \
261 #define instruction_hazard() do { } while (0)
268 #if defined(CONFIG_CPU_SB1)
270 #define __enable_fpu_hazard \
279 #define __disable_fpu_hazard
281 #elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
283 #define __enable_fpu_hazard \
286 #define __disable_fpu_hazard \
291 #define __enable_fpu_hazard \
297 #define __disable_fpu_hazard \
304 #define _ssnop ___ssnop
306 #define mtc0_tlbw_hazard __mtc0_tlbw_hazard
307 #define mtc0_tlbr_hazard __mtc0_tlbr_hazard
308 #define tlbw_use_hazard __tlbw_use_hazard
309 #define tlb_read_hazard __tlb_read_hazard
310 #define tlb_probe_hazard __tlb_probe_hazard
311 #define irq_enable_hazard __irq_enable_hazard
312 #define irq_disable_hazard __irq_disable_hazard
313 #define back_to_back_c0_hazard __back_to_back_c0_hazard
314 #define enable_fpu_hazard __enable_fpu_hazard
315 #define disable_fpu_hazard __disable_fpu_hazard
321 __asm__ __volatile__( \
322 __stringify(___ssnop) \
328 __asm__ __volatile__( \
329 __stringify(___ehb) \
334 #define mtc0_tlbw_hazard() \
336 __asm__ __volatile__( \
337 __stringify(__mtc0_tlbw_hazard) \
342 #define mtc0_tlbr_hazard() \
344 __asm__ __volatile__( \
345 __stringify(__mtc0_tlbr_hazard) \
350 #define tlbw_use_hazard() \
352 __asm__ __volatile__( \
353 __stringify(__tlbw_use_hazard) \
358 #define tlb_read_hazard() \
360 __asm__ __volatile__( \
361 __stringify(__tlb_read_hazard) \
366 #define tlb_probe_hazard() \
368 __asm__ __volatile__( \
369 __stringify(__tlb_probe_hazard) \
374 #define irq_enable_hazard() \
376 __asm__ __volatile__( \
377 __stringify(__irq_enable_hazard) \
382 #define irq_disable_hazard() \
384 __asm__ __volatile__( \
385 __stringify(__irq_disable_hazard) \
390 #define back_to_back_c0_hazard() \
392 __asm__ __volatile__( \
393 __stringify(__back_to_back_c0_hazard) \
398 #define enable_fpu_hazard() \
400 __asm__ __volatile__( \
401 __stringify(__enable_fpu_hazard) \
406 #define disable_fpu_hazard() \
408 __asm__ __volatile__( \
409 __stringify(__disable_fpu_hazard) \
414 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
416 extern void mips_ihb(void);
418 #endif /* __ASSEMBLY__ */
420 #endif /* _ASM_HAZARDS_H */