2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
13 #include <linux/futex.h>
14 #include <linux/uaccess.h>
15 #include <asm/asm-eva.h>
16 #include <asm/barrier.h>
17 #include <asm/compiler.h>
18 #include <asm/errno.h>
22 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
24 if (cpu_has_llsc && R10000_LLSC_WAR) { \
25 __asm__ __volatile__( \
29 " .set arch=r4000 \n" \
30 "1: ll %1, %4 # __futex_atomic_op \n" \
33 " .set arch=r4000 \n" \
36 __stringify(__WEAK_LLSC_MB) " \n" \
40 " .section .fixup,\"ax\" \n" \
44 " .section __ex_table,\"a\" \n" \
45 " "__UA_ADDR "\t1b, 4b \n" \
46 " "__UA_ADDR "\t2b, 4b \n" \
48 : "=r" (ret), "=&r" (oldval), \
49 "=" GCC_OFF_SMALL_ASM() (*uaddr) \
50 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
53 } else if (cpu_has_llsc) { \
54 __asm__ __volatile__( \
58 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
59 " " __SYNC(full, loongson3_war) " \n" \
60 "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
63 " .set "MIPS_ISA_ARCH_LEVEL" \n" \
64 "2: "user_sc("$1", "%2")" \n" \
66 __stringify(__WEAK_LLSC_MB) " \n" \
70 " .section .fixup,\"ax\" \n" \
74 " .section __ex_table,\"a\" \n" \
75 " "__UA_ADDR "\t1b, 4b \n" \
76 " "__UA_ADDR "\t2b, 4b \n" \
78 : "=r" (ret), "=&r" (oldval), \
79 "=" GCC_OFF_SMALL_ASM() (*uaddr) \
80 : "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
88 arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
96 __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
100 __futex_atomic_op("addu $1, %1, %z5",
101 ret, oldval, uaddr, oparg);
104 __futex_atomic_op("or $1, %1, %z5",
105 ret, oldval, uaddr, oparg);
108 __futex_atomic_op("and $1, %1, %z5",
109 ret, oldval, uaddr, ~oparg);
112 __futex_atomic_op("xor $1, %1, %z5",
113 ret, oldval, uaddr, oparg);
128 futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
129 u32 oldval, u32 newval)
134 if (!access_ok(uaddr, sizeof(u32)))
137 if (cpu_has_llsc && R10000_LLSC_WAR) {
138 __asm__ __volatile__(
139 "# futex_atomic_cmpxchg_inatomic \n"
143 " .set arch=r4000 \n"
145 " bne %1, %z4, 3f \n"
148 " .set arch=r4000 \n"
151 __stringify(__WEAK_LLSC_MB) " \n"
155 " .section .fixup,\"ax\" \n"
159 " .section __ex_table,\"a\" \n"
160 " "__UA_ADDR "\t1b, 4b \n"
161 " "__UA_ADDR "\t2b, 4b \n"
163 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
164 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
167 } else if (cpu_has_llsc) {
168 __asm__ __volatile__(
169 "# futex_atomic_cmpxchg_inatomic \n"
173 " .set "MIPS_ISA_ARCH_LEVEL" \n"
174 " " __SYNC(full, loongson3_war) " \n"
175 "1: "user_ll("%1", "%3")" \n"
176 " bne %1, %z4, 3f \n"
179 " .set "MIPS_ISA_ARCH_LEVEL" \n"
180 "2: "user_sc("$1", "%2")" \n"
182 "3: " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n"
185 " .section .fixup,\"ax\" \n"
189 " .section __ex_table,\"a\" \n"
190 " "__UA_ADDR "\t1b, 4b \n"
191 " "__UA_ADDR "\t2b, 4b \n"
193 : "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
194 : GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
205 #endif /* _ASM_FUTEX_H */