2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
13 #include <asm/cpu-info.h>
14 #include <cpu-feature-overrides.h>
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
24 #define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB)
26 #ifndef cpu_has_tlbinv
27 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
29 #ifndef cpu_has_segments
30 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
33 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
36 #define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
39 #define cpu_has_ldpte (cpu_data[0].options & MIPS_CPU_LDPTE)
41 #ifndef cpu_has_rixiex
42 #define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
45 #define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
47 #ifndef cpu_has_rw_llb
48 #define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
52 * For the moment we don't consider R6000 and R8000 so we can assume that
53 * anything that doesn't support R4000-style exceptions and interrupts is
54 * R3000-like. Users should still treat these two macro definitions as
58 #define cpu_has_3kex (!cpu_has_4kex)
61 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
63 #ifndef cpu_has_3k_cache
64 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
66 #define cpu_has_6k_cache 0
67 #define cpu_has_8k_cache 0
68 #ifndef cpu_has_4k_cache
69 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
71 #ifndef cpu_has_tx39_cache
72 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
74 #ifndef cpu_has_octeon_cache
75 #define cpu_has_octeon_cache 0
77 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
79 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
80 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
82 #define raw_cpu_has_fpu cpu_has_fpu
85 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
87 #ifndef cpu_has_counter
88 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
91 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
94 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
97 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
99 #ifndef cpu_has_cache_cdex_p
100 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
102 #ifndef cpu_has_cache_cdex_s
103 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
105 #ifndef cpu_has_prefetch
106 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
108 #ifndef cpu_has_mcheck
109 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
111 #ifndef cpu_has_ejtag
112 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
115 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
117 #ifndef cpu_has_bp_ghist
118 #define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST)
120 #ifndef kernel_uses_llsc
121 #define kernel_uses_llsc cpu_has_llsc
123 #ifndef cpu_has_mips16
124 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
127 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
129 #ifndef cpu_has_mips3d
130 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
132 #ifndef cpu_has_smartmips
133 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
137 #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
140 #ifndef cpu_has_mmips
141 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
142 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
144 # define cpu_has_mmips 0
149 #define cpu_has_lpa (cpu_data[0].options & MIPS_CPU_LPA)
152 #define cpu_has_mvh (cpu_data[0].options & MIPS_CPU_MVH)
155 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh)
157 #ifndef cpu_has_vtag_icache
158 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
160 #ifndef cpu_has_dc_aliases
161 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
163 #ifndef cpu_has_ic_fills_f_dc
164 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
166 #ifndef cpu_has_pindexed_dcache
167 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
169 #ifndef cpu_has_local_ebase
170 #define cpu_has_local_ebase 1
174 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
175 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
176 * don't. For maintaining I-cache coherency this means we need to flush the
177 * D-cache all the way back to whever the I-cache does refills from, so the
178 * I-cache has a chance to see the new data at all. Then we have to flush the
180 * Note we may have been rescheduled and may no longer be running on the CPU
181 * that did the store so we can't optimize this into only doing the flush on
184 #ifndef cpu_icache_snoops_remote_store
186 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
188 #define cpu_icache_snoops_remote_store 1
192 #ifndef cpu_has_mips_1
193 # define cpu_has_mips_1 (!cpu_has_mips_r6)
195 #ifndef cpu_has_mips_2
196 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
198 #ifndef cpu_has_mips_3
199 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
201 #ifndef cpu_has_mips_4
202 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
204 #ifndef cpu_has_mips_5
205 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
207 #ifndef cpu_has_mips32r1
208 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
210 #ifndef cpu_has_mips32r2
211 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
213 #ifndef cpu_has_mips32r6
214 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
216 #ifndef cpu_has_mips64r1
217 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
219 #ifndef cpu_has_mips64r2
220 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
222 #ifndef cpu_has_mips64r6
223 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
229 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
230 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
231 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
233 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
234 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
235 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
236 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
238 #define cpu_has_mips_3_4_5_64_r2_r6 \
239 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
240 #define cpu_has_mips_4_5_64_r2_r6 \
241 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \
242 cpu_has_mips_r2 | cpu_has_mips_r6)
244 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
245 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
246 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
247 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
248 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
249 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
250 cpu_has_mips32r6 | cpu_has_mips64r1 | \
251 cpu_has_mips64r2 | cpu_has_mips64r6)
253 /* MIPSR2 and MIPSR6 have a lot of similarities */
254 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
257 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
259 * Returns non-zero value if the current processor implementation requires
260 * an IHB instruction to deal with an instruction hazard as per MIPS R2
261 * architecture specification, zero otherwise.
263 #ifndef cpu_has_mips_r2_exec_hazard
264 #define cpu_has_mips_r2_exec_hazard \
268 switch (current_cpu_type()) { \
275 case CPU_QEMU_GENERIC: \
276 case CPU_CAVIUM_OCTEON: \
277 case CPU_CAVIUM_OCTEON_PLUS: \
278 case CPU_CAVIUM_OCTEON2: \
279 case CPU_CAVIUM_OCTEON3: \
292 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
293 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
294 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
295 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
297 #ifndef cpu_has_clo_clz
298 #define cpu_has_clo_clz cpu_has_mips_r
302 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
303 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
304 * This indicates the availability of WSBH and in case of 64 bit CPUs also
308 #define cpu_has_wsbh cpu_has_mips_r2
312 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
316 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
320 #define cpu_has_dsp3 (cpu_data[0].ases & MIPS_ASE_DSP3)
323 #ifndef cpu_has_mipsmt
324 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
328 #define cpu_has_vp (cpu_data[0].options & MIPS_CPU_VP)
331 #ifndef cpu_has_userlocal
332 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
336 # ifndef cpu_has_nofpuex
337 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
339 # ifndef cpu_has_64bits
340 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
342 # ifndef cpu_has_64bit_zero_reg
343 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
345 # ifndef cpu_has_64bit_gp_regs
346 # define cpu_has_64bit_gp_regs 0
348 # ifndef cpu_has_64bit_addresses
349 # define cpu_has_64bit_addresses 0
352 # define cpu_vmbits 31
357 # ifndef cpu_has_nofpuex
358 # define cpu_has_nofpuex 0
360 # ifndef cpu_has_64bits
361 # define cpu_has_64bits 1
363 # ifndef cpu_has_64bit_zero_reg
364 # define cpu_has_64bit_zero_reg 1
366 # ifndef cpu_has_64bit_gp_regs
367 # define cpu_has_64bit_gp_regs 1
369 # ifndef cpu_has_64bit_addresses
370 # define cpu_has_64bit_addresses 1
373 # define cpu_vmbits cpu_data[0].vmbits
374 # define __NEED_VMBITS_PROBE
378 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
379 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
380 #elif !defined(cpu_has_vint)
381 # define cpu_has_vint 0
384 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
385 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
386 #elif !defined(cpu_has_veic)
387 # define cpu_has_veic 0
390 #ifndef cpu_has_inclusive_pcaches
391 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
394 #ifndef cpu_dcache_line_size
395 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz
397 #ifndef cpu_icache_line_size
398 #define cpu_icache_line_size() cpu_data[0].icache.linesz
400 #ifndef cpu_scache_line_size
401 #define cpu_scache_line_size() cpu_data[0].scache.linesz
404 #ifndef cpu_hwrena_impl_bits
405 #define cpu_hwrena_impl_bits 0
408 #ifndef cpu_has_perf_cntr_intr_bit
409 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
413 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
416 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
417 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
418 #elif !defined(cpu_has_msa)
419 # define cpu_has_msa 0
423 # define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
427 # define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
430 #ifndef cpu_has_small_pages
431 # define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP)
434 #ifndef cpu_has_nan_legacy
435 #define cpu_has_nan_legacy (cpu_data[0].options & MIPS_CPU_NAN_LEGACY)
437 #ifndef cpu_has_nan_2008
438 #define cpu_has_nan_2008 (cpu_data[0].options & MIPS_CPU_NAN_2008)
441 #endif /* __ASM_CPU_FEATURES_H */