2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
7 * Copyright (C) 1999 by Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 * Some useful macros for MIPS assembler code
13 * Some of the routines below contain useless nops that will be optimized
14 * away by gas in -O mode. These nops are however required to fill delay
15 * slots in noreorder mode.
20 #include <asm/sgidefs.h>
21 #include <asm/asm-eva.h>
24 * LEAF - declare leaf routine
26 #define LEAF(symbol) \
29 .type symbol, @function; \
31 symbol: .frame sp, 0, ra; \
36 * NESTED - declare nested routine entry point
38 #define NESTED(symbol, framesize, rpc) \
41 .type symbol, @function; \
43 symbol: .frame sp, framesize, rpc; \
48 * END - mark end of function
50 #define END(function) \
53 .size function, .-function
56 * EXPORT - export definition of symbol
58 #define EXPORT(symbol) \
63 * FEXPORT - export definition of a function symbol
65 #define FEXPORT(symbol) \
67 .type symbol, @function; \
71 * ABS - export absolute symbol
73 #define ABS(symbol,value) \
87 * Print formatted string
90 #define PRINT(string) \
102 .pushsection .data; \
109 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
113 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
119 * Macros to handle different pointer/register sizes for 32/64-bit code
132 * Use the following macros in assemblercode to load/store registers,
135 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
138 #define REG_SUBU subu
139 #define REG_ADDU addu
141 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
144 #define REG_SUBU dsubu
145 #define REG_ADDU daddu
149 * How to add/sub/load/store/shift C int variables.
151 #if (_MIPS_SZINT == 32)
153 #define INT_ADDU addu
154 #define INT_ADDI addi
155 #define INT_ADDIU addiu
157 #define INT_SUBU subu
161 #define INT_SLLV sllv
163 #define INT_SRLV srlv
165 #define INT_SRAV srav
168 #if (_MIPS_SZINT == 64)
170 #define INT_ADDU daddu
171 #define INT_ADDI daddi
172 #define INT_ADDIU daddiu
174 #define INT_SUBU dsubu
178 #define INT_SLLV dsllv
180 #define INT_SRLV dsrlv
182 #define INT_SRAV dsrav
186 * How to add/sub/load/store/shift C long variables.
188 #if (_MIPS_SZLONG == 32)
190 #define LONG_ADDU addu
191 #define LONG_ADDI addi
192 #define LONG_ADDIU addiu
194 #define LONG_SUBU subu
199 #define LONG_SLLV sllv
201 #define LONG_SRLV srlv
203 #define LONG_SRAV srav
211 #if (_MIPS_SZLONG == 64)
212 #define LONG_ADD dadd
213 #define LONG_ADDU daddu
214 #define LONG_ADDI daddi
215 #define LONG_ADDIU daddiu
216 #define LONG_SUB dsub
217 #define LONG_SUBU dsubu
221 #define LONG_SLL dsll
222 #define LONG_SLLV dsllv
223 #define LONG_SRL dsrl
224 #define LONG_SRLV dsrlv
225 #define LONG_SRA dsra
226 #define LONG_SRAV dsrav
235 * How to add/sub/load/store/shift pointers.
237 #if (_MIPS_SZPTR == 32)
239 #define PTR_ADDU addu
240 #define PTR_ADDI addi
241 #define PTR_ADDIU addiu
243 #define PTR_SUBU subu
249 #define PTR_SLLV sllv
251 #define PTR_SRLV srlv
253 #define PTR_SRAV srav
255 #define PTR_SCALESHIFT 2
262 #if (_MIPS_SZPTR == 64)
264 #define PTR_ADDU daddu
265 #define PTR_ADDI daddi
266 #define PTR_ADDIU daddiu
268 #define PTR_SUBU dsubu
274 #define PTR_SLLV dsllv
276 #define PTR_SRLV dsrlv
278 #define PTR_SRAV dsrav
280 #define PTR_SCALESHIFT 3
288 * Some cp0 registers were extended to 64bit for MIPS III.
290 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
294 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
299 #define SSNOP sll zero, zero, 1
301 #ifdef CONFIG_SGI_IP28
302 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
303 #include <asm/cacheops.h>
304 #define R10KCBARRIER(addr) cache Cache_Barrier, addr;
306 #define R10KCBARRIER(addr)
309 #endif /* __ASM_ASM_H */