2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
7 * Copyright (C) 1999 by Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 * Some useful macros for MIPS assembler code
13 * Some of the routines below contain useless nops that will be optimized
14 * away by gas in -O mode. These nops are however required to fill delay
15 * slots in noreorder mode.
20 #include <asm/sgidefs.h>
21 #include <asm/asm-eva.h>
25 #define __CAT(str1, str2) str1##str2
27 #define __CAT(str1, str2) str1/**/str2
29 #define CAT(str1, str2) __CAT(str1, str2)
33 * LEAF - declare leaf routine
35 #define LEAF(symbol) \
38 .type symbol, @function; \
40 symbol: .frame sp, 0, ra; \
45 * NESTED - declare nested routine entry point
47 #define NESTED(symbol, framesize, rpc) \
50 .type symbol, @function; \
52 symbol: .frame sp, framesize, rpc; \
57 * END - mark end of function
59 #define END(function) \
62 .size function, .-function
65 * EXPORT - export definition of symbol
67 #define EXPORT(symbol) \
72 * FEXPORT - export definition of a function symbol
74 #define FEXPORT(symbol) \
76 .type symbol, @function; \
80 * ABS - export absolute symbol
82 #define ABS(symbol,value) \
96 * Print formatted string
99 #define PRINT(string) \
107 #define PRINT(string)
111 .pushsection .data; \
118 #define TTABLE(string) \
119 .pushsection .text; \
122 .pushsection .data; \
127 * MIPS IV pref instruction.
128 * Use with .set noreorder only!
130 * MIPS IV implementations are free to treat this as a nop. The R5000
131 * is one of them. So we should have an option not to use this instruction.
133 #ifdef CONFIG_CPU_HAS_PREFETCH
135 #define PREF(hint,addr) \
141 #define PREFE(hint, addr) \
148 #define PREFX(hint,addr) \
154 #else /* !CONFIG_CPU_HAS_PREFETCH */
156 #define PREF(hint, addr)
157 #define PREFE(hint, addr)
158 #define PREFX(hint, addr)
160 #endif /* !CONFIG_CPU_HAS_PREFETCH */
165 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
169 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
175 * Macros to handle different pointer/register sizes for 32/64-bit code
188 * Use the following macros in assemblercode to load/store registers,
191 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
194 #define REG_SUBU subu
195 #define REG_ADDU addu
197 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
200 #define REG_SUBU dsubu
201 #define REG_ADDU daddu
205 * How to add/sub/load/store/shift C int variables.
207 #if (_MIPS_SZINT == 32)
209 #define INT_ADDU addu
210 #define INT_ADDI addi
211 #define INT_ADDIU addiu
213 #define INT_SUBU subu
217 #define INT_SLLV sllv
219 #define INT_SRLV srlv
221 #define INT_SRAV srav
224 #if (_MIPS_SZINT == 64)
226 #define INT_ADDU daddu
227 #define INT_ADDI daddi
228 #define INT_ADDIU daddiu
230 #define INT_SUBU dsubu
234 #define INT_SLLV dsllv
236 #define INT_SRLV dsrlv
238 #define INT_SRAV dsrav
242 * How to add/sub/load/store/shift C long variables.
244 #if (_MIPS_SZLONG == 32)
246 #define LONG_ADDU addu
247 #define LONG_ADDI addi
248 #define LONG_ADDIU addiu
250 #define LONG_SUBU subu
255 #define LONG_SLLV sllv
257 #define LONG_SRLV srlv
259 #define LONG_SRAV srav
267 #if (_MIPS_SZLONG == 64)
268 #define LONG_ADD dadd
269 #define LONG_ADDU daddu
270 #define LONG_ADDI daddi
271 #define LONG_ADDIU daddiu
272 #define LONG_SUB dsub
273 #define LONG_SUBU dsubu
277 #define LONG_SLL dsll
278 #define LONG_SLLV dsllv
279 #define LONG_SRL dsrl
280 #define LONG_SRLV dsrlv
281 #define LONG_SRA dsra
282 #define LONG_SRAV dsrav
291 * How to add/sub/load/store/shift pointers.
293 #if (_MIPS_SZPTR == 32)
295 #define PTR_ADDU addu
296 #define PTR_ADDI addi
297 #define PTR_ADDIU addiu
299 #define PTR_SUBU subu
305 #define PTR_SLLV sllv
307 #define PTR_SRLV srlv
309 #define PTR_SRAV srav
311 #define PTR_SCALESHIFT 2
318 #if (_MIPS_SZPTR == 64)
320 #define PTR_ADDU daddu
321 #define PTR_ADDI daddi
322 #define PTR_ADDIU daddiu
324 #define PTR_SUBU dsubu
330 #define PTR_SLLV dsllv
332 #define PTR_SRLV dsrlv
334 #define PTR_SRAV dsrav
336 #define PTR_SCALESHIFT 3
344 * Some cp0 registers were extended to 64bit for MIPS III.
346 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
350 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
355 #define SSNOP sll zero, zero, 1
357 #ifdef CONFIG_SGI_IP28
358 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
359 #include <asm/cacheops.h>
360 #define R10KCBARRIER(addr) cache Cache_Barrier, addr;
362 #define R10KCBARRIER(addr)
365 #endif /* __ASM_ASM_H */