2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
9 #include <linux/delay.h>
10 #include <linux/smp.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/sched.h>
14 #include <linux/sched/hotplug.h>
15 #include <linux/sched/task_stack.h>
16 #include <linux/init.h>
17 #include <linux/export.h>
19 #include <asm/mmu_context.h>
21 #include <asm/setup.h>
23 #include <asm/octeon/octeon.h>
25 #include "octeon_boot.h"
27 volatile unsigned long octeon_processor_boot = 0xff;
28 volatile unsigned long octeon_processor_sp;
29 volatile unsigned long octeon_processor_gp;
30 #ifdef CONFIG_RELOCATABLE
31 volatile unsigned long octeon_processor_relocated_kernel_entry;
32 #endif /* CONFIG_RELOCATABLE */
34 #ifdef CONFIG_HOTPLUG_CPU
35 uint64_t octeon_bootloader_entry_addr;
36 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
39 extern void kernel_entry(unsigned long arg1, ...);
41 static void octeon_icache_flush(void)
43 asm volatile ("synci 0($0)\n");
46 static void (*octeon_message_functions[8])(void) = {
48 generic_smp_call_function_interrupt,
52 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
54 u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num());
59 * Make sure the function array initialization remains
62 BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0));
63 BUILD_BUG_ON(SMP_CALL_FUNCTION != (1 << 1));
64 BUILD_BUG_ON(SMP_ICACHE_FLUSH != (1 << 2));
67 * Load the mailbox register to figure out what we're supposed
70 action = cvmx_read_csr(mbox_clrx);
72 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
77 /* Clear the mailbox to clear the interrupt */
78 cvmx_write_csr(mbox_clrx, action);
80 for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) {
82 void (*fn)(void) = octeon_message_functions[i];
94 * Cause the function described by call_data to be executed on the passed
95 * cpu. When the function has finished, increment the finished field of
98 void octeon_send_ipi_single(int cpu, unsigned int action)
100 int coreid = cpu_logical_map(cpu);
102 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
105 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
108 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
113 for_each_cpu(i, mask)
114 octeon_send_ipi_single(i, action);
118 * Detect available CPUs, populate cpu_possible_mask
120 static void octeon_smp_hotplug_setup(void)
122 #ifdef CONFIG_HOTPLUG_CPU
123 struct linux_app_boot_info *labi;
128 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
129 if (labi->labi_signature != LABI_SIGNATURE) {
130 pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
134 octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
138 static void __init octeon_smp_setup(void)
140 const int coreid = cvmx_get_core_num();
143 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
145 #ifdef CONFIG_HOTPLUG_CPU
146 int core_mask = octeon_get_boot_coremask();
147 unsigned int num_cores = cvmx_octeon_num_cores();
150 /* The present CPUs are initially just the boot cpu (CPU 0). */
151 for (id = 0; id < NR_CPUS; id++) {
152 set_cpu_possible(id, id == 0);
153 set_cpu_present(id, id == 0);
156 __cpu_number_map[coreid] = 0;
157 __cpu_logical_map[0] = coreid;
159 /* The present CPUs get the lowest CPU numbers. */
161 for (id = 0; id < NR_CPUS; id++) {
162 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
163 set_cpu_possible(cpus, true);
164 set_cpu_present(cpus, true);
165 __cpu_number_map[id] = cpus;
166 __cpu_logical_map[cpus] = id;
171 #ifdef CONFIG_HOTPLUG_CPU
173 * The possible CPUs are all those present on the chip. We
174 * will assign CPU numbers for possible cores as well. Cores
175 * are always consecutively numberd from 0.
177 for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
178 id < num_cores && id < NR_CPUS; id++) {
179 if (!(core_mask & (1 << id))) {
180 set_cpu_possible(cpus, true);
181 __cpu_number_map[id] = cpus;
182 __cpu_logical_map[cpus] = id;
188 octeon_smp_hotplug_setup();
192 #ifdef CONFIG_RELOCATABLE
193 int plat_post_relocation(long offset)
195 unsigned long entry = (unsigned long)kernel_entry;
197 /* Send secondaries into relocated kernel */
198 octeon_processor_relocated_kernel_entry = entry + offset;
202 #endif /* CONFIG_RELOCATABLE */
205 * Firmware CPU startup hook
208 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
212 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
213 cpu_logical_map(cpu));
215 octeon_processor_sp = __KSTK_TOS(idle);
216 octeon_processor_gp = (unsigned long)(task_thread_info(idle));
217 octeon_processor_boot = cpu_logical_map(cpu);
221 while (octeon_processor_sp && count) {
222 /* Waiting for processor to get the SP and GP */
227 pr_err("Secondary boot timeout\n");
231 * After we've done initial boot, this function is called to allow the
232 * board code to clean up state, if needed
234 static void octeon_init_secondary(void)
238 sr = set_c0_status(ST0_BEV);
239 write_c0_ebase((u32)ebase);
242 octeon_check_cpu_bist();
243 octeon_init_cvmcount();
245 octeon_irq_setup_secondary();
249 * Callout to firmware before smp_init
252 static void __init octeon_prepare_cpus(unsigned int max_cpus)
255 * Only the low order mailbox bits are used for IPIs, leave
256 * the other bits alone.
258 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
259 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
260 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
261 mailbox_interrupt)) {
262 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
267 * Last chance for the board code to finish SMP initialization before
268 * the CPU is "online".
270 static void octeon_smp_finish(void)
272 octeon_user_io_init();
274 /* to generate the first CPU timer interrupt */
275 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
279 #ifdef CONFIG_HOTPLUG_CPU
281 /* State of each CPU. */
282 DEFINE_PER_CPU(int, cpu_state);
284 static int octeon_cpu_disable(void)
286 unsigned int cpu = smp_processor_id();
291 if (!octeon_bootloader_entry_addr)
294 set_cpu_online(cpu, false);
295 calculate_cpu_foreign_map();
299 local_flush_tlb_all();
304 static void octeon_cpu_die(unsigned int cpu)
306 int coreid = cpu_logical_map(cpu);
307 uint32_t mask, new_mask;
308 const struct cvmx_bootmem_named_block_desc *block_desc;
310 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
314 * This is a bit complicated strategics of getting/settig available
315 * cores mask, copied from bootloader
319 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
320 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
323 struct linux_app_boot_info *labi;
325 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
327 labi->avail_coremask |= mask;
328 new_mask = labi->avail_coremask;
329 } else { /* alternative, already initialized */
330 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
331 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
336 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
338 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
339 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
344 int cpu = cpu_number_map(cvmx_get_core_num());
347 octeon_processor_boot = 0xff;
348 per_cpu(cpu_state, cpu) = CPU_DEAD;
352 while (1) /* core will be reset here */
356 static void start_after_reset(void)
358 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
361 static int octeon_update_boot_vector(unsigned int cpu)
364 int coreid = cpu_logical_map(cpu);
365 uint32_t avail_coremask;
366 const struct cvmx_bootmem_named_block_desc *block_desc;
367 struct boot_init_vector *boot_vect =
368 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
370 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
373 struct linux_app_boot_info *labi;
375 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
377 avail_coremask = labi->avail_coremask;
378 labi->avail_coremask &= ~(1 << coreid);
379 } else { /* alternative, already initialized */
380 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
381 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
384 if (!(avail_coremask & (1 << coreid))) {
385 /* core not available, assume, that caught by simple-executive */
386 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
387 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
390 boot_vect[coreid].app_start_func_addr =
391 (uint32_t) (unsigned long) start_after_reset;
392 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
396 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
401 static int register_cavium_notifier(void)
403 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
404 "mips/cavium:prepare",
405 octeon_update_boot_vector, NULL);
407 late_initcall(register_cavium_notifier);
409 #endif /* CONFIG_HOTPLUG_CPU */
411 struct plat_smp_ops octeon_smp_ops = {
412 .send_ipi_single = octeon_send_ipi_single,
413 .send_ipi_mask = octeon_send_ipi_mask,
414 .init_secondary = octeon_init_secondary,
415 .smp_finish = octeon_smp_finish,
416 .boot_secondary = octeon_boot_secondary,
417 .smp_setup = octeon_smp_setup,
418 .prepare_cpus = octeon_prepare_cpus,
419 #ifdef CONFIG_HOTPLUG_CPU
420 .cpu_disable = octeon_cpu_disable,
421 .cpu_die = octeon_cpu_die,
425 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id)
431 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id)
433 generic_smp_call_function_interrupt();
437 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id)
439 octeon_icache_flush();
444 * Callout to firmware before smp_init
446 static void octeon_78xx_prepare_cpus(unsigned int max_cpus)
448 if (request_irq(OCTEON_IRQ_MBOX0 + 0,
449 octeon_78xx_reched_interrupt,
450 IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler",
451 octeon_78xx_reched_interrupt)) {
452 panic("Cannot request_irq for SchedulerIPI");
454 if (request_irq(OCTEON_IRQ_MBOX0 + 1,
455 octeon_78xx_call_function_interrupt,
456 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call",
457 octeon_78xx_call_function_interrupt)) {
458 panic("Cannot request_irq for SMP-Call");
460 if (request_irq(OCTEON_IRQ_MBOX0 + 2,
461 octeon_78xx_icache_flush_interrupt,
462 IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush",
463 octeon_78xx_icache_flush_interrupt)) {
464 panic("Cannot request_irq for ICache-Flush");
468 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action)
472 for (i = 0; i < 8; i++) {
474 octeon_ciu3_mbox_send(cpu, i);
479 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask,
484 for_each_cpu(cpu, mask)
485 octeon_78xx_send_ipi_single(cpu, action);
488 static struct plat_smp_ops octeon_78xx_smp_ops = {
489 .send_ipi_single = octeon_78xx_send_ipi_single,
490 .send_ipi_mask = octeon_78xx_send_ipi_mask,
491 .init_secondary = octeon_init_secondary,
492 .smp_finish = octeon_smp_finish,
493 .boot_secondary = octeon_boot_secondary,
494 .smp_setup = octeon_smp_setup,
495 .prepare_cpus = octeon_78xx_prepare_cpus,
496 #ifdef CONFIG_HOTPLUG_CPU
497 .cpu_disable = octeon_cpu_disable,
498 .cpu_die = octeon_cpu_die,
502 void __init octeon_setup_smp(void)
504 struct plat_smp_ops *ops;
506 if (octeon_has_feature(OCTEON_FEATURE_CIU3))
507 ops = &octeon_78xx_smp_ops;
509 ops = &octeon_smp_ops;
511 register_smp_ops(ops);