arch/mips/boot/dts/ingenic/jz4740.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/jz4740-cgu.h>
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "ingenic,jz4740";
   8
   9         cpuintc: interrupt-controller {
  10                 #address-cells = <0>;
  11                 #interrupt-cells = <1>;
  12                 interrupt-controller;
  13                 compatible = "mti,cpu-interrupt-controller";
  14         };
  15
  16         intc: interrupt-controller@10001000 {
  17                 compatible = "ingenic,jz4740-intc";
  18                 reg = <0x10001000 0x14>;
  19
  20                 interrupt-controller;
  21                 #interrupt-cells = <1>;
  22
  23                 interrupt-parent = <&cpuintc>;
  24                 interrupts = <2>;
  25         };
  26
  27         ext: ext {
  28                 compatible = "fixed-clock";
  29                 #clock-cells = <0>;
  30         };
  31
  32         rtc: rtc {
  33                 compatible = "fixed-clock";
  34                 #clock-cells = <0>;
  35                 clock-frequency = <32768>;
  36         };
  37
  38         cgu: jz4740-cgu@10000000 {
  39                 compatible = "ingenic,jz4740-cgu";
  40                 reg = <0x10000000 0x100>;
  41
  42                 clocks = <&ext>, <&rtc>;
  43                 clock-names = "ext", "rtc";
  44
  45                 #clock-cells = <1>;
  46         };
  47
  48         watchdog: watchdog@10002000 {
  49                 compatible = "ingenic,jz4740-watchdog";
  50                 reg = <0x10002000 0x10>;
  51
  52                 clocks = <&cgu JZ4740_CLK_RTC>;
  53                 clock-names = "rtc";
  54         };
  55
  56         rtc_dev: rtc@10003000 {
  57                 compatible = "ingenic,jz4740-rtc";
  58                 reg = <0x10003000 0x40>;
  59
  60                 interrupt-parent = <&intc>;
  61                 interrupts = <15>;
  62
  63                 clocks = <&cgu JZ4740_CLK_RTC>;
  64                 clock-names = "rtc";
  65         };
  66
  67         pinctrl: pin-controller@10010000 {
  68                 compatible = "ingenic,jz4740-pinctrl";
  69                 reg = <0x10010000 0x400>;
  70
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 gpa: gpio@0 {
  75                         compatible = "ingenic,jz4740-gpio";
  76                         reg = <0>;
  77
  78                         gpio-controller;
  79                         gpio-ranges = <&pinctrl 0 0 32>;
  80                         #gpio-cells = <2>;
  81
  82                         interrupt-controller;
  83                         #interrupt-cells = <2>;
  84
  85                         interrupt-parent = <&intc>;
  86                         interrupts = <28>;
  87                 };
  88
  89                 gpb: gpio@1 {
  90                         compatible = "ingenic,jz4740-gpio";
  91                         reg = <1>;
  92
  93                         gpio-controller;
  94                         gpio-ranges = <&pinctrl 0 32 32>;
  95                         #gpio-cells = <2>;
  96
  97                         interrupt-controller;
  98                         #interrupt-cells = <2>;
  99
 100                         interrupt-parent = <&intc>;
 101                         interrupts = <27>;
 102                 };
 103
 104                 gpc: gpio@2 {
 105                         compatible = "ingenic,jz4740-gpio";
 106                         reg = <2>;
 107
 108                         gpio-controller;
 109                         gpio-ranges = <&pinctrl 0 64 32>;
 110                         #gpio-cells = <2>;
 111
 112                         interrupt-controller;
 113                         #interrupt-cells = <2>;
 114
 115                         interrupt-parent = <&intc>;
 116                         interrupts = <26>;
 117                 };
 118
 119                 gpd: gpio@3 {
 120                         compatible = "ingenic,jz4740-gpio";
 121                         reg = <3>;
 122
 123                         gpio-controller;
 124                         gpio-ranges = <&pinctrl 0 96 32>;
 125                         #gpio-cells = <2>;
 126
 127                         interrupt-controller;
 128                         #interrupt-cells = <2>;
 129
 130                         interrupt-parent = <&intc>;
 131                         interrupts = <25>;
 132                 };
 133         };
 134
 135         aic: audio-controller@10020000 {
 136                 compatible = "ingenic,jz4740-i2s";
 137                 reg = <0x10020000 0x38>;
 138
 139                 #sound-dai-cells = <0>;
 140
 141                 interrupt-parent = <&intc>;
 142                 interrupts = <18>;
 143
 144                 clocks = <&cgu JZ4740_CLK_AIC>,
 145                          <&cgu JZ4740_CLK_I2S>,
 146                          <&cgu JZ4740_CLK_EXT>,
 147                          <&cgu JZ4740_CLK_PLL_HALF>;
 148                 clock-names = "aic", "i2s", "ext", "pll half";
 149
 150                 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
 151                 dma-names = "rx", "tx";
 152         };
 153
 154         codec: audio-codec@100200a4 {
 155                 compatible = "ingenic,jz4740-codec";
 156                 reg = <0x10020080 0x8>;
 157
 158                 #sound-dai-cells = <0>;
 159
 160                 clocks = <&cgu JZ4740_CLK_AIC>;
 161                 clock-names = "aic";
 162         };
 163
 164         mmc: mmc@10021000 {
 165                 compatible = "ingenic,jz4740-mmc";
 166                 reg = <0x10021000 0x1000>;
 167
 168                 clocks = <&cgu JZ4740_CLK_MMC>;
 169                 clock-names = "mmc";
 170
 171                 interrupt-parent = <&intc>;
 172                 interrupts = <14>;
 173
 174                 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
 175                 dma-names = "rx", "tx";
 176
 177                 cap-sd-highspeed;
 178                 cap-mmc-highspeed;
 179                 cap-sdio-irq;
 180         };
 181
 182         uart0: serial@10030000 {
 183                 compatible = "ingenic,jz4740-uart";
 184                 reg = <0x10030000 0x100>;
 185
 186                 interrupt-parent = <&intc>;
 187                 interrupts = <9>;
 188
 189                 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
 190                 clock-names = "baud", "module";
 191         };
 192
 193         uart1: serial@10031000 {
 194                 compatible = "ingenic,jz4740-uart";
 195                 reg = <0x10031000 0x100>;
 196
 197                 interrupt-parent = <&intc>;
 198                 interrupts = <8>;
 199
 200                 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
 201                 clock-names = "baud", "module";
 202         };
 203
 204         adc: adc@10070000 {
 205                 compatible = "ingenic,jz4740-adc";
 206                 reg = <0x10070000 0x30>;
 207                 #io-channel-cells = <1>;
 208
 209                 clocks = <&cgu JZ4740_CLK_ADC>;
 210                 clock-names = "adc";
 211
 212                 interrupt-parent = <&intc>;
 213                 interrupts = <12>;
 214         };
 215
 216         nemc: memory-controller@13010000 {
 217                 compatible = "ingenic,jz4740-nemc";
 218                 reg = <0x13010000 0x54>;
 219                 #address-cells = <2>;
 220                 #size-cells = <1>;
 221                 ranges = <1 0 0x18000000 0x4000000
 222                           2 0 0x14000000 0x4000000
 223                           3 0 0x0c000000 0x4000000
 224                           4 0 0x08000000 0x4000000>;
 225
 226                 clocks = <&cgu JZ4740_CLK_MCLK>;
 227         };
 228
 229         ecc: ecc-controller@13010100 {
 230                 compatible = "ingenic,jz4740-ecc";
 231                 reg = <0x13010100 0x2C>;
 232
 233                 clocks = <&cgu JZ4740_CLK_MCLK>;
 234         };
 235
 236         dmac: dma-controller@13020000 {
 237                 compatible = "ingenic,jz4740-dma";
 238                 reg = <0x13020000 0xbc
 239                        0x13020300 0x14>;
 240                 #dma-cells = <2>;
 241
 242                 interrupt-parent = <&intc>;
 243                 interrupts = <20>;
 244
 245                 clocks = <&cgu JZ4740_CLK_DMA>;
 246         };
 247
 248         uhc: uhc@13030000 {
 249                 compatible = "ingenic,jz4740-ohci", "generic-ohci";
 250                 reg = <0x13030000 0x1000>;
 251
 252                 clocks = <&cgu JZ4740_CLK_UHC>;
 253                 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
 254                 assigned-clock-rates = <48000000>;
 255
 256                 interrupt-parent = <&intc>;
 257                 interrupts = <3>;
 258
 259                 status = "disabled";
 260         };
 261
 262         udc: usb@13040000 {
 263                 compatible = "ingenic,jz4740-musb";
 264                 reg = <0x13040000 0x10000>;
 265
 266                 interrupt-parent = <&intc>;
 267                 interrupts = <24>;
 268                 interrupt-names = "mc";
 269
 270                 clocks = <&cgu JZ4740_CLK_UDC>;
 271                 clock-names = "udc";
 272         };
 273
 274         lcd: lcd-controller@13050000 {
 275                 compatible = "ingenic,jz4740-lcd";
 276                 reg = <0x13050000 0x1000>;
 277
 278                 interrupt-parent = <&intc>;
 279                 interrupts = <30>;
 280
 281                 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
 282                 clock-names = "lcd_pclk", "lcd";
 283         };
 284 };