arch/mips/boot/dts/ingenic/jz4740.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/jz4740-cgu.h>
   3 #include <dt-bindings/clock/ingenic,tcu.h>
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         compatible = "ingenic,jz4740";
   9
  10         cpuintc: interrupt-controller {
  11                 #address-cells = <0>;
  12                 #interrupt-cells = <1>;
  13                 interrupt-controller;
  14                 compatible = "mti,cpu-interrupt-controller";
  15         };
  16
  17         intc: interrupt-controller@10001000 {
  18                 compatible = "ingenic,jz4740-intc";
  19                 reg = <0x10001000 0x14>;
  20
  21                 interrupt-controller;
  22                 #interrupt-cells = <1>;
  23
  24                 interrupt-parent = <&cpuintc>;
  25                 interrupts = <2>;
  26         };
  27
  28         ext: ext {
  29                 compatible = "fixed-clock";
  30                 #clock-cells = <0>;
  31         };
  32
  33         rtc: rtc {
  34                 compatible = "fixed-clock";
  35                 #clock-cells = <0>;
  36                 clock-frequency = <32768>;
  37         };
  38
  39         cgu: jz4740-cgu@10000000 {
  40                 compatible = "ingenic,jz4740-cgu";
  41                 reg = <0x10000000 0x100>;
  42
  43                 clocks = <&ext>, <&rtc>;
  44                 clock-names = "ext", "rtc";
  45
  46                 #clock-cells = <1>;
  47         };
  48
  49         tcu: timer@10002000 {
  50                 compatible = "ingenic,jz4740-tcu", "simple-mfd";
  51                 reg = <0x10002000 0x1000>;
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges = <0x0 0x10002000 0x1000>;
  55
  56                 #clock-cells = <1>;
  57
  58                 clocks = <&cgu JZ4740_CLK_RTC
  59                           &cgu JZ4740_CLK_EXT
  60                           &cgu JZ4740_CLK_PCLK
  61                           &cgu JZ4740_CLK_TCU>;
  62                 clock-names = "rtc", "ext", "pclk", "tcu";
  63
  64                 interrupt-controller;
  65                 #interrupt-cells = <1>;
  66
  67                 interrupt-parent = <&intc>;
  68                 interrupts = <23 22 21>;
  69
  70                 watchdog: watchdog@0 {
  71                         compatible = "ingenic,jz4740-watchdog";
  72                         reg = <0x0 0xc>;
  73
  74                         clocks = <&tcu TCU_CLK_WDT>;
  75                         clock-names = "wdt";
  76                 };
  77         };
  78
  79         rtc_dev: rtc@10003000 {
  80                 compatible = "ingenic,jz4740-rtc";
  81                 reg = <0x10003000 0x40>;
  82
  83                 interrupt-parent = <&intc>;
  84                 interrupts = <15>;
  85
  86                 clocks = <&cgu JZ4740_CLK_RTC>;
  87                 clock-names = "rtc";
  88         };
  89
  90         pinctrl: pin-controller@10010000 {
  91                 compatible = "ingenic,jz4740-pinctrl";
  92                 reg = <0x10010000 0x400>;
  93
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96
  97                 gpa: gpio@0 {
  98                         compatible = "ingenic,jz4740-gpio";
  99                         reg = <0>;
 100
 101                         gpio-controller;
 102                         gpio-ranges = <&pinctrl 0 0 32>;
 103                         #gpio-cells = <2>;
 104
 105                         interrupt-controller;
 106                         #interrupt-cells = <2>;
 107
 108                         interrupt-parent = <&intc>;
 109                         interrupts = <28>;
 110                 };
 111
 112                 gpb: gpio@1 {
 113                         compatible = "ingenic,jz4740-gpio";
 114                         reg = <1>;
 115
 116                         gpio-controller;
 117                         gpio-ranges = <&pinctrl 0 32 32>;
 118                         #gpio-cells = <2>;
 119
 120                         interrupt-controller;
 121                         #interrupt-cells = <2>;
 122
 123                         interrupt-parent = <&intc>;
 124                         interrupts = <27>;
 125                 };
 126
 127                 gpc: gpio@2 {
 128                         compatible = "ingenic,jz4740-gpio";
 129                         reg = <2>;
 130
 131                         gpio-controller;
 132                         gpio-ranges = <&pinctrl 0 64 32>;
 133                         #gpio-cells = <2>;
 134
 135                         interrupt-controller;
 136                         #interrupt-cells = <2>;
 137
 138                         interrupt-parent = <&intc>;
 139                         interrupts = <26>;
 140                 };
 141
 142                 gpd: gpio@3 {
 143                         compatible = "ingenic,jz4740-gpio";
 144                         reg = <3>;
 145
 146                         gpio-controller;
 147                         gpio-ranges = <&pinctrl 0 96 32>;
 148                         #gpio-cells = <2>;
 149
 150                         interrupt-controller;
 151                         #interrupt-cells = <2>;
 152
 153                         interrupt-parent = <&intc>;
 154                         interrupts = <25>;
 155                 };
 156         };
 157
 158         aic: audio-controller@10020000 {
 159                 compatible = "ingenic,jz4740-i2s";
 160                 reg = <0x10020000 0x38>;
 161
 162                 #sound-dai-cells = <0>;
 163
 164                 interrupt-parent = <&intc>;
 165                 interrupts = <18>;
 166
 167                 clocks = <&cgu JZ4740_CLK_AIC>,
 168                          <&cgu JZ4740_CLK_I2S>,
 169                          <&cgu JZ4740_CLK_EXT>,
 170                          <&cgu JZ4740_CLK_PLL_HALF>;
 171                 clock-names = "aic", "i2s", "ext", "pll half";
 172
 173                 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
 174                 dma-names = "rx", "tx";
 175         };
 176
 177         codec: audio-codec@100200a4 {
 178                 compatible = "ingenic,jz4740-codec";
 179                 reg = <0x10020080 0x8>;
 180
 181                 #sound-dai-cells = <0>;
 182
 183                 clocks = <&cgu JZ4740_CLK_AIC>;
 184                 clock-names = "aic";
 185         };
 186
 187         mmc: mmc@10021000 {
 188                 compatible = "ingenic,jz4740-mmc";
 189                 reg = <0x10021000 0x1000>;
 190
 191                 clocks = <&cgu JZ4740_CLK_MMC>;
 192                 clock-names = "mmc";
 193
 194                 interrupt-parent = <&intc>;
 195                 interrupts = <14>;
 196
 197                 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
 198                 dma-names = "rx", "tx";
 199
 200                 cap-sd-highspeed;
 201                 cap-mmc-highspeed;
 202                 cap-sdio-irq;
 203         };
 204
 205         uart0: serial@10030000 {
 206                 compatible = "ingenic,jz4740-uart";
 207                 reg = <0x10030000 0x100>;
 208
 209                 interrupt-parent = <&intc>;
 210                 interrupts = <9>;
 211
 212                 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
 213                 clock-names = "baud", "module";
 214         };
 215
 216         uart1: serial@10031000 {
 217                 compatible = "ingenic,jz4740-uart";
 218                 reg = <0x10031000 0x100>;
 219
 220                 interrupt-parent = <&intc>;
 221                 interrupts = <8>;
 222
 223                 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
 224                 clock-names = "baud", "module";
 225         };
 226
 227         adc: adc@10070000 {
 228                 compatible = "ingenic,jz4740-adc";
 229                 reg = <0x10070000 0x30>;
 230                 #io-channel-cells = <1>;
 231
 232                 clocks = <&cgu JZ4740_CLK_ADC>;
 233                 clock-names = "adc";
 234
 235                 interrupt-parent = <&intc>;
 236                 interrupts = <12>;
 237         };
 238
 239         nemc: memory-controller@13010000 {
 240                 compatible = "ingenic,jz4740-nemc";
 241                 reg = <0x13010000 0x54>;
 242                 #address-cells = <2>;
 243                 #size-cells = <1>;
 244                 ranges = <1 0 0x18000000 0x4000000
 245                           2 0 0x14000000 0x4000000
 246                           3 0 0x0c000000 0x4000000
 247                           4 0 0x08000000 0x4000000>;
 248
 249                 clocks = <&cgu JZ4740_CLK_MCLK>;
 250         };
 251
 252         ecc: ecc-controller@13010100 {
 253                 compatible = "ingenic,jz4740-ecc";
 254                 reg = <0x13010100 0x2C>;
 255
 256                 clocks = <&cgu JZ4740_CLK_MCLK>;
 257         };
 258
 259         dmac: dma-controller@13020000 {
 260                 compatible = "ingenic,jz4740-dma";
 261                 reg = <0x13020000 0xbc
 262                        0x13020300 0x14>;
 263                 #dma-cells = <2>;
 264
 265                 interrupt-parent = <&intc>;
 266                 interrupts = <20>;
 267
 268                 clocks = <&cgu JZ4740_CLK_DMA>;
 269         };
 270
 271         uhc: uhc@13030000 {
 272                 compatible = "ingenic,jz4740-ohci", "generic-ohci";
 273                 reg = <0x13030000 0x1000>;
 274
 275                 clocks = <&cgu JZ4740_CLK_UHC>;
 276                 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
 277                 assigned-clock-rates = <48000000>;
 278
 279                 interrupt-parent = <&intc>;
 280                 interrupts = <3>;
 281
 282                 status = "disabled";
 283         };
 284
 285         udc: usb@13040000 {
 286                 compatible = "ingenic,jz4740-musb";
 287                 reg = <0x13040000 0x10000>;
 288
 289                 interrupt-parent = <&intc>;
 290                 interrupts = <24>;
 291                 interrupt-names = "mc";
 292
 293                 clocks = <&cgu JZ4740_CLK_UDC>;
 294                 clock-names = "udc";
 295         };
 296
 297         lcd: lcd-controller@13050000 {
 298                 compatible = "ingenic,jz4740-lcd";
 299                 reg = <0x13050000 0x1000>;
 300
 301                 interrupt-parent = <&intc>;
 302                 interrupts = <30>;
 303
 304                 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
 305                 clock-names = "lcd_pclk", "lcd";
 306         };
 307 };