dc3b7909de73282a368ba94e6de7257e7c17bcfb
[linux-2.6-microblaze.git] / arch / mips / boot / dts / img / pistachio.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
4  * Copyright (C) 2015 Google, Inc.
5  */
6
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
12
13 / {
14         compatible = "img,pistachio";
15
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         interrupt-parent = <&gic>;
20
21         cpus {
22                 #address-cells = <1>;
23                 #size-cells = <0>;
24
25                 cpu0: cpu@0 {
26                         device_type = "cpu";
27                         compatible = "mti,interaptiv";
28                         reg = <0>;
29                         clocks = <&clk_core CLK_MIPS_PLL>;
30                         clock-names = "cpu";
31                         clock-latency = <1000>;
32                         operating-points = <
33                                 /* kHz    uV(dummy) */
34                                 546000 1150000
35                                 520000 1100000
36                                 494000 1000000
37                                 468000 950000
38                                 442000 900000
39                                 416000 800000
40                         >;
41                 };
42         };
43
44         i2c0: i2c@18100000 {
45                 compatible = "img,scb-i2c";
46                 reg = <0x18100000 0x200>;
47                 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
48                 clocks = <&clk_periph PERIPH_CLK_I2C0>,
49                          <&cr_periph SYS_CLK_I2C0>;
50                 clock-names = "scb", "sys";
51                 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
52                                   <&clk_periph PERIPH_CLK_I2C0_DIV>;
53                 assigned-clock-rates = <100000000>, <33333334>;
54                 status = "disabled";
55                 pinctrl-names = "default";
56                 pinctrl-0 = <&i2c0_pins>;
57
58                 #address-cells = <1>;
59                 #size-cells = <0>;
60         };
61
62         i2c1: i2c@18100200 {
63                 compatible = "img,scb-i2c";
64                 reg = <0x18100200 0x200>;
65                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
66                 clocks = <&clk_periph PERIPH_CLK_I2C1>,
67                          <&cr_periph SYS_CLK_I2C1>;
68                 clock-names = "scb", "sys";
69                 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
70                                   <&clk_periph PERIPH_CLK_I2C1_DIV>;
71                 assigned-clock-rates = <100000000>, <33333334>;
72                 status = "disabled";
73                 pinctrl-names = "default";
74                 pinctrl-0 = <&i2c1_pins>;
75
76                 #address-cells = <1>;
77                 #size-cells = <0>;
78         };
79
80         i2c2: i2c@18100400 {
81                 compatible = "img,scb-i2c";
82                 reg = <0x18100400 0x200>;
83                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
84                 clocks = <&clk_periph PERIPH_CLK_I2C2>,
85                          <&cr_periph SYS_CLK_I2C2>;
86                 clock-names = "scb", "sys";
87                 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
88                                   <&clk_periph PERIPH_CLK_I2C2_DIV>;
89                 assigned-clock-rates = <100000000>, <33333334>;
90                 status = "disabled";
91                 pinctrl-names = "default";
92                 pinctrl-0 = <&i2c2_pins>;
93
94                 #address-cells = <1>;
95                 #size-cells = <0>;
96         };
97
98         i2c3: i2c@18100600 {
99                 compatible = "img,scb-i2c";
100                 reg = <0x18100600 0x200>;
101                 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
102                 clocks = <&clk_periph PERIPH_CLK_I2C3>,
103                          <&cr_periph SYS_CLK_I2C3>;
104                 clock-names = "scb", "sys";
105                 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
106                                   <&clk_periph PERIPH_CLK_I2C3_DIV>;
107                 assigned-clock-rates = <100000000>, <33333334>;
108                 status = "disabled";
109                 pinctrl-names = "default";
110                 pinctrl-0 = <&i2c3_pins>;
111
112                 #address-cells = <1>;
113                 #size-cells = <0>;
114         };
115
116         i2s_in: i2s-in@18100800 {
117                 compatible = "img,i2s-in";
118                 reg = <0x18100800 0x200>;
119                 interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
120                 dmas = <&mdc 30 0xffffffff 0>;
121                 dma-names = "rx";
122                 clocks = <&cr_periph SYS_CLK_I2S_IN>;
123                 clock-names = "sys";
124                 img,i2s-channels = <6>;
125                 pinctrl-names = "default";
126                 pinctrl-0 = <&i2s_in_pins>;
127                 status = "disabled";
128
129                 #sound-dai-cells = <0>;
130         };
131
132         i2s_out: i2s-out@18100a00 {
133                 compatible = "img,i2s-out";
134                 reg = <0x18100a00 0x200>;
135                 interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
136                 dmas = <&mdc 23 0xffffffff 0>;
137                 dma-names = "tx";
138                 clocks = <&cr_periph SYS_CLK_I2S_OUT>,
139                          <&clk_core CLK_I2S>;
140                 clock-names = "sys", "ref";
141                 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142                 assigned-clock-rates = <12288000>;
143                 img,i2s-channels = <6>;
144                 pinctrl-names = "default";
145                 pinctrl-0 = <&i2s_out_pins>;
146                 status = "disabled";
147                 resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
148                 reset-names = "rst";
149                 #sound-dai-cells = <0>;
150         };
151
152         parallel_out: parallel-audio-out@18100c00 {
153                 compatible = "img,parallel-out";
154                 reg = <0x18100c00 0x100>;
155                 interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
156                 dmas = <&mdc 16 0xffffffff 0>;
157                 dma-names = "tx";
158                 clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
159                          <&clk_core CLK_AUDIO_DAC>;
160                 clock-names = "sys", "ref";
161                 assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
162                 assigned-clock-rates = <12288000>;
163                 status = "disabled";
164                 resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
165                 reset-names = "rst";
166                 #sound-dai-cells = <0>;
167         };
168
169         spdif_out: spdif-out@18100d00 {
170                 compatible = "img,spdif-out";
171                 reg = <0x18100d00 0x100>;
172                 interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
173                 dmas = <&mdc 14 0xffffffff 0>;
174                 dma-names = "tx";
175                 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
176                          <&clk_core CLK_SPDIF>;
177                 clock-names = "sys", "ref";
178                 assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
179                 assigned-clock-rates = <12288000>;
180                 pinctrl-names = "default";
181                 pinctrl-0 = <&spdif_out_pin>;
182                 status = "disabled";
183                 resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
184                 reset-names = "rst";
185                 #sound-dai-cells = <0>;
186         };
187
188         spdif_in: spdif-in@18100e00 {
189                 compatible = "img,spdif-in";
190                 reg = <0x18100e00 0x100>;
191                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
192                 dmas = <&mdc 15 0xffffffff 0>;
193                 dma-names = "rx";
194                 clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
195                 clock-names = "sys";
196                 pinctrl-names = "default";
197                 pinctrl-0 = <&spdif_in_pin>;
198                 status = "disabled";
199
200                 #sound-dai-cells = <0>;
201         };
202
203         internal_dac: internal-dac {
204                 compatible = "img,pistachio-internal-dac";
205                 img,cr-top = <&cr_top>;
206                 img,voltage-select = <1>;
207
208                 #sound-dai-cells = <0>;
209         };
210
211         spfi0: spi@18100f00 {
212                 compatible = "img,spfi";
213                 reg = <0x18100f00 0x100>;
214                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
215                 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
216                 clock-names = "sys", "spfi";
217                 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
218                 dma-names = "rx", "tx";
219                 spfi-max-frequency = <50000000>;
220                 status = "disabled";
221
222                 #address-cells = <1>;
223                 #size-cells = <0>;
224         };
225
226         spfi1: spi@18101000 {
227                 compatible = "img,spfi";
228                 reg = <0x18101000 0x100>;
229                 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
230                 clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
231                 clock-names = "sys", "spfi";
232                 dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
233                 dma-names = "rx", "tx";
234                 img,supports-quad-mode;
235                 spfi-max-frequency = <50000000>;
236                 status = "disabled";
237
238                 #address-cells = <1>;
239                 #size-cells = <0>;
240         };
241
242         pwm: pwm@18101300 {
243                 compatible = "img,pistachio-pwm";
244                 reg = <0x18101300 0x100>;
245                 clocks = <&clk_periph PERIPH_CLK_PWM>,
246                          <&cr_periph SYS_CLK_PWM>;
247                 clock-names = "pwm", "sys";
248                 img,cr-periph = <&cr_periph>;
249                 #pwm-cells = <2>;
250                 status = "disabled";
251         };
252
253         uart0: uart@18101400 {
254                 compatible = "snps,dw-apb-uart";
255                 reg = <0x18101400 0x100>;
256                 interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
257                 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
258                 clock-names = "baudclk", "apb_pclk";
259                 assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
260                                   <&clk_core CLK_UART0_DIV>;
261                 reg-shift = <2>;
262                 reg-io-width = <4>;
263                 pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>;
264                 pinctrl-names = "default";
265                 status = "disabled";
266         };
267
268         uart1: uart@18101500 {
269                 compatible = "snps,dw-apb-uart";
270                 reg = <0x18101500 0x100>;
271                 interrupts = <GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
272                 clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
273                 clock-names = "baudclk", "apb_pclk";
274                 assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
275                                   <&clk_core CLK_UART1_DIV>;
276                 assigned-clock-rates = <114278400>, <1843200>;
277                 reg-shift = <2>;
278                 reg-io-width = <4>;
279                 pinctrl-0 = <&uart1_pins>;
280                 pinctrl-names = "default";
281                 status = "disabled";
282         };
283
284         adc: adc@18101600 {
285                 compatible = "cosmic,10001-adc";
286                 reg = <0x18101600 0x24>;
287                 adc-reserved-channels = <0x30>;
288                 clocks = <&clk_core CLK_AUX_ADC>;
289                 clock-names = "adc";
290                 assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
291                                   <&clk_core CLK_AUX_ADC_DIV>;
292                 assigned-clock-rates = <100000000>, <1000000>;
293                 status = "disabled";
294
295                 #io-channel-cells = <1>;
296         };
297
298         pinctrl: pinctrl@18101c00 {
299                 compatible = "img,pistachio-system-pinctrl";
300                 reg = <0x18101c00 0x400>;
301
302                 gpio0: gpio0 {
303                         interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
304
305                         gpio-controller;
306                         #gpio-cells = <2>;
307                         gpio-ranges = <&pinctrl 0 0 16>;
308
309                         interrupt-controller;
310                         #interrupt-cells = <2>;
311                 };
312
313                 gpio1: gpio1 {
314                         interrupts = <GIC_SHARED 72 IRQ_TYPE_LEVEL_HIGH>;
315
316                         gpio-controller;
317                         #gpio-cells = <2>;
318                         gpio-ranges = <&pinctrl 0 16 16>;
319
320                         interrupt-controller;
321                         #interrupt-cells = <2>;
322                 };
323
324                 gpio2: gpio2 {
325                         interrupts = <GIC_SHARED 73 IRQ_TYPE_LEVEL_HIGH>;
326
327                         gpio-controller;
328                         #gpio-cells = <2>;
329                         gpio-ranges = <&pinctrl 0 32 16>;
330
331                         interrupt-controller;
332                         #interrupt-cells = <2>;
333                 };
334
335                 gpio3: gpio3 {
336                         interrupts = <GIC_SHARED 74 IRQ_TYPE_LEVEL_HIGH>;
337
338                         gpio-controller;
339                         #gpio-cells = <2>;
340                         gpio-ranges = <&pinctrl 0 48 16>;
341
342                         interrupt-controller;
343                         #interrupt-cells = <2>;
344                 };
345
346                 gpio4: gpio4 {
347                         interrupts = <GIC_SHARED 75 IRQ_TYPE_LEVEL_HIGH>;
348
349                         gpio-controller;
350                         #gpio-cells = <2>;
351                         gpio-ranges = <&pinctrl 0 64 16>;
352
353                         interrupt-controller;
354                         #interrupt-cells = <2>;
355                 };
356
357                 gpio5: gpio5 {
358                         interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
359
360                         gpio-controller;
361                         #gpio-cells = <2>;
362                         gpio-ranges = <&pinctrl 0 80 10>;
363
364                         interrupt-controller;
365                         #interrupt-cells = <2>;
366                 };
367
368                 i2c0_pins: i2c0-pins {
369                         pin_i2c0: i2c0 {
370                                 pins = "mfio28", "mfio29";
371                                 function = "i2c0";
372                                 drive-strength = <4>;
373                         };
374                 };
375
376                 i2c1_pins: i2c1-pins {
377                         pin_i2c1: i2c1 {
378                                 pins = "mfio30", "mfio31";
379                                 function = "i2c1";
380                                 drive-strength = <4>;
381                         };
382                 };
383
384                 i2c2_pins: i2c2-pins {
385                         pin_i2c2: i2c2 {
386                                 pins = "mfio32", "mfio33";
387                                 function = "i2c2";
388                                 drive-strength = <4>;
389                         };
390                 };
391
392                 i2c3_pins: i2c3-pins {
393                         pin_i2c3: i2c3 {
394                                 pins = "mfio34", "mfio35";
395                                 function = "i2c3";
396                                 drive-strength = <4>;
397                         };
398                 };
399
400                 spim0_pins: spim0-pins {
401                         pin_spim0: spim0 {
402                                 pins = "mfio9", "mfio10";
403                                 function = "spim0";
404                                 drive-strength = <4>;
405                         };
406                         spim0_clk: spim0-clk {
407                                 pins = "mfio8";
408                                 function = "spim0";
409                                 drive-strength = <4>;
410                         };
411                 };
412
413                 spim0_cs0_alt_pin: spim0-cs0-alt-pin {
414                         spim0-cs0 {
415                                 pins = "mfio2";
416                                 drive-strength = <2>;
417                         };
418                 };
419
420                 spim0_cs1_pin: spim0-cs1-pin {
421                         spim0-cs1 {
422                                 pins = "mfio1";
423                                 drive-strength = <2>;
424                         };
425                 };
426
427                 spim0_cs2_pin: spim0-cs2-pin {
428                         spim0-cs2 {
429                                 pins = "mfio55";
430                                 drive-strength = <2>;
431                         };
432                 };
433
434                 spim0_cs2_alt_pin: spim0-cs2-alt-pin {
435                         spim0-cs2 {
436                                 pins = "mfio28";
437                                 drive-strength = <2>;
438                         };
439                 };
440
441                 spim0_cs3_pin: spim0-cs3-pin {
442                         spim0-cs3 {
443                                 pins = "mfio56";
444                                 drive-strength = <2>;
445                         };
446                 };
447
448                 spim0_cs3_alt_pin: spim0-cs3-alt-pin {
449                         spim0-cs3 {
450                                 pins = "mfio29";
451                                 drive-strength = <2>;
452                         };
453                 };
454
455                 spim0_cs4_pin: spim0-cs4-pin {
456                         spim0-cs4 {
457                                 pins = "mfio57";
458                                 drive-strength = <2>;
459                         };
460                 };
461
462                 spim0_cs4_alt_pin: spim0-cs4-alt-pin {
463                         spim0-cs4 {
464                                 pins = "mfio30";
465                                 drive-strength = <2>;
466                         };
467                 };
468
469                 spim1_pins: spim1-pins {
470                         spim1 {
471                                 pins = "mfio3", "mfio4", "mfio5";
472                                 function = "spim1";
473                                 drive-strength = <2>;
474                         };
475                 };
476
477                 spim1_quad_pins: spim1-quad-pins {
478                         spim1-quad {
479                                 pins = "mfio6", "mfio7";
480                                 function = "spim1";
481                                 drive-strength = <2>;
482                         };
483                 };
484
485                 spim1_cs0_pin: spim1-cs0-pins {
486                         spim1-cs0 {
487                                 pins = "mfio0";
488                                 function = "spim1";
489                                 drive-strength = <2>;
490                         };
491                 };
492
493                 spim1_cs1_pin: spim1-cs1-pin {
494                         spim1-cs1 {
495                                 pins = "mfio1";
496                                 function = "spim1";
497                                 drive-strength = <2>;
498                         };
499                 };
500
501                 spim1_cs1_alt_pin: spim1-cs1-alt-pin {
502                         spim1-cs1 {
503                                 pins = "mfio58";
504                                 function = "spim1";
505                                 drive-strength = <2>;
506                         };
507                 };
508
509                 spim1_cs2_pin: spim1-cs2-pin {
510                         spim1-cs2 {
511                                 pins = "mfio2";
512                                 function = "spim1";
513                                 drive-strength = <2>;
514                         };
515                 };
516
517                 spim1_cs2_alt0_pin: spim1-cs2-alt0-pin {
518                         spim1-cs2 {
519                                 pins = "mfio31";
520                                 function = "spim1";
521                                 drive-strength = <2>;
522                         };
523                 };
524
525                 spim1_cs2_alt1_pin: spim1-cs2-alt1-pin {
526                         spim1-cs2 {
527                                 pins = "mfio55";
528                                 function = "spim1";
529                                 drive-strength = <2>;
530                         };
531                 };
532
533                 spim1_cs3_pin: spim1-cs3-pin {
534                         spim1-cs3 {
535                                 pins = "mfio56";
536                                 function = "spim1";
537                                 drive-strength = <2>;
538                         };
539                 };
540
541                 spim1_cs4_pin: spim1-cs4-pin {
542                         spim1-cs4 {
543                                 pins = "mfio57";
544                                 function = "spim1";
545                                 drive-strength = <2>;
546                         };
547                 };
548
549                 uart0_pins: uart0-pins {
550                         uart0 {
551                                 pins = "mfio55", "mfio56";
552                                 function = "uart0";
553                                 drive-strength = <2>;
554                         };
555                 };
556
557                 uart0_rts_cts_pins: uart0-rts-cts-pins {
558                         uart0-rts-cts {
559                                 pins = "mfio57", "mfio58";
560                                 function = "uart0";
561                                 drive-strength = <2>;
562                         };
563                 };
564
565                 uart1_pins: uart1-pins {
566                         uart1 {
567                                 pins = "mfio59", "mfio60";
568                                 function = "uart1";
569                                 drive-strength = <2>;
570                         };
571                 };
572
573                 uart1_rts_cts_pins: uart1-rts-cts-pins {
574                         uart1-rts-cts {
575                                   pins = "mfio1", "mfio2";
576                                   function = "uart1";
577                                   drive-strength = <2>;
578                         };
579                 };
580
581                 enet_pins: enet-pins {
582                         pin_enet: enet {
583                                 pins = "mfio63", "mfio64", "mfio65", "mfio66",
584                                        "mfio67", "mfio68", "mfio69", "mfio70";
585                                 function = "eth";
586                                 slew-rate = <1>;
587                                 drive-strength = <4>;
588                         };
589                         pin_enet_phy_clk: enet-phy-clk {
590                                 pins = "mfio71";
591                                 function = "eth";
592                                 slew-rate = <1>;
593                                 drive-strength = <8>;
594                         };
595                 };
596
597                 sdhost_pins: sdhost-pins {
598                         pin_sdhost_clk: sdhost-clk {
599                                 pins = "mfio15";
600                                 function = "sdhost";
601                                 slew-rate = <1>;
602                                 drive-strength = <4>;
603                         };
604                         pin_sdhost_cmd: sdhost-cmd {
605                                 pins = "mfio16";
606                                 function = "sdhost";
607                                 slew-rate = <1>;
608                                 drive-strength = <4>;
609                         };
610                         pin_sdhost_data: sdhost-data {
611                                 pins = "mfio17", "mfio18", "mfio19", "mfio20",
612                                        "mfio21", "mfio22", "mfio23", "mfio24";
613                                 function = "sdhost";
614                                 slew-rate = <1>;
615                                 drive-strength = <4>;
616                         };
617                         pin_sdhost_power_select: sdhost-power-select {
618                                 pins = "mfio25";
619                                 function = "sdhost";
620                                 slew-rate = <1>;
621                                 drive-strength = <2>;
622                         };
623                         pin_sdhost_card_detect: sdhost-card-detect {
624                                 pins = "mfio26";
625                                 function = "sdhost";
626                                 drive-strength = <2>;
627                         };
628                         pin_sdhost_write_protect: sdhost-write-protect {
629                                 pins = "mfio27";
630                                 function = "sdhost";
631                                 drive-strength = <2>;
632                         };
633                 };
634
635                 ir_pin: ir-pin {
636                         ir-data {
637                                 pins = "mfio72";
638                                 function = "ir";
639                                 drive-strength = <2>;
640                         };
641                 };
642
643                 pwmpdm0_pin: pwmpdm0-pin {
644                         pwmpdm0 {
645                                 pins = "mfio73";
646                                 function = "pwmpdm";
647                                 drive-strength = <2>;
648                         };
649                 };
650
651                 pwmpdm1_pin: pwmpdm1-pin {
652                         pwmpdm1 {
653                                 pins = "mfio74";
654                                 function = "pwmpdm";
655                                 drive-strength = <2>;
656                         };
657                 };
658
659                 pwmpdm2_pin: pwmpdm2-pin {
660                         pwmpdm2 {
661                                 pins = "mfio75";
662                                 function = "pwmpdm";
663                                 drive-strength = <2>;
664                         };
665                 };
666
667                 pwmpdm3_pin: pwmpdm3-pin {
668                         pwmpdm3 {
669                                 pins = "mfio76";
670                                 function = "pwmpdm";
671                                 drive-strength = <2>;
672                         };
673                 };
674
675                 dac_clk_pin: dac-clk-pin {
676                         pin_dac_clk: dac-clk {
677                                 pins = "mfio45";
678                                 function = "i2s_dac_clk";
679                                 drive-strength = <4>;
680                         };
681                 };
682
683                 i2s_mclk_pin: i2s-mclk-pin {
684                         pin_i2s_mclk: i2s-mclk {
685                                 pins = "mfio36";
686                                 function = "i2s_out";
687                                 drive-strength = <4>;
688                         };
689                 };
690
691                 spdif_out_pin: spdif-out-pin {
692                         spdif-out {
693                                 pins = "mfio61";
694                                 function = "spdif_out";
695                                 slew-rate = <1>;
696                                 drive-strength = <2>;
697                         };
698                 };
699
700                 spdif_in_pin: spdif-in-pin {
701                         spdif-in {
702                                 pins = "mfio62";
703                                 function = "spdif_in";
704                                 drive-strength = <2>;
705                         };
706                 };
707
708                 i2s_out_pins: i2s-out-pins {
709                         pins_i2s_out_clk: i2s-out-clk {
710                                 pins = "mfio37", "mfio38";
711                                 function = "i2s_out";
712                                 drive-strength = <4>;
713                         };
714                         pins_i2s_out: i2s-out {
715                                 pins = "mfio39", "mfio40",
716                                        "mfio41", "mfio42",
717                                        "mfio43", "mfio44";
718                                 function = "i2s_out";
719                                 drive-strength = <2>;
720                         };
721                 };
722
723                 i2s_in_pins: i2s-in-pins {
724                         i2s-in {
725                                 pins = "mfio47", "mfio48", "mfio49",
726                                        "mfio50", "mfio51", "mfio52",
727                                        "mfio53", "mfio54";
728                                 function = "i2s_in";
729                                 drive-strength = <2>;
730                         };
731                 };
732         };
733
734         timer: timer@18102000 {
735                 compatible = "img,pistachio-gptimer";
736                 reg = <0x18102000 0x100>;
737                 interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>;
738                 clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
739                          <&cr_periph SYS_CLK_TIMER>;
740                 clock-names = "fast", "sys";
741                 img,cr-periph = <&cr_periph>;
742         };
743
744         wdt: watchdog@18102100 {
745                 compatible = "img,pdc-wdt";
746                 reg = <0x18102100 0x100>;
747                 interrupts = <GIC_SHARED 52 IRQ_TYPE_LEVEL_HIGH>;
748                 clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
749                 clock-names = "wdt", "sys";
750                 assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
751                                   <&clk_periph PERIPH_CLK_WD_DIV>;
752                 assigned-clock-rates = <4000000>, <32768>;
753         };
754
755         ir: ir@18102200 {
756                 compatible = "img,ir-rev1";
757                 reg = <0x18102200 0x100>;
758                 interrupts = <GIC_SHARED 51 IRQ_TYPE_LEVEL_HIGH>;
759                 clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>;
760                 clock-names = "core", "sys";
761                 assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
762                                   <&clk_periph PERIPH_CLK_IR_DIV>;
763                 assigned-clock-rates = <4000000>, <32768>;
764                 pinctrl-0 = <&ir_pin>;
765                 pinctrl-names = "default";
766                 status = "disabled";
767         };
768
769         usb: usb@18120000 {
770                 compatible = "snps,dwc2";
771                 reg = <0x18120000 0x1c000>;
772                 interrupts = <GIC_SHARED 49 IRQ_TYPE_LEVEL_HIGH>;
773                 phys = <&usb_phy>;
774                 phy-names = "usb2-phy";
775                 g-tx-fifo-size = <256 256 256 256>;
776                 status = "disabled";
777         };
778
779         enet: ethernet@18140000 {
780                 compatible = "snps,dwmac";
781                 reg = <0x18140000 0x2000>;
782                 interrupts = <GIC_SHARED 50 IRQ_TYPE_LEVEL_HIGH>;
783                 interrupt-names = "macirq";
784                 clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>;
785                 clock-names = "stmmaceth", "pclk";
786                 assigned-clocks = <&clk_core CLK_ENET_MUX>,
787                                   <&clk_core CLK_ENET_DIV>;
788                 assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
789                 assigned-clock-rates = <0>, <50000000>;
790                 pinctrl-0 = <&enet_pins>;
791                 pinctrl-names = "default";
792                 phy-mode = "rmii";
793                 status = "disabled";
794         };
795
796         sdhost: mmc@18142000 {
797                 compatible = "img,pistachio-dw-mshc";
798                 reg = <0x18142000 0x400>;
799                 interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>;
800                 clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>;
801                 clock-names = "ciu", "biu";
802                 pinctrl-0 = <&sdhost_pins>;
803                 pinctrl-names = "default";
804                 fifo-depth = <0x20>;
805                 clock-frequency = <50000000>;
806                 bus-width = <8>;
807                 cap-mmc-highspeed;
808                 cap-sd-highspeed;
809                 status = "disabled";
810         };
811
812         sram: sram@1b000000 {
813                 compatible = "mmio-sram";
814                 reg = <0x1b000000 0x10000>;
815         };
816
817         mdc: dma-controller@18143000 {
818                 compatible = "img,pistachio-mdc-dma";
819                 reg = <0x18143000 0x1000>;
820                 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
821                              <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
822                              <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
823                              <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
824                              <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
825                              <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
826                              <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
827                              <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
828                              <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
829                              <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
830                              <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
831                              <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
832                 clocks = <&cr_periph SYS_CLK_MDC>;
833                 clock-names = "sys";
834
835                 img,max-burst-multiplier = <16>;
836                 img,cr-periph = <&cr_periph>;
837
838                 #dma-cells = <3>;
839         };
840
841         clk_core: clk@18144000 {
842                 compatible = "img,pistachio-clk", "syscon";
843                 clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
844                          <&cr_top EXT_CLK_ENET_IN>;
845                 clock-names = "xtal", "audio_refclk_ext_gate",
846                               "ext_enet_in_gate";
847                 reg = <0x18144000 0x800>;
848                 #clock-cells = <1>;
849         };
850
851         clk_periph: clk@18144800 {
852                 compatible = "img,pistachio-clk-periph";
853                 reg = <0x18144800 0x1000>;
854                 clocks = <&clk_core CLK_PERIPH_SYS>;
855                 clock-names = "periph_sys_core";
856                 #clock-cells = <1>;
857         };
858
859         cr_periph: clk@18148000 {
860                 compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
861                 reg = <0x18148000 0x1000>;
862                 clocks = <&clk_periph PERIPH_CLK_SYS>;
863                 clock-names = "sys";
864                 #clock-cells = <1>;
865
866                 pistachio_reset: reset-controller {
867                         compatible = "img,pistachio-reset";
868                         #reset-cells = <1>;
869                 };
870         };
871
872         cr_top: clk@18149000 {
873                 compatible = "img,pistachio-cr-top", "syscon";
874                 reg = <0x18149000 0x200>;
875                 #clock-cells = <1>;
876         };
877
878         hash: hash@18149600 {
879                 compatible = "img,hash-accelerator";
880                 reg = <0x18149600 0x100>, <0x18101100 0x4>;
881                 interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
882                 dmas = <&mdc 8 0xffffffff 0>;
883                 dma-names = "tx";
884                 clocks = <&cr_periph SYS_CLK_HASH>,
885                          <&clk_periph PERIPH_CLK_ROM>;
886                 clock-names = "sys", "hash";
887         };
888
889         gic: interrupt-controller@1bdc0000 {
890                 compatible = "mti,gic";
891                 reg = <0x1bdc0000 0x20000>;
892
893                 interrupt-controller;
894                 #interrupt-cells = <3>;
895
896                 timer {
897                         compatible = "mti,gic-timer";
898                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
899                         clocks = <&clk_core CLK_MIPS>;
900                 };
901         };
902
903         usb_phy: usb-phy {
904                 compatible = "img,pistachio-usb-phy";
905                 clocks = <&clk_core CLK_USB_PHY>;
906                 clock-names = "usb_phy";
907                 assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
908                 assigned-clock-rates = <50000000>;
909                 img,refclk = <0x2>;
910                 img,cr-top = <&cr_top>;
911                 #phy-cells = <0>;
912         };
913
914         xtal: xtal {
915                 compatible = "fixed-clock";
916                 #clock-cells = <0>;
917                 clock-frequency = <52000000>;
918                 clock-output-names = "xtal";
919         };
920 };