2 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
4 * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/init.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
25 #include <asm/mach-ar7/ar7.h>
27 #define AR7_GPIO_MAX 32
28 #define TITAN_GPIO_MAX 51
30 struct ar7_gpio_chip {
32 struct gpio_chip chip;
35 static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
37 struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
38 void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
40 return !!(readl(gpio_in) & (1 << gpio));
43 static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
45 struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
46 void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
47 void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
49 return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
52 static void ar7_gpio_set_value(struct gpio_chip *chip,
53 unsigned gpio, int value)
55 struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
56 void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
59 tmp = readl(gpio_out) & ~(1 << gpio);
62 writel(tmp, gpio_out);
65 static void titan_gpio_set_value(struct gpio_chip *chip,
66 unsigned gpio, int value)
68 struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
69 void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
70 void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
73 tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
75 tmp |= 1 << (gpio & 0x1f);
76 writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
79 static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
81 struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
82 void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
84 writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
89 static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
91 struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
92 void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
93 void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
95 if (gpio >= TITAN_GPIO_MAX)
98 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
99 gpio >> 5 ? gpio_dir1 : gpio_dir0);
103 static int ar7_gpio_direction_output(struct gpio_chip *chip,
104 unsigned gpio, int value)
106 struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
107 void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
109 ar7_gpio_set_value(chip, gpio, value);
110 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
115 static int titan_gpio_direction_output(struct gpio_chip *chip,
116 unsigned gpio, int value)
118 struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
119 void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
120 void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
122 if (gpio >= TITAN_GPIO_MAX)
125 titan_gpio_set_value(chip, gpio, value);
126 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
127 (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
132 static struct ar7_gpio_chip ar7_gpio_chip = {
135 .direction_input = ar7_gpio_direction_input,
136 .direction_output = ar7_gpio_direction_output,
137 .set = ar7_gpio_set_value,
138 .get = ar7_gpio_get_value,
140 .ngpio = AR7_GPIO_MAX,
144 static struct ar7_gpio_chip titan_gpio_chip = {
146 .label = "titan-gpio",
147 .direction_input = titan_gpio_direction_input,
148 .direction_output = titan_gpio_direction_output,
149 .set = titan_gpio_set_value,
150 .get = titan_gpio_get_value,
152 .ngpio = TITAN_GPIO_MAX,
156 static inline int ar7_gpio_enable_ar7(unsigned gpio)
158 void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
160 writel(readl(gpio_en) | (1 << gpio), gpio_en);
165 static inline int ar7_gpio_enable_titan(unsigned gpio)
167 void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
168 void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
170 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
171 gpio >> 5 ? gpio_en1 : gpio_en0);
176 int ar7_gpio_enable(unsigned gpio)
178 return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
179 ar7_gpio_enable_ar7(gpio);
181 EXPORT_SYMBOL(ar7_gpio_enable);
183 static inline int ar7_gpio_disable_ar7(unsigned gpio)
185 void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
187 writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
192 static inline int ar7_gpio_disable_titan(unsigned gpio)
194 void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
195 void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
197 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
198 gpio >> 5 ? gpio_en1 : gpio_en0);
203 int ar7_gpio_disable(unsigned gpio)
205 return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
206 ar7_gpio_disable_ar7(gpio);
208 EXPORT_SYMBOL(ar7_gpio_disable);
210 struct titan_gpio_cfg {
216 static const struct titan_gpio_cfg titan_gpio_table[] = {
217 /* reg, start bit, mux value */
272 static int titan_gpio_pinsel(unsigned gpio)
274 struct titan_gpio_cfg gpio_cfg;
275 u32 mux_status, pin_sel_reg, tmp;
276 void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
278 if (gpio >= ARRAY_SIZE(titan_gpio_table))
281 gpio_cfg = titan_gpio_table[gpio];
282 pin_sel_reg = gpio_cfg.reg - 1;
284 mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
286 /* Check the mux status */
287 if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
290 /* Set the pin sel value */
291 tmp = readl(pin_sel + pin_sel_reg);
292 tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
293 writel(tmp, pin_sel + pin_sel_reg);
298 /* Perform minimal Titan GPIO configuration */
299 static void titan_gpio_init(void)
303 for (i = 44; i < 48; i++) {
304 titan_gpio_pinsel(i);
305 ar7_gpio_enable_titan(i);
306 titan_gpio_direction_input(&titan_gpio_chip.chip, i);
310 int __init ar7_gpio_init(void)
313 struct ar7_gpio_chip *gpch;
316 if (!ar7_is_titan()) {
317 gpch = &ar7_gpio_chip;
320 gpch = &titan_gpio_chip;
324 gpch->regs = ioremap_nocache(AR7_REGS_GPIO, size);
326 printk(KERN_ERR "%s: failed to ioremap regs\n",
331 ret = gpiochip_add_data(&gpch->chip, gpch);
333 printk(KERN_ERR "%s: failed to add gpiochip\n",
337 printk(KERN_INFO "%s: registered %d GPIOs\n",
338 gpch->chip.label, gpch->chip.ngpio);