4 * Exposes all configurable internal clock sources to the clk framework.
7 * - Root source, usually 12MHz supplied by an external crystal
8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
11 * - 6 clock dividers with:
12 * * selectable source [one of the PLLs],
13 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14 * or [1 .. 256 in steps of 1] (Au1300),
15 * * can be enabled individually.
17 * - up to 6 "internal" (fixed) consumers which:
18 * * take either AUXPLL or one of the above 6 dividers as input,
19 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20 * * can be disabled separately.
23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24 * depends on board design and should be set by bootloader, read-only.
25 * - peripheral clock: half the rate of sysbus clock, source for a lot
26 * of peripheral blocks, read-only.
27 * - memory clock: clk rate to main memory chips, depends on board
28 * design and is read-only,
29 * - lrclk: the static bus clock signal for synchronous operation.
30 * depends on board design, must be set by bootloader,
31 * but may be required to correctly configure devices attached to
32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33 * later models it's called RCLK.
36 #include <linux/init.h>
38 #include <linux/clk-provider.h>
39 #include <linux/clkdev.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/types.h>
43 #include <asm/mach-au1x00/au1000.h>
45 /* Base clock: 12MHz is the default in all databooks, and I haven't
46 * found any board yet which uses a different rate.
48 #define ALCHEMY_ROOTCLK_RATE 12000000
51 * the internal sources which can be driven by the PLLs and dividers.
52 * Names taken from the databooks, refer to them for more information,
53 * especially which ones are share a clock line.
55 static const char * const alchemy_au1300_intclknames[] = {
56 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
60 static const char * const alchemy_au1200_intclknames[] = {
61 "lcd_intclk", NULL, NULL, NULL, "EXTCLK0", "EXTCLK1"
64 static const char * const alchemy_au1550_intclknames[] = {
65 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
69 static const char * const alchemy_au1100_intclknames[] = {
70 "usb_clk", "lcd_intclk", NULL, "i2s_clk", "EXTCLK0", "EXTCLK1"
73 static const char * const alchemy_au1500_intclknames[] = {
74 NULL, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
77 static const char * const alchemy_au1000_intclknames[] = {
78 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
82 /* aliases for a few on-chip sources which are either shared
83 * or have gone through name changes.
85 static struct clk_aliastable {
89 } alchemy_clk_aliases[] __initdata = {
90 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
91 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
92 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
93 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
94 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
95 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550 },
96 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550 },
97 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200 },
98 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200 },
99 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
100 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
101 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
102 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
107 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
109 /* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
110 static spinlock_t alchemy_clk_fg0_lock;
111 static spinlock_t alchemy_clk_fg1_lock;
112 static spinlock_t alchemy_clk_csrc_lock;
114 /* CPU Core clock *****************************************************/
116 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
117 unsigned long parent_rate)
122 * On early Au1000, sys_cpupll was write-only. Since these
123 * silicon versions of Au1000 are not sold, we don't bend
124 * over backwards trying to determine the frequency.
126 if (unlikely(au1xxx_cpu_has_pll_wo()))
129 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
130 if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
138 void __init alchemy_set_lpj(void)
140 preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE);
141 preset_lpj /= 2 * HZ;
144 static struct clk_ops alchemy_clkops_cpu = {
145 .recalc_rate = alchemy_clk_cpu_recalc,
148 static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
151 struct clk_init_data id;
154 h = kzalloc(sizeof(*h), GFP_KERNEL);
156 return ERR_PTR(-ENOMEM);
158 id.name = ALCHEMY_CPU_CLK;
159 id.parent_names = &parent_name;
161 id.flags = CLK_IS_BASIC;
162 id.ops = &alchemy_clkops_cpu;
165 return clk_register(NULL, h);
168 /* AUXPLLs ************************************************************/
170 struct alchemy_auxpll_clk {
172 unsigned long reg; /* au1300 has also AUXPLL2 */
173 int maxmult; /* max multiplier */
175 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
177 static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw,
178 unsigned long parent_rate)
180 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
182 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate;
185 static int alchemy_clk_aux_setr(struct clk_hw *hw,
187 unsigned long parent_rate)
189 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
190 unsigned long d = rate;
197 /* minimum is 84MHz, max is 756-1032 depending on variant */
198 if (((d < 7) && (d != 0)) || (d > a->maxmult))
201 alchemy_wrsys(d, a->reg);
205 static long alchemy_clk_aux_roundr(struct clk_hw *hw,
207 unsigned long *parent_rate)
209 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
212 if (!rate || !*parent_rate)
215 mult = rate / (*parent_rate);
217 if (mult && (mult < 7))
219 if (mult > a->maxmult)
222 return (*parent_rate) * mult;
225 static struct clk_ops alchemy_clkops_aux = {
226 .recalc_rate = alchemy_clk_aux_recalc,
227 .set_rate = alchemy_clk_aux_setr,
228 .round_rate = alchemy_clk_aux_roundr,
231 static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,
232 char *name, int maxmult,
235 struct clk_init_data id;
237 struct alchemy_auxpll_clk *a;
239 a = kzalloc(sizeof(*a), GFP_KERNEL);
241 return ERR_PTR(-ENOMEM);
244 id.parent_names = &parent_name;
246 id.flags = CLK_GET_RATE_NOCACHE;
247 id.ops = &alchemy_clkops_aux;
250 a->maxmult = maxmult;
253 c = clk_register(NULL, &a->hw);
255 clk_register_clkdev(c, name, NULL);
262 /* sysbus_clk *********************************************************/
264 static struct clk __init *alchemy_clk_setup_sysbus(const char *pn)
266 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;
269 c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,
272 clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL);
276 /* Peripheral Clock ***************************************************/
278 static struct clk __init *alchemy_clk_setup_periph(const char *pn)
280 /* Peripheral clock runs at half the rate of sysbus clk */
283 c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,
286 clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL);
290 /* mem clock **********************************************************/
292 static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
294 void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR);
300 case ALCHEMY_CPU_AU1550:
301 case ALCHEMY_CPU_AU1200:
302 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
303 div = (v & (1 << 15)) ? 1 : 2;
305 case ALCHEMY_CPU_AU1300:
306 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
307 div = (v & (1 << 31)) ? 1 : 2;
309 case ALCHEMY_CPU_AU1000:
310 case ALCHEMY_CPU_AU1500:
311 case ALCHEMY_CPU_AU1100:
317 c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,
320 clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL);
324 /* lrclk: external synchronous static bus clock ***********************/
326 static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
328 /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
329 * otherwise lrclk=pclk/4.
330 * All other variants: MEM_STCFG0[15:13] = divisor.
331 * L/RCLK = periph_clk / (divisor + 1)
332 * On Au1000, Au1500, Au1100 it's called LCLK,
333 * on later models it's called RCLK, but it's the same thing.
336 unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
339 case ALCHEMY_CPU_AU1000:
340 case ALCHEMY_CPU_AU1500:
341 v = 4 + ((v >> 11) & 1);
343 default: /* all other models */
344 v = ((v >> 13) & 7) + 1;
346 c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
349 clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL);
353 /* Clock dividers and muxes *******************************************/
355 /* data for fgen and csrc mux-dividers */
356 struct alchemy_fgcs_clk {
358 spinlock_t *reglock; /* register lock */
359 unsigned long reg; /* SYS_FREQCTRL0/1 */
360 int shift; /* offset in register */
361 int parent; /* parent before disable [Au1300] */
362 int isen; /* is it enabled? */
363 int *dt; /* dividertable for csrc */
365 #define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
367 static long alchemy_calc_div(unsigned long rate, unsigned long prate,
368 int scale, int maxdiv, unsigned long *rv)
373 if ((prate / div1) > rate)
376 if (scale == 2) { /* only div-by-multiple-of-2 possible */
378 div1++; /* stay <=prate */
381 div2 = (div1 / scale) - 1; /* value to write to register */
388 div1 = ((div2 + 1) * scale);
392 static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
393 unsigned long *best_parent_rate,
394 struct clk_hw **best_parent_clk,
395 int scale, int maxdiv)
397 struct clk *pc, *bpc, *free;
398 long tdv, tpr, pr, nr, br, bpr, diff, lastdiff;
407 /* look at the rates each enabled parent supplies and select
408 * the one that gets closest to but not over the requested rate.
410 for (j = 0; j < 7; j++) {
411 pc = clk_get_parent_by_index(hw->clk, j);
415 /* if this parent is currently unused, remember it.
416 * XXX: we would actually want clk_has_active_children()
417 * but this is a good-enough approximation for now.
419 if (!__clk_is_prepared(pc)) {
424 pr = clk_get_rate(pc);
428 /* what can hardware actually provide */
429 tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
435 if (diff < lastdiff) {
445 /* if we couldn't get the exact rate we wanted from the enabled
446 * parents, maybe we can tell an available disabled/inactive one
447 * to give us a rate we can divide down to the requested rate.
449 if (lastdiff && free) {
450 for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) {
454 pr = clk_round_rate(free, tpr);
456 tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
461 if (diff < lastdiff) {
472 *best_parent_rate = bpr;
473 *best_parent_clk = __clk_get_hw(bpc);
477 static int alchemy_clk_fgv1_en(struct clk_hw *hw)
479 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
480 unsigned long v, flags;
482 spin_lock_irqsave(c->reglock, flags);
483 v = alchemy_rdsys(c->reg);
484 v |= (1 << 1) << c->shift;
485 alchemy_wrsys(v, c->reg);
486 spin_unlock_irqrestore(c->reglock, flags);
491 static int alchemy_clk_fgv1_isen(struct clk_hw *hw)
493 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
494 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);
499 static void alchemy_clk_fgv1_dis(struct clk_hw *hw)
501 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
502 unsigned long v, flags;
504 spin_lock_irqsave(c->reglock, flags);
505 v = alchemy_rdsys(c->reg);
506 v &= ~((1 << 1) << c->shift);
507 alchemy_wrsys(v, c->reg);
508 spin_unlock_irqrestore(c->reglock, flags);
511 static int alchemy_clk_fgv1_setp(struct clk_hw *hw, u8 index)
513 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
514 unsigned long v, flags;
516 spin_lock_irqsave(c->reglock, flags);
517 v = alchemy_rdsys(c->reg);
519 v |= (1 << c->shift);
521 v &= ~(1 << c->shift);
522 alchemy_wrsys(v, c->reg);
523 spin_unlock_irqrestore(c->reglock, flags);
528 static u8 alchemy_clk_fgv1_getp(struct clk_hw *hw)
530 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
532 return (alchemy_rdsys(c->reg) >> c->shift) & 1;
535 static int alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate,
536 unsigned long parent_rate)
538 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
539 unsigned long div, v, flags, ret;
540 int sh = c->shift + 2;
542 if (!rate || !parent_rate || rate > (parent_rate / 2))
544 ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div);
545 spin_lock_irqsave(c->reglock, flags);
546 v = alchemy_rdsys(c->reg);
549 alchemy_wrsys(v, c->reg);
550 spin_unlock_irqrestore(c->reglock, flags);
555 static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
556 unsigned long parent_rate)
558 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
559 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);
561 v = ((v & 0xff) + 1) * 2;
562 return parent_rate / v;
565 static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
566 unsigned long *best_parent_rate,
567 struct clk_hw **best_parent_clk)
569 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
570 best_parent_clk, 2, 512);
573 /* Au1000, Au1100, Au15x0, Au12x0 */
574 static struct clk_ops alchemy_clkops_fgenv1 = {
575 .recalc_rate = alchemy_clk_fgv1_recalc,
576 .determine_rate = alchemy_clk_fgv1_detr,
577 .set_rate = alchemy_clk_fgv1_setr,
578 .set_parent = alchemy_clk_fgv1_setp,
579 .get_parent = alchemy_clk_fgv1_getp,
580 .enable = alchemy_clk_fgv1_en,
581 .disable = alchemy_clk_fgv1_dis,
582 .is_enabled = alchemy_clk_fgv1_isen,
585 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c)
587 unsigned long v = alchemy_rdsys(c->reg);
589 v &= ~(3 << c->shift);
590 v |= (c->parent & 3) << c->shift;
591 alchemy_wrsys(v, c->reg);
595 static int alchemy_clk_fgv2_en(struct clk_hw *hw)
597 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
600 /* enable by setting the previous parent clock */
601 spin_lock_irqsave(c->reglock, flags);
602 __alchemy_clk_fgv2_en(c);
603 spin_unlock_irqrestore(c->reglock, flags);
608 static int alchemy_clk_fgv2_isen(struct clk_hw *hw)
610 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
612 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0;
615 static void alchemy_clk_fgv2_dis(struct clk_hw *hw)
617 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
618 unsigned long v, flags;
620 spin_lock_irqsave(c->reglock, flags);
621 v = alchemy_rdsys(c->reg);
622 v &= ~(3 << c->shift); /* set input mux to "disabled" state */
623 alchemy_wrsys(v, c->reg);
625 spin_unlock_irqrestore(c->reglock, flags);
628 static int alchemy_clk_fgv2_setp(struct clk_hw *hw, u8 index)
630 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
633 spin_lock_irqsave(c->reglock, flags);
634 c->parent = index + 1; /* value to write to register */
636 __alchemy_clk_fgv2_en(c);
637 spin_unlock_irqrestore(c->reglock, flags);
642 static u8 alchemy_clk_fgv2_getp(struct clk_hw *hw)
644 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
645 unsigned long flags, v;
647 spin_lock_irqsave(c->reglock, flags);
649 spin_unlock_irqrestore(c->reglock, flags);
653 /* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
654 * dividers behave exactly as on previous models (dividers are multiples
655 * of 2); with the bit set, dividers are multiples of 1, halving their
656 * range, but making them also much more flexible.
658 static int alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate,
659 unsigned long parent_rate)
661 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
662 int sh = c->shift + 2;
663 unsigned long div, v, flags, ret;
665 if (!rate || !parent_rate || rate > parent_rate)
668 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */
669 ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,
670 v ? 256 : 512, &div);
672 spin_lock_irqsave(c->reglock, flags);
673 v = alchemy_rdsys(c->reg);
675 v |= (div & 0xff) << sh;
676 alchemy_wrsys(v, c->reg);
677 spin_unlock_irqrestore(c->reglock, flags);
682 static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
683 unsigned long parent_rate)
685 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
686 int sh = c->shift + 2;
689 v = alchemy_rdsys(c->reg);
690 t = parent_rate / (((v >> sh) & 0xff) + 1);
691 if ((v & (1 << 30)) == 0) /* test scale bit */
697 static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
698 unsigned long *best_parent_rate,
699 struct clk_hw **best_parent_clk)
701 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
704 if (alchemy_rdsys(c->reg) & (1 << 30)) {
712 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
713 best_parent_clk, scale, maxdiv);
716 /* Au1300 larger input mux, no separate disable bit, flexible divider */
717 static struct clk_ops alchemy_clkops_fgenv2 = {
718 .recalc_rate = alchemy_clk_fgv2_recalc,
719 .determine_rate = alchemy_clk_fgv2_detr,
720 .set_rate = alchemy_clk_fgv2_setr,
721 .set_parent = alchemy_clk_fgv2_setp,
722 .get_parent = alchemy_clk_fgv2_getp,
723 .enable = alchemy_clk_fgv2_en,
724 .disable = alchemy_clk_fgv2_dis,
725 .is_enabled = alchemy_clk_fgv2_isen,
728 static const char * const alchemy_clk_fgv1_parents[] = {
729 ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
732 static const char * const alchemy_clk_fgv2_parents[] = {
733 ALCHEMY_AUXPLL2_CLK, ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
736 static const char * const alchemy_clk_fgen_names[] = {
737 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
738 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK };
740 static int __init alchemy_clk_init_fgens(int ctype)
743 struct clk_init_data id;
744 struct alchemy_fgcs_clk *a;
749 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
750 id.ops = &alchemy_clkops_fgenv1;
751 id.parent_names = (const char **)alchemy_clk_fgv1_parents;
754 case ALCHEMY_CPU_AU1300:
755 id.ops = &alchemy_clkops_fgenv2;
756 id.parent_names = (const char **)alchemy_clk_fgv2_parents;
762 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
764 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
768 spin_lock_init(&alchemy_clk_fg0_lock);
769 spin_lock_init(&alchemy_clk_fg1_lock);
771 for (i = 0; i < 6; i++) {
772 id.name = alchemy_clk_fgen_names[i];
773 a->shift = 10 * (i < 3 ? i : i - 3);
775 a->reg = AU1000_SYS_FREQCTRL1;
776 a->reglock = &alchemy_clk_fg1_lock;
778 a->reg = AU1000_SYS_FREQCTRL0;
779 a->reglock = &alchemy_clk_fg0_lock;
782 /* default to first parent if bootloader has set
783 * the mux to disabled state.
785 if (ctype == ALCHEMY_CPU_AU1300) {
786 v = alchemy_rdsys(a->reg);
787 a->parent = (v >> a->shift) & 3;
796 c = clk_register(NULL, &a->hw);
800 clk_register_clkdev(c, id.name, NULL);
807 /* internal sources muxes *********************************************/
809 static int alchemy_clk_csrc_isen(struct clk_hw *hw)
811 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
812 unsigned long v = alchemy_rdsys(c->reg);
814 return (((v >> c->shift) >> 2) & 7) != 0;
817 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c)
819 unsigned long v = alchemy_rdsys(c->reg);
821 v &= ~((7 << 2) << c->shift);
822 v |= ((c->parent & 7) << 2) << c->shift;
823 alchemy_wrsys(v, c->reg);
827 static int alchemy_clk_csrc_en(struct clk_hw *hw)
829 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
832 /* enable by setting the previous parent clock */
833 spin_lock_irqsave(c->reglock, flags);
834 __alchemy_clk_csrc_en(c);
835 spin_unlock_irqrestore(c->reglock, flags);
840 static void alchemy_clk_csrc_dis(struct clk_hw *hw)
842 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
843 unsigned long v, flags;
845 spin_lock_irqsave(c->reglock, flags);
846 v = alchemy_rdsys(c->reg);
847 v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */
848 alchemy_wrsys(v, c->reg);
850 spin_unlock_irqrestore(c->reglock, flags);
853 static int alchemy_clk_csrc_setp(struct clk_hw *hw, u8 index)
855 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
858 spin_lock_irqsave(c->reglock, flags);
859 c->parent = index + 1; /* value to write to register */
861 __alchemy_clk_csrc_en(c);
862 spin_unlock_irqrestore(c->reglock, flags);
867 static u8 alchemy_clk_csrc_getp(struct clk_hw *hw)
869 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
871 return c->parent - 1;
874 static unsigned long alchemy_clk_csrc_recalc(struct clk_hw *hw,
875 unsigned long parent_rate)
877 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
878 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;
880 return parent_rate / c->dt[v];
883 static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
884 unsigned long parent_rate)
886 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
887 unsigned long d, v, flags;
890 if (!rate || !parent_rate || rate > parent_rate)
893 d = (parent_rate + (rate / 2)) / rate;
896 if ((d == 3) && (c->dt[2] != 3))
899 for (i = 0; i < 4; i++)
904 return -EINVAL; /* oops */
906 spin_lock_irqsave(c->reglock, flags);
907 v = alchemy_rdsys(c->reg);
908 v &= ~(3 << c->shift);
909 v |= (i & 3) << c->shift;
910 alchemy_wrsys(v, c->reg);
911 spin_unlock_irqrestore(c->reglock, flags);
916 static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
917 unsigned long *best_parent_rate,
918 struct clk_hw **best_parent_clk)
920 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
921 int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
923 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
924 best_parent_clk, scale, 4);
927 static struct clk_ops alchemy_clkops_csrc = {
928 .recalc_rate = alchemy_clk_csrc_recalc,
929 .determine_rate = alchemy_clk_csrc_detr,
930 .set_rate = alchemy_clk_csrc_setr,
931 .set_parent = alchemy_clk_csrc_setp,
932 .get_parent = alchemy_clk_csrc_getp,
933 .enable = alchemy_clk_csrc_en,
934 .disable = alchemy_clk_csrc_dis,
935 .is_enabled = alchemy_clk_csrc_isen,
938 static const char * const alchemy_clk_csrc_parents[] = {
939 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK,
940 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
941 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK
945 static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 }; /* rest */
946 static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */
948 static int __init alchemy_clk_setup_imux(int ctype)
950 struct alchemy_fgcs_clk *a;
951 const char * const *names;
952 struct clk_init_data id;
957 id.ops = &alchemy_clkops_csrc;
958 id.parent_names = (const char **)alchemy_clk_csrc_parents;
960 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
962 dt = alchemy_csrc_dt1;
964 case ALCHEMY_CPU_AU1000:
965 names = alchemy_au1000_intclknames;
967 case ALCHEMY_CPU_AU1500:
968 names = alchemy_au1500_intclknames;
970 case ALCHEMY_CPU_AU1100:
971 names = alchemy_au1100_intclknames;
973 case ALCHEMY_CPU_AU1550:
974 names = alchemy_au1550_intclknames;
976 case ALCHEMY_CPU_AU1200:
977 names = alchemy_au1200_intclknames;
979 case ALCHEMY_CPU_AU1300:
980 dt = alchemy_csrc_dt2;
981 names = alchemy_au1300_intclknames;
987 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
991 spin_lock_init(&alchemy_clk_csrc_lock);
994 for (i = 0; i < 6; i++) {
1000 a->reg = AU1000_SYS_CLKSRC;
1001 a->reglock = &alchemy_clk_csrc_lock;
1004 /* default to first parent clock if mux is initially
1005 * set to disabled state.
1007 v = alchemy_rdsys(a->reg);
1008 a->parent = ((v >> a->shift) >> 2) & 7;
1016 c = clk_register(NULL, &a->hw);
1020 clk_register_clkdev(c, id.name, NULL);
1029 /**********************************************************************/
1038 static int __init alchemy_clk_init(void)
1040 int ctype = alchemy_get_cputype(), ret, i;
1041 struct clk_aliastable *t = alchemy_clk_aliases;
1044 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1045 c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL,
1047 ALCHEMY_ROOTCLK_RATE);
1050 /* CPU core clock */
1051 c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype);
1054 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1055 i = (ctype == ALCHEMY_CPU_AU1300) ? 84 : 63;
1056 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK,
1057 i, AU1000_SYS_AUXPLL);
1060 if (ctype == ALCHEMY_CPU_AU1300) {
1061 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK,
1062 ALCHEMY_AUXPLL2_CLK, i,
1063 AU1300_SYS_AUXPLL2);
1067 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1068 c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK);
1071 /* peripheral clock: runs at half rate of sysbus clk */
1072 c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK);
1075 /* SDR/DDR memory clock */
1076 c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype);
1079 /* L/RCLK: external static bus clock for synchronous mode */
1080 c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
1083 /* Frequency dividers 0-5 */
1084 ret = alchemy_clk_init_fgens(ctype);
1090 /* diving muxes for internal sources */
1091 ret = alchemy_clk_setup_imux(ctype);
1097 /* set up aliases drivers might look for */
1099 if (t->cputype == ctype)
1100 clk_add_alias(t->alias, NULL, t->base, NULL);
1104 pr_info("Alchemy clocktree installed\n");
1110 postcore_initcall(alchemy_clk_init);