1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CPU_CACHE_ALIASING
8 select ARCH_HAS_CPU_FINALIZE_INIT
9 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
10 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
11 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
14 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
15 select ARCH_HAS_STRNCPY_FROM_USER
16 select ARCH_HAS_STRNLEN_USER
17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
19 select ARCH_HAS_GCOV_PROFILE_ALL
20 select ARCH_KEEP_MEMBLOCK
21 select ARCH_USE_BUILTIN_BSWAP
22 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
23 select ARCH_USE_MEMTEST
24 select ARCH_USE_QUEUED_RWLOCKS
25 select ARCH_USE_QUEUED_SPINLOCKS
26 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
27 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
28 select ARCH_WANT_IPC_PARSE_VERSION
29 select ARCH_WANT_LD_ORPHAN_WARN
30 select BUILDTIME_TABLE_SORT
31 select CLONE_BACKWARDS
32 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
33 select CPU_PM if CPU_IDLE
34 select GENERIC_ATOMIC64 if !64BIT
35 select GENERIC_CMOS_UPDATE
36 select GENERIC_CPU_AUTOPROBE
37 select GENERIC_GETTIMEOFDAY
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_ISA_DMA if EISA
42 select GENERIC_LIB_ASHLDI3
43 select GENERIC_LIB_ASHRDI3
44 select GENERIC_LIB_CMPDI2
45 select GENERIC_LIB_LSHRDI3
46 select GENERIC_LIB_UCMPDI2
47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
48 select GENERIC_SMP_IDLE_THREAD
49 select GENERIC_IDLE_POLL_SETUP
50 select GENERIC_TIME_VSYSCALL
51 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
52 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
53 select HAVE_ARCH_COMPILER_H
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
56 select HAVE_ARCH_MMAP_RND_BITS if MMU
57 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
58 select HAVE_ARCH_SECCOMP_FILTER
59 select HAVE_ARCH_TRACEHOOK
60 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
61 select HAVE_ASM_MODVERSIONS
62 select HAVE_CONTEXT_TRACKING_USER
64 select HAVE_C_RECORDMCOUNT
65 select HAVE_DEBUG_KMEMLEAK
66 select HAVE_DEBUG_STACKOVERFLOW
67 select HAVE_DMA_CONTIGUOUS
68 select HAVE_DYNAMIC_FTRACE
69 select HAVE_EBPF_JIT if !CPU_MICROMIPS
70 select HAVE_EXIT_THREAD
72 select HAVE_FTRACE_MCOUNT_RECORD
73 select HAVE_FUNCTION_GRAPH_TRACER
74 select HAVE_FUNCTION_TRACER
75 select HAVE_GCC_PLUGINS
76 select HAVE_GENERIC_VDSO
77 select HAVE_IOREMAP_PROT
78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
79 select HAVE_IRQ_TIME_ACCOUNTING
81 select HAVE_KRETPROBES
82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
83 select HAVE_MOD_ARCH_SPECIFIC
85 select HAVE_PAGE_SIZE_4KB if !CPU_LOONGSON2EF && !CPU_LOONGSON64
86 select HAVE_PAGE_SIZE_16KB if !CPU_R3000
87 select HAVE_PAGE_SIZE_64KB if !CPU_R3000
88 select HAVE_PERF_EVENTS
90 select HAVE_PERF_USER_STACK_DUMP
91 select HAVE_REGS_AND_STACK_ACCESS_API
93 select HAVE_SPARSE_SYSCALL_NR
94 select HAVE_STACKPROTECTOR
95 select HAVE_SYSCALL_TRACEPOINTS
96 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
97 select IRQ_FORCED_THREADING
99 select LOCK_MM_AND_FIND_VMA
100 select MODULES_USE_ELF_REL if MODULES
101 select MODULES_USE_ELF_RELA if MODULES && 64BIT
102 select PERF_USE_VMALLOC
103 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
105 select SYSCTL_EXCEPTION_TRACE
106 select TRACE_IRQFLAGS_SUPPORT
107 select ARCH_HAS_ELFCORE_COMPAT
108 select HAVE_ARCH_KCSAN if 64BIT
110 config MIPS_FIXUP_BIGPHYS_ADDR
118 select SYS_SUPPORTS_32BIT_KERNEL
119 select SYS_SUPPORTS_LITTLE_ENDIAN
120 select SYS_SUPPORTS_ZBOOT
121 select DMA_NONCOHERENT
126 select GENERIC_IRQ_CHIP
127 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
129 select CPU_SUPPORTS_CPUFREQ
130 select MIPS_EXTERNAL_TIMER
132 menu "Machine selection"
136 default MIPS_GENERIC_KERNEL
138 config MIPS_GENERIC_KERNEL
139 bool "Generic board-agnostic MIPS kernel"
144 select CLKSRC_MIPS_GIC
146 select CPU_MIPSR2_IRQ_EI
147 select CPU_MIPSR2_IRQ_VI
149 select DMA_NONCOHERENT
152 select MIPS_AUTO_PFN_OFFSET
153 select MIPS_CPU_SCACHE
155 select MIPS_L1_CACHE_SHIFT_7
156 select NO_EXCEPT_FILL
157 select PCI_DRIVERS_GENERIC
160 select SYS_HAS_CPU_MIPS32_R1
161 select SYS_HAS_CPU_MIPS32_R2
162 select SYS_HAS_CPU_MIPS32_R5
163 select SYS_HAS_CPU_MIPS32_R6
164 select SYS_HAS_CPU_MIPS64_R1
165 select SYS_HAS_CPU_MIPS64_R2
166 select SYS_HAS_CPU_MIPS64_R5
167 select SYS_HAS_CPU_MIPS64_R6
168 select SYS_SUPPORTS_32BIT_KERNEL
169 select SYS_SUPPORTS_64BIT_KERNEL
170 select SYS_SUPPORTS_BIG_ENDIAN
171 select SYS_SUPPORTS_HIGHMEM
172 select SYS_SUPPORTS_LITTLE_ENDIAN
173 select SYS_SUPPORTS_MICROMIPS
174 select SYS_SUPPORTS_MIPS16
175 select SYS_SUPPORTS_MIPS_CPS
176 select SYS_SUPPORTS_MULTITHREADING
177 select SYS_SUPPORTS_RELOCATABLE
178 select SYS_SUPPORTS_SMARTMIPS
179 select SYS_SUPPORTS_ZBOOT
181 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
182 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
183 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
184 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
185 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
186 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
189 Select this to build a kernel which aims to support multiple boards,
190 generally using a flattened device tree passed from the bootloader
191 using the boot protocol defined in the UHI (Unified Hosting
192 Interface) specification.
195 bool "Alchemy processor based machines"
196 select PHYS_ADDR_T_64BIT
200 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
201 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
202 select SYS_HAS_CPU_MIPS32_R1
203 select SYS_SUPPORTS_32BIT_KERNEL
204 select SYS_SUPPORTS_APM_EMULATION
206 select SYS_SUPPORTS_ZBOOT
210 bool "Atheros AR231x/AR531x SoC support"
213 select DMA_NONCOHERENT
216 select SYS_HAS_CPU_MIPS32_R1
217 select SYS_SUPPORTS_BIG_ENDIAN
218 select SYS_SUPPORTS_32BIT_KERNEL
219 select SYS_HAS_EARLY_PRINTK
221 Support for Atheros AR231x and Atheros AR531x based boards
224 bool "Atheros AR71XX/AR724X/AR913X based boards"
225 select ARCH_HAS_RESET_CONTROLLER
229 select DMA_NONCOHERENT
234 select SYS_HAS_CPU_MIPS32_R2
235 select SYS_HAS_EARLY_PRINTK
236 select SYS_SUPPORTS_32BIT_KERNEL
237 select SYS_SUPPORTS_BIG_ENDIAN
238 select SYS_SUPPORTS_MIPS16
239 select SYS_SUPPORTS_ZBOOT_UART_PROM
241 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
243 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
246 bool "Broadcom Generic BMIPS kernel"
247 select ARCH_HAS_RESET_CONTROLLER
248 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
250 select NO_EXCEPT_FILL
256 select BCM6345_L1_IRQ
257 select BCM7038_L1_IRQ
258 select BCM7120_L2_IRQ
259 select BRCMSTB_L2_IRQ
261 select DMA_NONCOHERENT
262 select SYS_SUPPORTS_32BIT_KERNEL
263 select SYS_SUPPORTS_LITTLE_ENDIAN
264 select SYS_SUPPORTS_BIG_ENDIAN
265 select SYS_SUPPORTS_HIGHMEM
266 select SYS_HAS_CPU_BMIPS32_3300
267 select SYS_HAS_CPU_BMIPS4350
268 select SYS_HAS_CPU_BMIPS4380
269 select SYS_HAS_CPU_BMIPS5000
271 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
272 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
273 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
274 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
275 select HARDIRQS_SW_RESEND
277 select PCI_DRIVERS_GENERIC
280 Build a generic DT-based kernel image that boots on select
281 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
282 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
283 must be set appropriately for your board.
286 bool "Broadcom BCM47XX based boards"
290 select DMA_NONCOHERENT
293 select SYS_HAS_CPU_MIPS32_R1
294 select NO_EXCEPT_FILL
295 select SYS_SUPPORTS_32BIT_KERNEL
296 select SYS_SUPPORTS_LITTLE_ENDIAN
297 select SYS_SUPPORTS_MIPS16
298 select SYS_SUPPORTS_ZBOOT
299 select SYS_HAS_EARLY_PRINTK
300 select USE_GENERIC_EARLY_PRINTK_8250
302 select LEDS_GPIO_REGISTER
305 select BCM47XX_SSB if !BCM47XX_BCMA
307 Support for BCM47XX based boards
310 bool "Broadcom BCM63XX based boards"
315 select DMA_NONCOHERENT
317 select SYS_SUPPORTS_32BIT_KERNEL
318 select SYS_SUPPORTS_BIG_ENDIAN
319 select SYS_HAS_EARLY_PRINTK
320 select SYS_HAS_CPU_BMIPS32_3300
321 select SYS_HAS_CPU_BMIPS4350
322 select SYS_HAS_CPU_BMIPS4380
325 select MIPS_L1_CACHE_SHIFT_4
326 select HAVE_LEGACY_CLK
328 Support for BCM63XX based boards
335 select DMA_NONCOHERENT
341 select PCI_GT64XXX_PCI0
342 select SYS_HAS_CPU_NEVADA
343 select SYS_HAS_EARLY_PRINTK
344 select SYS_SUPPORTS_32BIT_KERNEL
345 select SYS_SUPPORTS_64BIT_KERNEL
346 select SYS_SUPPORTS_LITTLE_ENDIAN
347 select USE_GENERIC_EARLY_PRINTK_8250
349 config MACH_DECSTATION
353 select CEVT_R4K if CPU_R4X00
355 select CSRC_R4K if CPU_R4X00
356 select CPU_DADDI_WORKAROUNDS if 64BIT
357 select CPU_R4000_WORKAROUNDS if 64BIT
358 select CPU_R4400_WORKAROUNDS if 64BIT
359 select DMA_NONCOHERENT
362 select SYS_HAS_CPU_R3000
363 select SYS_HAS_CPU_R4X00
364 select SYS_SUPPORTS_32BIT_KERNEL
365 select SYS_SUPPORTS_64BIT_KERNEL
366 select SYS_SUPPORTS_LITTLE_ENDIAN
367 select SYS_SUPPORTS_128HZ
368 select SYS_SUPPORTS_256HZ
369 select SYS_SUPPORTS_1024HZ
370 select MIPS_L1_CACHE_SHIFT_4
372 This enables support for DEC's MIPS based workstations. For details
373 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
374 DECstation porting pages on <http://decstation.unix-ag.org/>.
376 If you have one of the following DECstation Models you definitely
377 want to choose R4xx0 for the CPU Type:
384 otherwise choose R3000.
387 bool "Jazz family of machines"
390 select ARCH_MIGHT_HAVE_PC_PARPORT
391 select ARCH_MIGHT_HAVE_PC_SERIO
395 select ARCH_MAY_HAVE_PC_FDC
398 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
399 select GENERIC_ISA_DMA
400 select HAVE_PCSPKR_PLATFORM
405 select SYS_HAS_CPU_R4X00
406 select SYS_SUPPORTS_32BIT_KERNEL
407 select SYS_SUPPORTS_64BIT_KERNEL
408 select SYS_SUPPORTS_100HZ
409 select SYS_SUPPORTS_LITTLE_ENDIAN
411 This a family of machines based on the MIPS R4030 chipset which was
412 used by several vendors to build RISC/os and Windows NT workstations.
413 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
414 Olivetti M700-10 workstations.
416 config MACH_INGENIC_SOC
417 bool "Ingenic SoC based machines"
420 select SYS_SUPPORTS_ZBOOT_UART16550
421 select CPU_SUPPORTS_CPUFREQ
422 select MIPS_EXTERNAL_TIMER
425 bool "Lantiq based platforms"
426 select DMA_NONCOHERENT
430 select NO_EXCEPT_FILL
431 select SYS_HAS_CPU_MIPS32_R1
432 select SYS_HAS_CPU_MIPS32_R2
433 select SYS_SUPPORTS_BIG_ENDIAN
434 select SYS_SUPPORTS_32BIT_KERNEL
435 select SYS_SUPPORTS_MIPS16
436 select SYS_SUPPORTS_MULTITHREADING
437 select SYS_SUPPORTS_VPE_LOADER
438 select SYS_HAS_EARLY_PRINTK
442 select HAVE_LEGACY_CLK
445 select PINCTRL_LANTIQ
446 select ARCH_HAS_RESET_CONTROLLER
447 select RESET_CONTROLLER
449 config MACH_LOONGSON32
450 bool "Loongson 32-bit family of machines"
451 select SYS_SUPPORTS_ZBOOT
453 This enables support for the Loongson-1 family of machines.
455 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
456 the Institute of Computing Technology (ICT), Chinese Academy of
459 config MACH_LOONGSON2EF
460 bool "Loongson-2E/F family of machines"
461 select SYS_SUPPORTS_ZBOOT
463 This enables the support of early Loongson-2E/F family of machines.
465 config MACH_LOONGSON64
466 bool "Loongson 64-bit family of machines"
467 select ARCH_DMA_DEFAULT_COHERENT
468 select ARCH_SPARSEMEM_ENABLE
469 select ARCH_MIGHT_HAVE_PC_PARPORT
470 select ARCH_MIGHT_HAVE_PC_SERIO
471 select GENERIC_ISA_DMA_SUPPORT_BROKEN
480 select NO_EXCEPT_FILL
481 select NR_CPUS_DEFAULT_64
482 select USE_GENERIC_EARLY_PRINTK_8250
483 select PCI_DRIVERS_GENERIC
484 select SYS_HAS_CPU_LOONGSON64
485 select SYS_HAS_EARLY_PRINTK
486 select SYS_SUPPORTS_SMP
487 select SYS_SUPPORTS_HOTPLUG_CPU
488 select SYS_SUPPORTS_NUMA
489 select SYS_SUPPORTS_64BIT_KERNEL
490 select SYS_SUPPORTS_HIGHMEM
491 select SYS_SUPPORTS_LITTLE_ENDIAN
492 select SYS_SUPPORTS_ZBOOT
493 select SYS_SUPPORTS_RELOCATABLE
498 select PCI_HOST_GENERIC
499 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
501 This enables the support of Loongson-2/3 family of machines.
503 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
504 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
505 and Loongson-2F which will be removed), developed by the Institute
506 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
509 bool "MIPS Malta board"
510 select ARCH_MAY_HAVE_PC_FDC
511 select ARCH_MIGHT_HAVE_PC_PARPORT
512 select ARCH_MIGHT_HAVE_PC_SERIO
517 select CLKSRC_MIPS_GIC
520 select DMA_NONCOHERENT
521 select GENERIC_ISA_DMA
522 select HAVE_PCSPKR_PLATFORM
528 select MIPS_CPU_SCACHE
530 select MIPS_L1_CACHE_SHIFT_6
532 select PCI_GT64XXX_PCI0
535 select SYS_HAS_CPU_MIPS32_R1
536 select SYS_HAS_CPU_MIPS32_R2
537 select SYS_HAS_CPU_MIPS32_R3_5
538 select SYS_HAS_CPU_MIPS32_R5
539 select SYS_HAS_CPU_MIPS32_R6
540 select SYS_HAS_CPU_MIPS64_R1
541 select SYS_HAS_CPU_MIPS64_R2
542 select SYS_HAS_CPU_MIPS64_R6
543 select SYS_HAS_CPU_NEVADA
544 select SYS_HAS_CPU_RM7000
545 select SYS_SUPPORTS_32BIT_KERNEL
546 select SYS_SUPPORTS_64BIT_KERNEL
547 select SYS_SUPPORTS_BIG_ENDIAN
548 select SYS_SUPPORTS_HIGHMEM
549 select SYS_SUPPORTS_LITTLE_ENDIAN
550 select SYS_SUPPORTS_MICROMIPS
551 select SYS_SUPPORTS_MIPS16
552 select SYS_SUPPORTS_MIPS_CPS
553 select SYS_SUPPORTS_MULTITHREADING
554 select SYS_SUPPORTS_RELOCATABLE
555 select SYS_SUPPORTS_SMARTMIPS
556 select SYS_SUPPORTS_VPE_LOADER
557 select SYS_SUPPORTS_ZBOOT
559 select WAR_ICACHE_REFILLS
560 select ZONE_DMA32 if 64BIT
562 This enables support for the MIPS Technologies Malta evaluation
566 bool "Microchip PIC32 Family"
568 This enables support for the Microchip PIC32 family of platforms.
570 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
573 config MACH_NINTENDO64
574 bool "Nintendo 64 console"
577 select SYS_HAS_CPU_R4300
578 select SYS_SUPPORTS_BIG_ENDIAN
579 select SYS_SUPPORTS_ZBOOT
580 select SYS_SUPPORTS_32BIT_KERNEL
581 select SYS_SUPPORTS_64BIT_KERNEL
582 select DMA_NONCOHERENT
586 bool "Ralink based machines"
591 select DMA_NONCOHERENT
594 select SYS_HAS_CPU_MIPS32_R2
595 select SYS_SUPPORTS_32BIT_KERNEL
596 select SYS_SUPPORTS_LITTLE_ENDIAN
597 select SYS_SUPPORTS_MIPS16
598 select SYS_SUPPORTS_ZBOOT
599 select SYS_HAS_EARLY_PRINTK
600 select ARCH_HAS_RESET_CONTROLLER
601 select RESET_CONTROLLER
603 config MACH_REALTEK_RTL
604 bool "Realtek RTL838x/RTL839x based machines"
606 select DMA_NONCOHERENT
610 select SYS_HAS_CPU_MIPS32_R1
611 select SYS_HAS_CPU_MIPS32_R2
612 select SYS_SUPPORTS_BIG_ENDIAN
613 select SYS_SUPPORTS_32BIT_KERNEL
614 select SYS_SUPPORTS_MIPS16
615 select SYS_SUPPORTS_MULTITHREADING
616 select SYS_SUPPORTS_VPE_LOADER
622 bool "SGI IP22 (Indy/Indigo2)"
627 select ARCH_MIGHT_HAVE_PC_SERIO
631 select DEFAULT_SGI_PARTITION
632 select DMA_NONCOHERENT
636 select IP22_CPU_SCACHE
638 select GENERIC_ISA_DMA_SUPPORT_BROKEN
640 select SGI_HAS_INDYDOG
646 select SYS_HAS_CPU_R4X00
647 select SYS_HAS_CPU_R5000
648 select SYS_HAS_EARLY_PRINTK
649 select SYS_SUPPORTS_32BIT_KERNEL
650 select SYS_SUPPORTS_64BIT_KERNEL
651 select SYS_SUPPORTS_BIG_ENDIAN
652 select WAR_R4600_V1_INDEX_ICACHEOP
653 select WAR_R4600_V1_HIT_CACHEOP
654 select WAR_R4600_V2_HIT_CACHEOP
655 select MIPS_L1_CACHE_SHIFT_7
657 This are the SGI Indy, Challenge S and Indigo2, as well as certain
658 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
659 that runs on these, say Y here.
662 bool "SGI IP27 (Origin200/2000)"
663 select ARCH_HAS_PHYS_TO_DMA
664 select ARCH_SPARSEMEM_ENABLE
667 select ARC_CMDLINE_ONLY
669 select DEFAULT_SGI_PARTITION
671 select SYS_HAS_EARLY_PRINTK
674 select IRQ_DOMAIN_HIERARCHY
675 select NR_CPUS_DEFAULT_64
676 select PCI_DRIVERS_GENERIC
677 select PCI_XTALK_BRIDGE
678 select SYS_HAS_CPU_R10000
679 select SYS_SUPPORTS_64BIT_KERNEL
680 select SYS_SUPPORTS_BIG_ENDIAN
681 select SYS_SUPPORTS_NUMA
682 select SYS_SUPPORTS_SMP
683 select WAR_R10000_LLSC
684 select MIPS_L1_CACHE_SHIFT_7
686 select HAVE_ARCH_NODEDATA_EXTENSION
688 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
689 workstations. To compile a Linux kernel that runs on these, say Y
693 bool "SGI IP28 (Indigo2 R10k)"
698 select ARCH_MIGHT_HAVE_PC_SERIO
702 select DEFAULT_SGI_PARTITION
703 select DMA_NONCOHERENT
704 select GENERIC_ISA_DMA_SUPPORT_BROKEN
710 select SGI_HAS_INDYDOG
716 select SYS_HAS_CPU_R10000
717 select SYS_HAS_EARLY_PRINTK
718 select SYS_SUPPORTS_64BIT_KERNEL
719 select SYS_SUPPORTS_BIG_ENDIAN
720 select WAR_R10000_LLSC
721 select MIPS_L1_CACHE_SHIFT_7
723 This is the SGI Indigo2 with R10000 processor. To compile a Linux
724 kernel that runs on these, say Y here.
727 bool "SGI IP30 (Octane/Octane2)"
728 select ARCH_HAS_PHYS_TO_DMA
735 select SYNC_R4K if SMP
739 select IRQ_DOMAIN_HIERARCHY
740 select PCI_DRIVERS_GENERIC
741 select PCI_XTALK_BRIDGE
742 select SYS_HAS_EARLY_PRINTK
743 select SYS_HAS_CPU_R10000
744 select SYS_SUPPORTS_64BIT_KERNEL
745 select SYS_SUPPORTS_BIG_ENDIAN
746 select SYS_SUPPORTS_SMP
747 select WAR_R10000_LLSC
748 select MIPS_L1_CACHE_SHIFT_7
751 These are the SGI Octane and Octane2 graphics workstations. To
752 compile a Linux kernel that runs on these, say Y here.
758 select ARCH_HAS_PHYS_TO_DMA
764 select DMA_NONCOHERENT
767 select R5000_CPU_SCACHE
768 select RM7000_CPU_SCACHE
769 select SYS_HAS_CPU_R5000
770 select SYS_HAS_CPU_R10000 if BROKEN
771 select SYS_HAS_CPU_RM7000
772 select SYS_HAS_CPU_NEVADA
773 select SYS_SUPPORTS_64BIT_KERNEL
774 select SYS_SUPPORTS_BIG_ENDIAN
775 select WAR_ICACHE_REFILLS
777 If you want this kernel to run on SGI O2 workstation, say Y here.
780 bool "Sibyte BCM91125C-CRhone"
782 select SIBYTE_BCM1125
784 select SYS_HAS_CPU_SB1
785 select SYS_SUPPORTS_BIG_ENDIAN
786 select SYS_SUPPORTS_HIGHMEM
787 select SYS_SUPPORTS_LITTLE_ENDIAN
790 bool "Sibyte BCM91125E-Rhone"
794 select SYS_HAS_CPU_SB1
795 select SYS_SUPPORTS_BIG_ENDIAN
796 select SYS_SUPPORTS_LITTLE_ENDIAN
799 bool "Sibyte BCM91250A-SWARM"
801 select HAVE_PATA_PLATFORM
804 select SYS_HAS_CPU_SB1
805 select SYS_SUPPORTS_BIG_ENDIAN
806 select SYS_SUPPORTS_HIGHMEM
807 select SYS_SUPPORTS_LITTLE_ENDIAN
808 select ZONE_DMA32 if 64BIT
809 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
811 config SIBYTE_LITTLESUR
812 bool "Sibyte BCM91250C2-LittleSur"
814 select HAVE_PATA_PLATFORM
817 select SYS_HAS_CPU_SB1
818 select SYS_SUPPORTS_BIG_ENDIAN
819 select SYS_SUPPORTS_HIGHMEM
820 select SYS_SUPPORTS_LITTLE_ENDIAN
821 select ZONE_DMA32 if 64BIT
823 config SIBYTE_SENTOSA
824 bool "Sibyte BCM91250E-Sentosa"
828 select SYS_HAS_CPU_SB1
829 select SYS_SUPPORTS_BIG_ENDIAN
830 select SYS_SUPPORTS_LITTLE_ENDIAN
831 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
834 bool "Sibyte BCM91480B-BigSur"
836 select NR_CPUS_DEFAULT_4
837 select SIBYTE_BCM1x80
839 select SYS_HAS_CPU_SB1
840 select SYS_SUPPORTS_BIG_ENDIAN
841 select SYS_SUPPORTS_HIGHMEM
842 select SYS_SUPPORTS_LITTLE_ENDIAN
843 select ZONE_DMA32 if 64BIT
844 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
847 bool "SNI RM200/300/400"
850 select FW_ARC if CPU_LITTLE_ENDIAN
851 select FW_ARC32 if CPU_LITTLE_ENDIAN
852 select FW_SNIPROM if CPU_BIG_ENDIAN
853 select ARCH_MAY_HAVE_PC_FDC
854 select ARCH_MIGHT_HAVE_PC_PARPORT
855 select ARCH_MIGHT_HAVE_PC_SERIO
859 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
860 select DMA_NONCOHERENT
861 select GENERIC_ISA_DMA
863 select HAVE_PCSPKR_PLATFORM
869 select MIPS_L1_CACHE_SHIFT_6
870 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
871 select SYS_HAS_CPU_R4X00
872 select SYS_HAS_CPU_R5000
873 select SYS_HAS_CPU_R10000
874 select R5000_CPU_SCACHE
875 select SYS_HAS_EARLY_PRINTK
876 select SYS_SUPPORTS_32BIT_KERNEL
877 select SYS_SUPPORTS_64BIT_KERNEL
878 select SYS_SUPPORTS_BIG_ENDIAN
879 select SYS_SUPPORTS_HIGHMEM
880 select SYS_SUPPORTS_LITTLE_ENDIAN
881 select WAR_R4600_V2_HIT_CACHEOP
883 The SNI RM200/300/400 are MIPS-based machines manufactured by
884 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
885 Technology and now in turn merged with Fujitsu. Say Y here to
886 support this machine type.
889 bool "Toshiba TX49 series based machines"
890 select WAR_TX49XX_ICACHE_INDEX_INV
892 config MIKROTIK_RB532
893 bool "Mikrotik RB532 boards"
896 select DMA_NONCOHERENT
899 select SYS_HAS_CPU_MIPS32_R1
900 select SYS_SUPPORTS_32BIT_KERNEL
901 select SYS_SUPPORTS_LITTLE_ENDIAN
905 select MIPS_L1_CACHE_SHIFT_4
907 Support the Mikrotik(tm) RouterBoard 532 series,
908 based on the IDT RC32434 SoC.
910 config CAVIUM_OCTEON_SOC
911 bool "Cavium Networks Octeon SoC based boards"
913 select ARCH_HAS_PHYS_TO_DMA
915 select PHYS_ADDR_T_64BIT
916 select SYS_SUPPORTS_64BIT_KERNEL
917 select SYS_SUPPORTS_BIG_ENDIAN
919 select EDAC_ATOMIC_SCRUB
920 select SYS_SUPPORTS_LITTLE_ENDIAN
921 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
922 select SYS_HAS_EARLY_PRINTK
923 select SYS_HAS_CPU_CAVIUM_OCTEON
925 select HAVE_PLAT_DELAY
926 select HAVE_PLAT_FW_INIT_CMDLINE
927 select HAVE_PLAT_MEMCPY
931 select ARCH_SPARSEMEM_ENABLE
932 select SYS_SUPPORTS_SMP
933 select NR_CPUS_DEFAULT_64
934 select MIPS_NR_CPU_NR_MAP_1024
937 select MTD_COMPLEX_MAPPINGS
939 select SYS_SUPPORTS_RELOCATABLE
941 This option supports all of the Octeon reference boards from Cavium
942 Networks. It builds a kernel that dynamically determines the Octeon
943 CPU type and supports all known board reference implementations.
944 Some of the supported boards are:
951 Say Y here for most Octeon reference boards.
955 source "arch/mips/alchemy/Kconfig"
956 source "arch/mips/ath25/Kconfig"
957 source "arch/mips/ath79/Kconfig"
958 source "arch/mips/bcm47xx/Kconfig"
959 source "arch/mips/bcm63xx/Kconfig"
960 source "arch/mips/bmips/Kconfig"
961 source "arch/mips/generic/Kconfig"
962 source "arch/mips/ingenic/Kconfig"
963 source "arch/mips/jazz/Kconfig"
964 source "arch/mips/lantiq/Kconfig"
965 source "arch/mips/pic32/Kconfig"
966 source "arch/mips/ralink/Kconfig"
967 source "arch/mips/sgi-ip27/Kconfig"
968 source "arch/mips/sibyte/Kconfig"
969 source "arch/mips/txx9/Kconfig"
970 source "arch/mips/cavium-octeon/Kconfig"
971 source "arch/mips/loongson2ef/Kconfig"
972 source "arch/mips/loongson32/Kconfig"
973 source "arch/mips/loongson64/Kconfig"
977 config GENERIC_HWEIGHT
981 config GENERIC_CALIBRATE_DELAY
985 config SCHED_OMIT_FRAME_POINTER
990 # Select some configuration options automatically based on user selections.
995 config ARCH_MAY_HAVE_PC_FDC
1026 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1032 config MIPS_CLOCK_VSYSCALL
1033 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
1042 config ARCH_SUPPORTS_UPROBES
1045 config DMA_NONCOHERENT
1048 # MIPS allows mixing "slightly different" Cacheability and Coherency
1049 # Attribute bits. It is believed that the uncached access through
1050 # KSEG1 and the implementation specific "uncached accelerated" used
1051 # by pgprot_writcombine can be mixed, and the latter sometimes provides
1052 # significant advantages.
1054 select ARCH_HAS_SETUP_DMA_OPS
1055 select ARCH_HAS_DMA_WRITE_COMBINE
1056 select ARCH_HAS_DMA_PREP_COHERENT
1057 select ARCH_HAS_SYNC_DMA_FOR_CPU
1058 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
1059 select ARCH_HAS_DMA_SET_UNCACHED
1060 select DMA_NONCOHERENT_MMAP
1061 select NEED_DMA_MAP_STATE
1063 config SYS_HAS_EARLY_PRINTK
1066 config SYS_SUPPORTS_HOTPLUG_CPU
1069 config MIPS_BONITO64
1078 config NO_IOPORT_MAP
1082 def_bool CPU_NO_LOAD_STORE_LR
1084 config GENERIC_ISA_DMA
1086 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
1089 config GENERIC_ISA_DMA_SUPPORT_BROKEN
1091 select GENERIC_ISA_DMA
1093 config HAVE_PLAT_DELAY
1096 config HAVE_PLAT_FW_INIT_CMDLINE
1099 config HAVE_PLAT_MEMCPY
1105 config SYS_SUPPORTS_RELOCATABLE
1108 Selected if the platform supports relocating the kernel.
1109 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1110 to allow access to command line and entropy sources.
1113 # Endianness selection. Sufficiently obscure so many users don't know what to
1114 # answer,so we try hard to limit the available choices. Also the use of a
1115 # choice statement should be more obvious to the user.
1118 prompt "Endianness selection"
1120 Some MIPS machines can be configured for either little or big endian
1121 byte order. These modes require different kernels and a different
1122 Linux distribution. In general there is one preferred byteorder for a
1123 particular system but some systems are just as commonly used in the
1124 one or the other endianness.
1126 config CPU_BIG_ENDIAN
1128 depends on SYS_SUPPORTS_BIG_ENDIAN
1130 config CPU_LITTLE_ENDIAN
1131 bool "Little endian"
1132 depends on SYS_SUPPORTS_LITTLE_ENDIAN
1139 config SYS_SUPPORTS_APM_EMULATION
1142 config SYS_SUPPORTS_BIG_ENDIAN
1145 config SYS_SUPPORTS_LITTLE_ENDIAN
1148 config MIPS_HUGE_TLB_SUPPORT
1149 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
1157 config PCI_GT64XXX_PCI0
1160 config PCI_XTALK_BRIDGE
1163 config NO_EXCEPT_FILL
1169 config SWAP_IO_SPACE
1172 config SGI_HAS_INDYDOG
1184 config SGI_HAS_ZILOG
1187 config SGI_HAS_I8042
1190 config DEFAULT_SGI_PARTITION
1202 config MIPS_L1_CACHE_SHIFT_4
1205 config MIPS_L1_CACHE_SHIFT_5
1208 config MIPS_L1_CACHE_SHIFT_6
1211 config MIPS_L1_CACHE_SHIFT_7
1214 config MIPS_L1_CACHE_SHIFT
1216 default "7" if MIPS_L1_CACHE_SHIFT_7
1217 default "6" if MIPS_L1_CACHE_SHIFT_6
1218 default "5" if MIPS_L1_CACHE_SHIFT_5
1219 default "4" if MIPS_L1_CACHE_SHIFT_4
1222 config ARC_CMDLINE_ONLY
1226 bool "ARC console support"
1227 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
1241 menu "CPU selection"
1247 config CPU_LOONGSON64
1248 bool "Loongson 64-bit CPU"
1249 depends on SYS_HAS_CPU_LOONGSON64
1250 select ARCH_HAS_PHYS_TO_DMA
1252 select CPU_HAS_PREFETCH
1253 select CPU_SUPPORTS_64BIT_KERNEL
1254 select CPU_SUPPORTS_HIGHMEM
1255 select CPU_SUPPORTS_HUGEPAGES
1256 select CPU_SUPPORTS_MSA
1257 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
1258 select CPU_MIPSR2_IRQ_VI
1259 select DMA_NONCOHERENT
1260 select WEAK_ORDERING
1261 select WEAK_REORDERING_BEYOND_LLSC
1262 select MIPS_ASID_BITS_VARIABLE
1263 select MIPS_PGD_C0_CONTEXT
1264 select MIPS_L1_CACHE_SHIFT_6
1265 select MIPS_FP_SUPPORT
1270 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1271 cores implements the MIPS64R2 instruction set with many extensions,
1272 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1273 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1274 Loongson-2E/2F is not covered here and will be removed in future.
1276 config LOONGSON3_ENHANCEMENT
1277 bool "New Loongson-3 CPU Enhancements"
1279 depends on CPU_LOONGSON64
1281 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1282 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1283 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1284 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1285 Fast TLB refill support, etc.
1287 This option enable those enhancements which are not probed at run
1288 time. If you want a generic kernel to run on all Loongson 3 machines,
1289 please say 'N' here. If you want a high-performance kernel to run on
1290 new Loongson-3 machines only, please say 'Y' here.
1292 config CPU_LOONGSON3_WORKAROUNDS
1293 bool "Loongson-3 LLSC Workarounds"
1295 depends on CPU_LOONGSON64
1297 Loongson-3 processors have the llsc issues which require workarounds.
1298 Without workarounds the system may hang unexpectedly.
1300 Say Y, unless you know what you are doing.
1302 config CPU_LOONGSON3_CPUCFG_EMULATION
1303 bool "Emulate the CPUCFG instruction on older Loongson cores"
1305 depends on CPU_LOONGSON64
1307 Loongson-3A R4 and newer have the CPUCFG instruction available for
1308 userland to query CPU capabilities, much like CPUID on x86. This
1309 option provides emulation of the instruction on older Loongson
1310 cores, back to Loongson-3A1000.
1312 If unsure, please say Y.
1314 config CPU_LOONGSON2E
1316 depends on SYS_HAS_CPU_LOONGSON2E
1317 select CPU_LOONGSON2EF
1319 The Loongson 2E processor implements the MIPS III instruction set
1320 with many extensions.
1322 It has an internal FPGA northbridge, which is compatible to
1325 config CPU_LOONGSON2F
1327 depends on SYS_HAS_CPU_LOONGSON2F
1328 select CPU_LOONGSON2EF
1330 The Loongson 2F processor implements the MIPS III instruction set
1331 with many extensions.
1333 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1334 have a similar programming interface with FPGA northbridge used in
1337 config CPU_LOONGSON1B
1339 depends on SYS_HAS_CPU_LOONGSON1B
1340 select CPU_LOONGSON32
1341 select LEDS_GPIO_REGISTER
1343 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1344 Release 1 instruction set and part of the MIPS32 Release 2
1347 config CPU_LOONGSON1C
1349 depends on SYS_HAS_CPU_LOONGSON1C
1350 select CPU_LOONGSON32
1351 select LEDS_GPIO_REGISTER
1353 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1354 Release 1 instruction set and part of the MIPS32 Release 2
1357 config CPU_MIPS32_R1
1358 bool "MIPS32 Release 1"
1359 depends on SYS_HAS_CPU_MIPS32_R1
1360 select CPU_HAS_PREFETCH
1361 select CPU_SUPPORTS_32BIT_KERNEL
1362 select CPU_SUPPORTS_HIGHMEM
1364 Choose this option to build a kernel for release 1 or later of the
1365 MIPS32 architecture. Most modern embedded systems with a 32-bit
1366 MIPS processor are based on a MIPS32 processor. If you know the
1367 specific type of processor in your system, choose those that one
1368 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1369 Release 2 of the MIPS32 architecture is available since several
1370 years so chances are you even have a MIPS32 Release 2 processor
1371 in which case you should choose CPU_MIPS32_R2 instead for better
1374 config CPU_MIPS32_R2
1375 bool "MIPS32 Release 2"
1376 depends on SYS_HAS_CPU_MIPS32_R2
1377 select CPU_HAS_PREFETCH
1378 select CPU_SUPPORTS_32BIT_KERNEL
1379 select CPU_SUPPORTS_HIGHMEM
1380 select CPU_SUPPORTS_MSA
1383 Choose this option to build a kernel for release 2 or later of the
1384 MIPS32 architecture. Most modern embedded systems with a 32-bit
1385 MIPS processor are based on a MIPS32 processor. If you know the
1386 specific type of processor in your system, choose those that one
1387 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1389 config CPU_MIPS32_R5
1390 bool "MIPS32 Release 5"
1391 depends on SYS_HAS_CPU_MIPS32_R5
1392 select CPU_HAS_PREFETCH
1393 select CPU_SUPPORTS_32BIT_KERNEL
1394 select CPU_SUPPORTS_HIGHMEM
1395 select CPU_SUPPORTS_MSA
1397 select MIPS_O32_FP64_SUPPORT
1399 Choose this option to build a kernel for release 5 or later of the
1400 MIPS32 architecture. New MIPS processors, starting with the Warrior
1401 family, are based on a MIPS32r5 processor. If you own an older
1402 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1404 config CPU_MIPS32_R6
1405 bool "MIPS32 Release 6"
1406 depends on SYS_HAS_CPU_MIPS32_R6
1407 select CPU_HAS_PREFETCH
1408 select CPU_NO_LOAD_STORE_LR
1409 select CPU_SUPPORTS_32BIT_KERNEL
1410 select CPU_SUPPORTS_HIGHMEM
1411 select CPU_SUPPORTS_MSA
1413 select MIPS_O32_FP64_SUPPORT
1415 Choose this option to build a kernel for release 6 or later of the
1416 MIPS32 architecture. New MIPS processors, starting with the Warrior
1417 family, are based on a MIPS32r6 processor. If you own an older
1418 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1420 config CPU_MIPS64_R1
1421 bool "MIPS64 Release 1"
1422 depends on SYS_HAS_CPU_MIPS64_R1
1423 select CPU_HAS_PREFETCH
1424 select CPU_SUPPORTS_32BIT_KERNEL
1425 select CPU_SUPPORTS_64BIT_KERNEL
1426 select CPU_SUPPORTS_HIGHMEM
1427 select CPU_SUPPORTS_HUGEPAGES
1429 Choose this option to build a kernel for release 1 or later of the
1430 MIPS64 architecture. Many modern embedded systems with a 64-bit
1431 MIPS processor are based on a MIPS64 processor. If you know the
1432 specific type of processor in your system, choose those that one
1433 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1434 Release 2 of the MIPS64 architecture is available since several
1435 years so chances are you even have a MIPS64 Release 2 processor
1436 in which case you should choose CPU_MIPS64_R2 instead for better
1439 config CPU_MIPS64_R2
1440 bool "MIPS64 Release 2"
1441 depends on SYS_HAS_CPU_MIPS64_R2
1442 select CPU_HAS_PREFETCH
1443 select CPU_SUPPORTS_32BIT_KERNEL
1444 select CPU_SUPPORTS_64BIT_KERNEL
1445 select CPU_SUPPORTS_HIGHMEM
1446 select CPU_SUPPORTS_HUGEPAGES
1447 select CPU_SUPPORTS_MSA
1450 Choose this option to build a kernel for release 2 or later of the
1451 MIPS64 architecture. Many modern embedded systems with a 64-bit
1452 MIPS processor are based on a MIPS64 processor. If you know the
1453 specific type of processor in your system, choose those that one
1454 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1456 config CPU_MIPS64_R5
1457 bool "MIPS64 Release 5"
1458 depends on SYS_HAS_CPU_MIPS64_R5
1459 select CPU_HAS_PREFETCH
1460 select CPU_SUPPORTS_32BIT_KERNEL
1461 select CPU_SUPPORTS_64BIT_KERNEL
1462 select CPU_SUPPORTS_HIGHMEM
1463 select CPU_SUPPORTS_HUGEPAGES
1464 select CPU_SUPPORTS_MSA
1465 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1468 Choose this option to build a kernel for release 5 or later of the
1469 MIPS64 architecture. This is a intermediate MIPS architecture
1470 release partly implementing release 6 features. Though there is no
1471 any hardware known to be based on this release.
1473 config CPU_MIPS64_R6
1474 bool "MIPS64 Release 6"
1475 depends on SYS_HAS_CPU_MIPS64_R6
1476 select CPU_HAS_PREFETCH
1477 select CPU_NO_LOAD_STORE_LR
1478 select CPU_SUPPORTS_32BIT_KERNEL
1479 select CPU_SUPPORTS_64BIT_KERNEL
1480 select CPU_SUPPORTS_HIGHMEM
1481 select CPU_SUPPORTS_HUGEPAGES
1482 select CPU_SUPPORTS_MSA
1483 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1486 Choose this option to build a kernel for release 6 or later of the
1487 MIPS64 architecture. New MIPS processors, starting with the Warrior
1488 family, are based on a MIPS64r6 processor. If you own an older
1489 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1492 bool "MIPS Warrior P5600"
1493 depends on SYS_HAS_CPU_P5600
1494 select CPU_HAS_PREFETCH
1495 select CPU_SUPPORTS_32BIT_KERNEL
1496 select CPU_SUPPORTS_HIGHMEM
1497 select CPU_SUPPORTS_MSA
1498 select CPU_SUPPORTS_CPUFREQ
1499 select CPU_MIPSR2_IRQ_VI
1500 select CPU_MIPSR2_IRQ_EI
1502 select MIPS_O32_FP64_SUPPORT
1504 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
1505 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
1506 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1507 level features like up to six P5600 calculation cores, CM2 with L2
1508 cache, IOCU/IOMMU (though might be unused depending on the system-
1509 specific IP core configuration), GIC, CPC, virtualisation module,
1514 depends on SYS_HAS_CPU_R3000
1517 select CPU_SUPPORTS_32BIT_KERNEL
1518 select CPU_SUPPORTS_HIGHMEM
1520 Please make sure to pick the right CPU type. Linux/MIPS is not
1521 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
1522 *not* work on R4000 machines and vice versa. However, since most
1523 of the supported machines have an R4000 (or similar) CPU, R4x00
1524 might be a safe bet. If the resulting kernel does not work,
1525 try to recompile with R3000.
1529 depends on SYS_HAS_CPU_R4300
1530 select CPU_SUPPORTS_32BIT_KERNEL
1531 select CPU_SUPPORTS_64BIT_KERNEL
1533 MIPS Technologies R4300-series processors.
1537 depends on SYS_HAS_CPU_R4X00
1538 select CPU_SUPPORTS_32BIT_KERNEL
1539 select CPU_SUPPORTS_64BIT_KERNEL
1540 select CPU_SUPPORTS_HUGEPAGES
1542 MIPS Technologies R4000-series processors other than 4300, including
1543 the R4000, R4400, R4600, and 4700.
1547 depends on SYS_HAS_CPU_TX49XX
1548 select CPU_HAS_PREFETCH
1549 select CPU_SUPPORTS_32BIT_KERNEL
1550 select CPU_SUPPORTS_64BIT_KERNEL
1551 select CPU_SUPPORTS_HUGEPAGES
1555 depends on SYS_HAS_CPU_R5000
1556 select CPU_SUPPORTS_32BIT_KERNEL
1557 select CPU_SUPPORTS_64BIT_KERNEL
1558 select CPU_SUPPORTS_HUGEPAGES
1560 MIPS Technologies R5000-series processors other than the Nevada.
1564 depends on SYS_HAS_CPU_R5500
1565 select CPU_SUPPORTS_32BIT_KERNEL
1566 select CPU_SUPPORTS_64BIT_KERNEL
1567 select CPU_SUPPORTS_HUGEPAGES
1569 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1574 depends on SYS_HAS_CPU_NEVADA
1575 select CPU_SUPPORTS_32BIT_KERNEL
1576 select CPU_SUPPORTS_64BIT_KERNEL
1577 select CPU_SUPPORTS_HUGEPAGES
1579 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1583 depends on SYS_HAS_CPU_R10000
1584 select CPU_HAS_PREFETCH
1585 select CPU_SUPPORTS_32BIT_KERNEL
1586 select CPU_SUPPORTS_64BIT_KERNEL
1587 select CPU_SUPPORTS_HIGHMEM
1588 select CPU_SUPPORTS_HUGEPAGES
1590 MIPS Technologies R10000-series processors.
1594 depends on SYS_HAS_CPU_RM7000
1595 select CPU_HAS_PREFETCH
1596 select CPU_SUPPORTS_32BIT_KERNEL
1597 select CPU_SUPPORTS_64BIT_KERNEL
1598 select CPU_SUPPORTS_HIGHMEM
1599 select CPU_SUPPORTS_HUGEPAGES
1603 depends on SYS_HAS_CPU_SB1
1604 select CPU_SUPPORTS_32BIT_KERNEL
1605 select CPU_SUPPORTS_64BIT_KERNEL
1606 select CPU_SUPPORTS_HIGHMEM
1607 select CPU_SUPPORTS_HUGEPAGES
1608 select WEAK_ORDERING
1610 config CPU_CAVIUM_OCTEON
1611 bool "Cavium Octeon processor"
1612 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1613 select CPU_HAS_PREFETCH
1614 select CPU_SUPPORTS_64BIT_KERNEL
1615 select HAVE_PAGE_SIZE_8KB if !MIPS_VA_BITS_48
1616 select HAVE_PAGE_SIZE_32KB if !MIPS_VA_BITS_48
1617 select WEAK_ORDERING
1618 select CPU_SUPPORTS_HIGHMEM
1619 select CPU_SUPPORTS_HUGEPAGES
1620 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1621 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1622 select MIPS_L1_CACHE_SHIFT_7
1625 The Cavium Octeon processor is a highly integrated chip containing
1626 many ethernet hardware widgets for networking tasks. The processor
1627 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1628 Full details can be found at http://www.caviumnetworks.com.
1631 bool "Broadcom BMIPS"
1632 depends on SYS_HAS_CPU_BMIPS
1634 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
1635 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
1636 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
1637 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
1638 select CPU_SUPPORTS_32BIT_KERNEL
1639 select DMA_NONCOHERENT
1641 select SWAP_IO_SPACE
1642 select WEAK_ORDERING
1643 select CPU_SUPPORTS_HIGHMEM
1644 select CPU_HAS_PREFETCH
1645 select CPU_SUPPORTS_CPUFREQ
1646 select MIPS_EXTERNAL_TIMER
1647 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1649 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1653 config CPU_MIPS32_3_5_FEATURES
1654 bool "MIPS32 Release 3.5 Features"
1655 depends on SYS_HAS_CPU_MIPS32_R3_5
1656 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
1659 Choose this option to build a kernel for release 2 or later of the
1660 MIPS32 architecture including features from the 3.5 release such as
1661 support for Enhanced Virtual Addressing (EVA).
1663 config CPU_MIPS32_3_5_EVA
1664 bool "Enhanced Virtual Addressing (EVA)"
1665 depends on CPU_MIPS32_3_5_FEATURES
1669 Choose this option if you want to enable the Enhanced Virtual
1670 Addressing (EVA) on your MIPS32 core (such as proAptiv).
1671 One of its primary benefits is an increase in the maximum size
1672 of lowmem (up to 3GB). If unsure, say 'N' here.
1674 config CPU_MIPS32_R5_FEATURES
1675 bool "MIPS32 Release 5 Features"
1676 depends on SYS_HAS_CPU_MIPS32_R5
1677 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
1679 Choose this option to build a kernel for release 2 or later of the
1680 MIPS32 architecture including features from release 5 such as
1681 support for Extended Physical Addressing (XPA).
1683 config CPU_MIPS32_R5_XPA
1684 bool "Extended Physical Addressing (XPA)"
1685 depends on CPU_MIPS32_R5_FEATURES
1687 depends on !PAGE_SIZE_4KB
1688 depends on SYS_SUPPORTS_HIGHMEM
1691 select PHYS_ADDR_T_64BIT
1694 Choose this option if you want to enable the Extended Physical
1695 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
1696 benefit is to increase physical addressing equal to or greater
1697 than 40 bits. Note that this has the side effect of turning on
1698 64-bit addressing which in turn makes the PTEs 64-bit in size.
1699 If unsure, say 'N' here.
1702 config CPU_NOP_WORKAROUNDS
1705 config CPU_JUMP_WORKAROUNDS
1708 config CPU_LOONGSON2F_WORKAROUNDS
1709 bool "Loongson 2F Workarounds"
1711 select CPU_NOP_WORKAROUNDS
1712 select CPU_JUMP_WORKAROUNDS
1714 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1715 require workarounds. Without workarounds the system may hang
1716 unexpectedly. For more information please refer to the gas
1717 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1719 Loongson 2F03 and later have fixed these issues and no workarounds
1720 are needed. The workarounds have no significant side effect on them
1721 but may decrease the performance of the system so this option should
1722 be disabled unless the kernel is intended to be run on 2F01 or 2F02
1725 If unsure, please say Y.
1726 endif # CPU_LOONGSON2F
1728 config SYS_SUPPORTS_ZBOOT
1730 select HAVE_KERNEL_GZIP
1731 select HAVE_KERNEL_BZIP2
1732 select HAVE_KERNEL_LZ4
1733 select HAVE_KERNEL_LZMA
1734 select HAVE_KERNEL_LZO
1735 select HAVE_KERNEL_XZ
1736 select HAVE_KERNEL_ZSTD
1738 config SYS_SUPPORTS_ZBOOT_UART16550
1740 select SYS_SUPPORTS_ZBOOT
1742 config SYS_SUPPORTS_ZBOOT_UART_PROM
1744 select SYS_SUPPORTS_ZBOOT
1746 config CPU_LOONGSON2EF
1748 select CPU_SUPPORTS_32BIT_KERNEL
1749 select CPU_SUPPORTS_64BIT_KERNEL
1750 select CPU_SUPPORTS_HIGHMEM
1751 select CPU_SUPPORTS_HUGEPAGES
1753 config CPU_LOONGSON32
1757 select CPU_HAS_PREFETCH
1758 select CPU_SUPPORTS_32BIT_KERNEL
1759 select CPU_SUPPORTS_HIGHMEM
1760 select CPU_SUPPORTS_CPUFREQ
1762 config CPU_BMIPS32_3300
1763 select SMP_UP if SMP
1766 config CPU_BMIPS4350
1768 select SYS_SUPPORTS_SMP
1769 select SYS_SUPPORTS_HOTPLUG_CPU
1771 config CPU_BMIPS4380
1773 select MIPS_L1_CACHE_SHIFT_6
1774 select SYS_SUPPORTS_SMP
1775 select SYS_SUPPORTS_HOTPLUG_CPU
1778 config CPU_BMIPS5000
1780 select MIPS_CPU_SCACHE
1781 select MIPS_L1_CACHE_SHIFT_7
1782 select SYS_SUPPORTS_SMP
1783 select SYS_SUPPORTS_HOTPLUG_CPU
1786 config SYS_HAS_CPU_LOONGSON64
1788 select CPU_SUPPORTS_CPUFREQ
1791 config SYS_HAS_CPU_LOONGSON2E
1794 config SYS_HAS_CPU_LOONGSON2F
1796 select CPU_SUPPORTS_CPUFREQ
1797 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1799 config SYS_HAS_CPU_LOONGSON1B
1802 config SYS_HAS_CPU_LOONGSON1C
1805 config SYS_HAS_CPU_MIPS32_R1
1808 config SYS_HAS_CPU_MIPS32_R2
1811 config SYS_HAS_CPU_MIPS32_R3_5
1814 config SYS_HAS_CPU_MIPS32_R5
1817 config SYS_HAS_CPU_MIPS32_R6
1820 config SYS_HAS_CPU_MIPS64_R1
1823 config SYS_HAS_CPU_MIPS64_R2
1826 config SYS_HAS_CPU_MIPS64_R5
1829 config SYS_HAS_CPU_MIPS64_R6
1832 config SYS_HAS_CPU_P5600
1835 config SYS_HAS_CPU_R3000
1838 config SYS_HAS_CPU_R4300
1841 config SYS_HAS_CPU_R4X00
1844 config SYS_HAS_CPU_TX49XX
1847 config SYS_HAS_CPU_R5000
1850 config SYS_HAS_CPU_R5500
1853 config SYS_HAS_CPU_NEVADA
1856 config SYS_HAS_CPU_R10000
1859 config SYS_HAS_CPU_RM7000
1862 config SYS_HAS_CPU_SB1
1865 config SYS_HAS_CPU_CAVIUM_OCTEON
1868 config SYS_HAS_CPU_BMIPS
1871 config SYS_HAS_CPU_BMIPS32_3300
1873 select SYS_HAS_CPU_BMIPS
1875 config SYS_HAS_CPU_BMIPS4350
1877 select SYS_HAS_CPU_BMIPS
1879 config SYS_HAS_CPU_BMIPS4380
1881 select SYS_HAS_CPU_BMIPS
1883 config SYS_HAS_CPU_BMIPS5000
1885 select SYS_HAS_CPU_BMIPS
1888 # CPU may reorder R->R, R->W, W->R, W->W
1889 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1891 config WEAK_ORDERING
1895 # CPU may reorder reads and writes beyond LL/SC
1896 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1898 config WEAK_REORDERING_BEYOND_LLSC
1903 # These two indicate any level of the MIPS32 and MIPS64 architecture
1907 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
1908 CPU_MIPS32_R6 || CPU_P5600
1912 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
1913 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1916 # These indicate the revision of the architecture
1920 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1924 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1926 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1931 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1933 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1938 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
1940 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1941 select HAVE_ARCH_BITREVERSE
1942 select MIPS_ASID_BITS_VARIABLE
1943 select MIPS_CRC_SUPPORT
1946 config TARGET_ISA_REV
1948 default 1 if CPU_MIPSR1
1949 default 2 if CPU_MIPSR2
1950 default 5 if CPU_MIPSR5
1951 default 6 if CPU_MIPSR6
1954 Reflects the ISA revision being targeted by the kernel build. This
1955 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1963 config SYS_SUPPORTS_32BIT_KERNEL
1965 config SYS_SUPPORTS_64BIT_KERNEL
1967 config CPU_SUPPORTS_32BIT_KERNEL
1969 config CPU_SUPPORTS_64BIT_KERNEL
1971 config CPU_SUPPORTS_CPUFREQ
1973 config CPU_SUPPORTS_ADDRWINCFG
1975 config CPU_SUPPORTS_HUGEPAGES
1977 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
1978 config MIPS_PGD_C0_CONTEXT
1981 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1984 # Set to y for ptrace access to watch registers.
1986 config HARDWARE_WATCHPOINTS
1988 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1993 prompt "Kernel code model"
1995 You should only select this option if you have a workload that
1996 actually benefits from 64-bit processing or if your machine has
1997 large memory. You will only be presented a single option in this
1998 menu if your system does not support both 32-bit and 64-bit kernels.
2001 bool "32-bit kernel"
2002 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
2005 Select this option if you want to build a 32-bit kernel.
2008 bool "64-bit kernel"
2009 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
2011 Select this option if you want to build a 64-bit kernel.
2015 config MIPS_VA_BITS_48
2016 bool "48 bits virtual memory"
2019 Support a maximum at least 48 bits of application virtual
2020 memory. Default is 40 bits or less, depending on the CPU.
2021 For page sizes 16k and above, this option results in a small
2022 memory overhead for page tables. For 4k page size, a fourth
2023 level of page tables is added which imposes both a memory
2024 overhead as well as slower TLB fault handling.
2028 config ZBOOT_LOAD_ADDRESS
2029 hex "Compressed kernel load address"
2030 default 0xffffffff80400000 if BCM47XX
2032 depends on SYS_SUPPORTS_ZBOOT
2034 The address to load compressed kernel, aka vmlinuz.
2036 This is only used if non-zero.
2038 config ARCH_FORCE_MAX_ORDER
2039 int "Maximum zone order"
2040 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
2041 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2042 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2045 The kernel memory allocator divides physically contiguous memory
2046 blocks into "zones", where each zone is a power of two number of
2047 pages. This option selects the largest power of two that the kernel
2048 keeps in the memory allocator. If you need to allocate very large
2049 blocks of physically contiguous memory, then you may need to
2050 increase this value.
2052 The page size is not necessarily 4KB. Keep this in mind
2053 when choosing a value for this option.
2058 config IP22_CPU_SCACHE
2063 # Support for a MIPS32 / MIPS64 style S-caches
2065 config MIPS_CPU_SCACHE
2069 config R5000_CPU_SCACHE
2073 config RM7000_CPU_SCACHE
2077 config SIBYTE_DMA_PAGEOPS
2078 bool "Use DMA to clear/copy pages"
2081 Instead of using the CPU to zero and copy pages, use a Data Mover
2082 channel. These DMA channels are otherwise unused by the standard
2083 SiByte Linux port. Seems to give a small performance benefit.
2085 config CPU_HAS_PREFETCH
2088 config CPU_GENERIC_DUMP_TLB
2090 default y if !CPU_R3000
2092 config MIPS_FP_SUPPORT
2093 bool "Floating Point support" if EXPERT
2096 Select y to include support for floating point in the kernel
2097 including initialization of FPU hardware, FP context save & restore
2098 and emulation of an FPU where necessary. Without this support any
2099 userland program attempting to use floating point instructions will
2102 If you know that your userland will not attempt to use floating point
2103 instructions then you can say n here to shrink the kernel a little.
2107 config CPU_R2300_FPU
2109 depends on MIPS_FP_SUPPORT
2110 default y if CPU_R3000
2117 depends on MIPS_FP_SUPPORT
2118 default y if !CPU_R2300_FPU
2120 config CPU_R4K_CACHE_TLB
2122 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
2125 bool "MIPS MT SMP support (1 TC on each available VPE)"
2127 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
2128 select CPU_MIPSR2_IRQ_VI
2129 select CPU_MIPSR2_IRQ_EI
2134 select SYS_SUPPORTS_SMP
2135 select SYS_SUPPORTS_SCHED_SMT
2136 select MIPS_PERF_SHARED_TC_COUNTERS
2138 This is a kernel model which is known as SMVP. This is supported
2139 on cores with the MT ASE and uses the available VPEs to implement
2140 virtual processors which supports SMP. This is equivalent to the
2141 Intel Hyperthreading feature. For further information go to
2142 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2148 bool "SMT (multithreading) scheduler support"
2149 depends on SYS_SUPPORTS_SCHED_SMT
2152 SMT scheduler support improves the CPU scheduler's decision making
2153 when dealing with MIPS MT enabled cores at a cost of slightly
2154 increased overhead in some places. If unsure say N here.
2156 config SYS_SUPPORTS_SCHED_SMT
2159 config SYS_SUPPORTS_MULTITHREADING
2162 config MIPS_MT_FPAFF
2163 bool "Dynamic FPU affinity for FP-intensive threads"
2165 depends on MIPS_MT_SMP
2167 config MIPSR2_TO_R6_EMULATOR
2168 bool "MIPS R2-to-R6 emulator"
2169 depends on CPU_MIPSR6
2170 depends on MIPS_FP_SUPPORT
2173 Choose this option if you want to run non-R6 MIPS userland code.
2174 Even if you say 'Y' here, the emulator will still be disabled by
2175 default. You can enable it using the 'mipsr2emu' kernel option.
2176 The only reason this is a build-time option is to save ~14K from the
2179 config SYS_SUPPORTS_VPE_LOADER
2181 depends on SYS_SUPPORTS_MULTITHREADING
2183 Indicates that the platform supports the VPE loader, and provides
2186 config MIPS_VPE_LOADER
2187 bool "VPE loader support."
2188 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
2189 select CPU_MIPSR2_IRQ_VI
2190 select CPU_MIPSR2_IRQ_EI
2193 Includes a loader for loading an elf relocatable object
2194 onto another VPE and running it.
2196 config MIPS_VPE_LOADER_MT
2199 depends on MIPS_VPE_LOADER
2201 config MIPS_VPE_LOADER_TOM
2202 bool "Load VPE program into memory hidden from linux"
2203 depends on MIPS_VPE_LOADER
2206 The loader can use memory that is present but has been hidden from
2207 Linux using the kernel command line option "mem=xxMB". It's up to
2208 you to ensure the amount you put in the option and the space your
2209 program requires is less or equal to the amount physically present.
2211 config MIPS_VPE_APSP_API
2212 bool "Enable support for AP/SP API (RTLX)"
2213 depends on MIPS_VPE_LOADER
2215 config MIPS_VPE_APSP_API_MT
2218 depends on MIPS_VPE_APSP_API
2221 bool "MIPS Coherent Processing System support"
2222 depends on SYS_SUPPORTS_MIPS_CPS
2224 select MIPS_CPS_PM if HOTPLUG_CPU
2226 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
2227 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
2228 select SYS_SUPPORTS_HOTPLUG_CPU
2229 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
2230 select SYS_SUPPORTS_SMP
2231 select WEAK_ORDERING
2232 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
2234 Select this if you wish to run an SMP kernel across multiple cores
2235 within a MIPS Coherent Processing System. When this option is
2236 enabled the kernel will probe for other cores and boot them with
2237 no external assistance. It is safe to enable this when hardware
2238 support is unavailable.
2251 config SB1_PASS_2_WORKAROUNDS
2253 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
2256 config SB1_PASS_2_1_WORKAROUNDS
2258 depends on CPU_SB1 && CPU_SB1_PASS_2
2262 prompt "SmartMIPS or microMIPS ASE support"
2264 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
2267 Select this if you want neither microMIPS nor SmartMIPS support
2269 config CPU_HAS_SMARTMIPS
2270 depends on SYS_SUPPORTS_SMARTMIPS
2273 SmartMIPS is a extension of the MIPS32 architecture aimed at
2274 increased security at both hardware and software level for
2275 smartcards. Enabling this option will allow proper use of the
2276 SmartMIPS instructions by Linux applications. However a kernel with
2277 this option will not work on a MIPS core without SmartMIPS core. If
2278 you don't know you probably don't have SmartMIPS and should say N
2281 config CPU_MICROMIPS
2282 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
2285 When this option is enabled the kernel will be built using the
2291 bool "Support for the MIPS SIMD Architecture"
2292 depends on CPU_SUPPORTS_MSA
2293 depends on MIPS_FP_SUPPORT
2294 depends on 64BIT || MIPS_O32_FP64_SUPPORT
2296 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2297 and a set of SIMD instructions to operate on them. When this option
2298 is enabled the kernel will support allocating & switching MSA
2299 vector register contexts. If you know that your kernel will only be
2300 running on CPUs which do not support MSA or that your userland will
2301 not be making use of it then you may wish to say N here to reduce
2302 the size & complexity of your kernel.
2313 depends on !CPU_DIEI_BROKEN
2316 config CPU_DIEI_BROKEN
2322 config CPU_NO_LOAD_STORE_LR
2325 CPU lacks support for unaligned load and store instructions:
2326 LWL, LWR, SWL, SWR (Load/store word left/right).
2327 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
2331 # Vectored interrupt mode is an R2 feature
2333 config CPU_MIPSR2_IRQ_VI
2337 # Extended interrupt mode is an R2 feature
2339 config CPU_MIPSR2_IRQ_EI
2344 depends on !CPU_R3000
2351 # Work around the "daddi" and "daddiu" CPU errata:
2353 # - The `daddi' instruction fails to trap on overflow.
2354 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2357 # - The `daddiu' instruction can produce an incorrect result.
2358 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2360 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2362 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
2363 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
2364 config CPU_DADDI_WORKAROUNDS
2367 # Work around certain R4000 CPU errata (as implemented by GCC):
2369 # - A double-word or a variable shift may give an incorrect result
2370 # if executed immediately after starting an integer division:
2371 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2373 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2376 # - A double-word or a variable shift may give an incorrect result
2377 # if executed while an integer multiplication is in progress:
2378 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2381 # - An integer division may give an incorrect result if started in
2382 # a delay slot of a taken branch or a jump:
2383 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2385 config CPU_R4000_WORKAROUNDS
2387 select CPU_R4400_WORKAROUNDS
2389 # Work around certain R4400 CPU errata (as implemented by GCC):
2391 # - A double-word or a variable shift may give an incorrect result
2392 # if executed immediately after starting an integer division:
2393 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2394 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2395 config CPU_R4400_WORKAROUNDS
2398 config CPU_R4X00_BUGS64
2400 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2402 config MIPS_ASID_SHIFT
2404 default 6 if CPU_R3000
2407 config MIPS_ASID_BITS
2409 default 0 if MIPS_ASID_BITS_VARIABLE
2410 default 6 if CPU_R3000
2413 config MIPS_ASID_BITS_VARIABLE
2416 config MIPS_CRC_SUPPORT
2419 # R4600 erratum. Due to the lack of errata information the exact
2420 # technical details aren't known. I've experimentally found that disabling
2421 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2423 config WAR_R4600_V1_INDEX_ICACHEOP
2426 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2428 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
2429 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
2430 # executed if there is no other dcache activity. If the dcache is
2431 # accessed for another instruction immediately preceding when these
2432 # cache instructions are executing, it is possible that the dcache
2433 # tag match outputs used by these cache instructions will be
2434 # incorrect. These cache instructions should be preceded by at least
2435 # four instructions that are not any kind of load or store
2438 # This is not allowed: lw
2442 # cache Hit_Writeback_Invalidate_D
2444 # This is allowed: lw
2449 # cache Hit_Writeback_Invalidate_D
2450 config WAR_R4600_V1_HIT_CACHEOP
2453 # Writeback and invalidate the primary cache dcache before DMA.
2455 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
2456 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
2457 # operate correctly if the internal data cache refill buffer is empty. These
2458 # CACHE instructions should be separated from any potential data cache miss
2459 # by a load instruction to an uncached address to empty the response buffer."
2460 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
2462 config WAR_R4600_V2_HIT_CACHEOP
2465 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2466 # the line which this instruction itself exists, the following
2467 # operation is not guaranteed."
2469 # Workaround: do two phase flushing for Index_Invalidate_I
2470 config WAR_TX49XX_ICACHE_INDEX_INV
2473 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2474 # opposes it being called that) where invalid instructions in the same
2475 # I-cache line worth of instructions being fetched may case spurious
2477 config WAR_ICACHE_REFILLS
2480 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2481 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2482 config WAR_R10000_LLSC
2485 # 34K core erratum: "Problems Executing the TLBR Instruction"
2486 config WAR_MIPS34K_MISSED_ITLB
2490 # - Highmem only makes sense for the 32-bit kernel.
2491 # - The current highmem code will only work properly on physically indexed
2492 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2493 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
2494 # moment we protect the user and offer the highmem option only on machines
2495 # where it's known to be safe. This will not offer highmem on a few systems
2496 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
2497 # indexed CPUs but we're playing safe.
2498 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2499 # know they might have memory configurations that could make use of highmem
2503 bool "High Memory Support"
2504 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
2507 config CPU_SUPPORTS_HIGHMEM
2510 config SYS_SUPPORTS_HIGHMEM
2513 config SYS_SUPPORTS_SMARTMIPS
2516 config SYS_SUPPORTS_MICROMIPS
2519 config SYS_SUPPORTS_MIPS16
2522 This option must be set if a kernel might be executed on a MIPS16-
2523 enabled CPU even if MIPS16 is not actually being used. In other
2524 words, it makes the kernel MIPS16-tolerant.
2526 config CPU_SUPPORTS_MSA
2529 config ARCH_FLATMEM_ENABLE
2531 depends on !NUMA && !CPU_LOONGSON2EF
2533 config ARCH_SPARSEMEM_ENABLE
2538 depends on SYS_SUPPORTS_NUMA
2540 select HAVE_SETUP_PER_CPU_AREA
2541 select NEED_PER_CPU_EMBED_FIRST_CHUNK
2543 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2544 Access). This option improves performance on systems with more
2545 than two nodes; on two node systems it is generally better to
2546 leave it disabled; on single node systems leave this option
2549 config SYS_SUPPORTS_NUMA
2552 config HAVE_ARCH_NODEDATA_EXTENSION
2556 bool "Relocatable kernel"
2557 depends on SYS_SUPPORTS_RELOCATABLE
2558 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
2559 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
2560 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
2561 CPU_P5600 || CAVIUM_OCTEON_SOC || \
2564 This builds a kernel image that retains relocation information
2565 so it can be loaded someplace besides the default 1MB.
2566 The relocations make the kernel binary about 15% larger,
2567 but are discarded at runtime
2569 config RELOCATION_TABLE_SIZE
2570 hex "Relocation table size"
2571 depends on RELOCATABLE
2572 range 0x0 0x01000000
2573 default "0x00200000" if CPU_LOONGSON64
2574 default "0x00100000"
2576 A table of relocation data will be appended to the kernel binary
2577 and parsed at boot to fix up the relocated kernel.
2579 This option allows the amount of space reserved for the table to be
2580 adjusted, although the default of 1Mb should be ok in most cases.
2582 The build will fail and a valid size suggested if this is too small.
2584 If unsure, leave at the default value.
2586 config RANDOMIZE_BASE
2587 bool "Randomize the address of the kernel image"
2588 depends on RELOCATABLE
2590 Randomizes the physical and virtual address at which the
2591 kernel image is loaded, as a security feature that
2592 deters exploit attempts relying on knowledge of the location
2593 of kernel internals.
2595 Entropy is generated using any coprocessor 0 registers available.
2597 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2601 config RANDOMIZE_BASE_MAX_OFFSET
2602 hex "Maximum kASLR offset" if EXPERT
2603 depends on RANDOMIZE_BASE
2604 range 0x0 0x40000000 if EVA || 64BIT
2605 range 0x0 0x08000000
2606 default "0x01000000"
2608 When kASLR is active, this provides the maximum offset that will
2609 be applied to the kernel image. It should be set according to the
2610 amount of physical RAM available in the target system minus
2611 PHYSICAL_START and must be a power of 2.
2613 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2614 EVA or 64-bit. The default is 16Mb.
2621 config HW_PERF_EVENTS
2622 bool "Enable hardware performance counter support for perf events"
2623 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2626 Enable hardware performance counter support for perf events. If
2627 disabled, perf events will use software events only.
2630 bool "Enable DMI scanning"
2631 depends on MACH_LOONGSON64
2632 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2635 Enabled scanning of DMI to identify machine quirks. Say Y
2636 here unless you have verified that your setup is not
2637 affected by entries in the DMI blacklist. Required by PNP
2641 bool "Multi-Processing support"
2642 depends on SYS_SUPPORTS_SMP
2644 This enables support for systems with more than one CPU. If you have
2645 a system with only one CPU, say N. If you have a system with more
2646 than one CPU, say Y.
2648 If you say N here, the kernel will run on uni- and multiprocessor
2649 machines, but will use only one CPU of a multiprocessor machine. If
2650 you say Y here, the kernel will run on many, but not all,
2651 uniprocessor machines. On a uniprocessor machine, the kernel
2652 will run faster if you say N here.
2654 People using multiprocessor machines who say Y here should also say
2655 Y to "Enhanced Real Time Clock Support", below.
2657 See also the SMP-HOWTO available at
2658 <https://www.tldp.org/docs.html#howto>.
2660 If you don't know what to do here, say N.
2663 bool "Support for hot-pluggable CPUs"
2664 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2666 Say Y here to allow turning CPUs off and on. CPUs can be
2667 controlled through /sys/devices/system/cpu.
2668 (Note: power management support will enable this option
2669 automatically on SMP systems. )
2670 Say N if you want to disable CPU hotplug.
2675 config SYS_SUPPORTS_MIPS_CPS
2678 config SYS_SUPPORTS_SMP
2681 config NR_CPUS_DEFAULT_4
2684 config NR_CPUS_DEFAULT_8
2687 config NR_CPUS_DEFAULT_16
2690 config NR_CPUS_DEFAULT_32
2693 config NR_CPUS_DEFAULT_64
2697 int "Maximum number of CPUs (2-256)"
2700 default "4" if NR_CPUS_DEFAULT_4
2701 default "8" if NR_CPUS_DEFAULT_8
2702 default "16" if NR_CPUS_DEFAULT_16
2703 default "32" if NR_CPUS_DEFAULT_32
2704 default "64" if NR_CPUS_DEFAULT_64
2706 This allows you to specify the maximum number of CPUs which this
2707 kernel will support. The maximum supported value is 32 for 32-bit
2708 kernel and 64 for 64-bit kernels; the minimum value which makes
2709 sense is 1 for Qemu (useful only for kernel debugging purposes)
2710 and 2 for all others.
2712 This is purely to save memory - each supported CPU adds
2713 approximately eight kilobytes to the kernel image. For best
2714 performance should round up your number of processors to the next
2717 config MIPS_PERF_SHARED_TC_COUNTERS
2720 config MIPS_NR_CPU_NR_MAP_1024
2723 config MIPS_NR_CPU_NR_MAP
2726 default 1024 if MIPS_NR_CPU_NR_MAP_1024
2727 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2730 # Timer Interrupt Frequency Configuration
2734 prompt "Timer frequency"
2737 Allows the configuration of the timer frequency.
2740 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2743 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2746 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2749 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2752 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2755 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2758 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2761 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2765 config SYS_SUPPORTS_24HZ
2768 config SYS_SUPPORTS_48HZ
2771 config SYS_SUPPORTS_100HZ
2774 config SYS_SUPPORTS_128HZ
2777 config SYS_SUPPORTS_250HZ
2780 config SYS_SUPPORTS_256HZ
2783 config SYS_SUPPORTS_1000HZ
2786 config SYS_SUPPORTS_1024HZ
2789 config SYS_SUPPORTS_ARBIT_HZ
2791 default y if !SYS_SUPPORTS_24HZ && \
2792 !SYS_SUPPORTS_48HZ && \
2793 !SYS_SUPPORTS_100HZ && \
2794 !SYS_SUPPORTS_128HZ && \
2795 !SYS_SUPPORTS_250HZ && \
2796 !SYS_SUPPORTS_256HZ && \
2797 !SYS_SUPPORTS_1000HZ && \
2798 !SYS_SUPPORTS_1024HZ
2804 default 100 if HZ_100
2805 default 128 if HZ_128
2806 default 250 if HZ_250
2807 default 256 if HZ_256
2808 default 1000 if HZ_1000
2809 default 1024 if HZ_1024
2812 def_bool HIGH_RES_TIMERS
2814 config ARCH_SUPPORTS_KEXEC
2817 config ARCH_SUPPORTS_CRASH_DUMP
2820 config PHYSICAL_START
2821 hex "Physical address where the kernel is loaded"
2822 default "0xffffffff84000000"
2823 depends on CRASH_DUMP
2825 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2826 If you plan to use kernel for capturing the crash dump change
2827 this value to start of the reserved region (the "X" value as
2828 specified in the "crashkernel=YM@XM" command line boot parameter
2829 passed to the panic-ed kernel).
2831 config MIPS_O32_FP64_SUPPORT
2832 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2833 depends on 32BIT || MIPS32_O32
2835 When this is enabled, the kernel will support use of 64-bit floating
2836 point registers with binaries using the O32 ABI along with the
2837 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2838 32-bit MIPS systems this support is at the cost of increasing the
2839 size and complexity of the compiled FPU emulator. Thus if you are
2840 running a MIPS32 system and know that none of your userland binaries
2841 will require 64-bit floating point, you may wish to reduce the size
2842 of your kernel & potentially improve FP emulation performance by
2845 Although binutils currently supports use of this flag the details
2846 concerning its effect upon the O32 ABI in userland are still being
2847 worked on. In order to avoid userland becoming dependent upon current
2848 behaviour before the details have been finalised, this option should
2849 be considered experimental and only enabled by those working upon
2857 select OF_EARLY_FLATTREE
2867 prompt "Kernel appended dtb support" if USE_OF
2868 default MIPS_NO_APPENDED_DTB
2870 config MIPS_NO_APPENDED_DTB
2873 Do not enable appended dtb support.
2875 config MIPS_ELF_APPENDED_DTB
2878 With this option, the boot code will look for a device tree binary
2879 DTB) included in the vmlinux ELF section .appended_dtb. By default
2880 it is empty and the DTB can be appended using binutils command
2883 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
2885 This is meant as a backward compatibility convenience for those
2886 systems with a bootloader that can't be upgraded to accommodate
2887 the documented boot protocol using a device tree.
2889 config MIPS_RAW_APPENDED_DTB
2890 bool "vmlinux.bin or vmlinuz.bin"
2892 With this option, the boot code will look for a device tree binary
2893 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
2894 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
2896 This is meant as a backward compatibility convenience for those
2897 systems with a bootloader that can't be upgraded to accommodate
2898 the documented boot protocol using a device tree.
2900 Beware that there is very little in terms of protection against
2901 this option being confused by leftover garbage in memory that might
2902 look like a DTB header after a reboot if no actual DTB is appended
2903 to vmlinux.bin. Do not leave this option active in a production kernel
2904 if you don't intend to always append a DTB.
2908 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2909 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2910 !MACH_LOONGSON64 && !MIPS_MALTA && \
2912 default MIPS_CMDLINE_FROM_BOOTLOADER
2914 config MIPS_CMDLINE_FROM_DTB
2916 bool "Dtb kernel arguments if available"
2918 config MIPS_CMDLINE_DTB_EXTEND
2920 bool "Extend dtb kernel arguments with bootloader arguments"
2922 config MIPS_CMDLINE_FROM_BOOTLOADER
2923 bool "Bootloader kernel arguments if available"
2925 config MIPS_CMDLINE_BUILTIN_EXTEND
2926 depends on CMDLINE_BOOL
2927 bool "Extend builtin kernel arguments with bootloader arguments"
2932 config LOCKDEP_SUPPORT
2936 config STACKTRACE_SUPPORT
2940 config PGTABLE_LEVELS
2942 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
2943 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
2946 config MIPS_AUTO_PFN_OFFSET
2949 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2951 config PCI_DRIVERS_GENERIC
2952 select PCI_DOMAINS_GENERIC if PCI
2955 config PCI_DRIVERS_LEGACY
2956 def_bool !PCI_DRIVERS_GENERIC
2957 select NO_GENERIC_PCI_IOPORT_MAP
2958 select PCI_DOMAINS if PCI
2961 # ISA support is now enabled via select. Too many systems still have the one
2962 # or other ISA chip on the board that users don't know about so don't expect
2963 # users to choose the right thing ...
2969 bool "TURBOchannel support"
2970 depends on MACH_DECSTATION
2972 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
2973 processors. TURBOchannel programming specifications are available
2975 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
2977 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
2978 Linux driver support status is documented at:
2979 <http://www.linux-mips.org/wiki/DECstation>
2985 config ARCH_MMAP_RND_BITS_MIN
2989 config ARCH_MMAP_RND_BITS_MAX
2993 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2996 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3003 select MIPS_EXTERNAL_TIMER
3009 config MIPS32_COMPAT
3016 bool "Kernel support for o32 binaries"
3018 select ARCH_WANT_OLD_COMPAT_IPC
3020 select MIPS32_COMPAT
3022 Select this option if you want to run o32 binaries. These are pure
3023 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3024 existing binaries are in this format.
3029 bool "Kernel support for n32 binaries"
3031 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3033 select MIPS32_COMPAT
3035 Select this option if you want to run n32 binaries. These are
3036 64-bit binaries using 32-bit quantities for addressing and certain
3037 data that would normally be 64-bit. They are used in special
3042 config CC_HAS_MNO_BRANCH_LIKELY
3044 depends on $(cc-option,-mno-branch-likely)
3046 # https://github.com/llvm/llvm-project/issues/61045
3047 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
3048 def_bool y if CC_IS_CLANG
3050 menu "Power management options"
3052 config ARCH_HIBERNATION_POSSIBLE
3054 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3056 config ARCH_SUSPEND_POSSIBLE
3058 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3060 source "kernel/power/Kconfig"
3064 config MIPS_EXTERNAL_TIMER
3067 menu "CPU Power Management"
3069 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3070 source "drivers/cpufreq/Kconfig"
3071 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3073 source "drivers/cpuidle/Kconfig"
3077 source "arch/mips/kvm/Kconfig"
3079 source "arch/mips/vdso/Kconfig"