1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CPU_FINALIZE_INIT
8 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
9 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
10 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_STRNCPY_FROM_USER
15 select ARCH_HAS_STRNLEN_USER
16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
17 select ARCH_HAS_UBSAN_SANITIZE_ALL
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_KEEP_MEMBLOCK
20 select ARCH_USE_BUILTIN_BSWAP
21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
22 select ARCH_USE_MEMTEST
23 select ARCH_USE_QUEUED_RWLOCKS
24 select ARCH_USE_QUEUED_SPINLOCKS
25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
27 select ARCH_WANT_IPC_PARSE_VERSION
28 select ARCH_WANT_LD_ORPHAN_WARN
29 select BUILDTIME_TABLE_SORT
30 select CLONE_BACKWARDS
31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
32 select CPU_PM if CPU_IDLE
33 select GENERIC_ATOMIC64 if !64BIT
34 select GENERIC_CMOS_UPDATE
35 select GENERIC_CPU_AUTOPROBE
36 select GENERIC_GETTIMEOFDAY
38 select GENERIC_IRQ_PROBE
39 select GENERIC_IRQ_SHOW
40 select GENERIC_ISA_DMA if EISA
41 select GENERIC_LIB_ASHLDI3
42 select GENERIC_LIB_ASHRDI3
43 select GENERIC_LIB_CMPDI2
44 select GENERIC_LIB_LSHRDI3
45 select GENERIC_LIB_UCMPDI2
46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
47 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_IDLE_POLL_SETUP
49 select GENERIC_TIME_VSYSCALL
50 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
51 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
52 select HAVE_ARCH_COMPILER_H
53 select HAVE_ARCH_JUMP_LABEL
54 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
55 select HAVE_ARCH_MMAP_RND_BITS if MMU
56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
57 select HAVE_ARCH_SECCOMP_FILTER
58 select HAVE_ARCH_TRACEHOOK
59 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
60 select HAVE_ASM_MODVERSIONS
61 select HAVE_CONTEXT_TRACKING_USER
63 select HAVE_C_RECORDMCOUNT
64 select HAVE_DEBUG_KMEMLEAK
65 select HAVE_DEBUG_STACKOVERFLOW
66 select HAVE_DMA_CONTIGUOUS
67 select HAVE_DYNAMIC_FTRACE
68 select HAVE_EBPF_JIT if !CPU_MICROMIPS
69 select HAVE_EXIT_THREAD
71 select HAVE_FTRACE_MCOUNT_RECORD
72 select HAVE_FUNCTION_GRAPH_TRACER
73 select HAVE_FUNCTION_TRACER
74 select HAVE_GCC_PLUGINS
75 select HAVE_GENERIC_VDSO
76 select HAVE_IOREMAP_PROT
77 select HAVE_IRQ_EXIT_ON_IRQ_STACK
78 select HAVE_IRQ_TIME_ACCOUNTING
80 select HAVE_KRETPROBES
81 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
82 select HAVE_MOD_ARCH_SPECIFIC
84 select HAVE_PERF_EVENTS
86 select HAVE_PERF_USER_STACK_DUMP
87 select HAVE_REGS_AND_STACK_ACCESS_API
89 select HAVE_SPARSE_SYSCALL_NR
90 select HAVE_STACKPROTECTOR
91 select HAVE_SYSCALL_TRACEPOINTS
92 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
93 select IRQ_FORCED_THREADING
95 select LOCK_MM_AND_FIND_VMA
96 select MODULES_USE_ELF_REL if MODULES
97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
98 select PERF_USE_VMALLOC
99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
101 select SYSCTL_EXCEPTION_TRACE
102 select TRACE_IRQFLAGS_SUPPORT
103 select ARCH_HAS_ELFCORE_COMPAT
104 select HAVE_ARCH_KCSAN if 64BIT
106 config MIPS_FIXUP_BIGPHYS_ADDR
114 select SYS_SUPPORTS_32BIT_KERNEL
115 select SYS_SUPPORTS_LITTLE_ENDIAN
116 select SYS_SUPPORTS_ZBOOT
117 select DMA_NONCOHERENT
122 select GENERIC_IRQ_CHIP
123 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
125 select CPU_SUPPORTS_CPUFREQ
126 select MIPS_EXTERNAL_TIMER
128 menu "Machine selection"
132 default MIPS_GENERIC_KERNEL
134 config MIPS_GENERIC_KERNEL
135 bool "Generic board-agnostic MIPS kernel"
140 select CLKSRC_MIPS_GIC
142 select CPU_MIPSR2_IRQ_EI
143 select CPU_MIPSR2_IRQ_VI
145 select DMA_NONCOHERENT
148 select MIPS_AUTO_PFN_OFFSET
149 select MIPS_CPU_SCACHE
151 select MIPS_L1_CACHE_SHIFT_7
152 select NO_EXCEPT_FILL
153 select PCI_DRIVERS_GENERIC
156 select SYS_HAS_CPU_MIPS32_R1
157 select SYS_HAS_CPU_MIPS32_R2
158 select SYS_HAS_CPU_MIPS32_R5
159 select SYS_HAS_CPU_MIPS32_R6
160 select SYS_HAS_CPU_MIPS64_R1
161 select SYS_HAS_CPU_MIPS64_R2
162 select SYS_HAS_CPU_MIPS64_R5
163 select SYS_HAS_CPU_MIPS64_R6
164 select SYS_SUPPORTS_32BIT_KERNEL
165 select SYS_SUPPORTS_64BIT_KERNEL
166 select SYS_SUPPORTS_BIG_ENDIAN
167 select SYS_SUPPORTS_HIGHMEM
168 select SYS_SUPPORTS_LITTLE_ENDIAN
169 select SYS_SUPPORTS_MICROMIPS
170 select SYS_SUPPORTS_MIPS16
171 select SYS_SUPPORTS_MIPS_CPS
172 select SYS_SUPPORTS_MULTITHREADING
173 select SYS_SUPPORTS_RELOCATABLE
174 select SYS_SUPPORTS_SMARTMIPS
175 select SYS_SUPPORTS_ZBOOT
177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
185 Select this to build a kernel which aims to support multiple boards,
186 generally using a flattened device tree passed from the bootloader
187 using the boot protocol defined in the UHI (Unified Hosting
188 Interface) specification.
191 bool "Alchemy processor based machines"
192 select PHYS_ADDR_T_64BIT
196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
198 select SYS_HAS_CPU_MIPS32_R1
199 select SYS_SUPPORTS_32BIT_KERNEL
200 select SYS_SUPPORTS_APM_EMULATION
202 select SYS_SUPPORTS_ZBOOT
206 bool "Atheros AR231x/AR531x SoC support"
209 select DMA_NONCOHERENT
212 select SYS_HAS_CPU_MIPS32_R1
213 select SYS_SUPPORTS_BIG_ENDIAN
214 select SYS_SUPPORTS_32BIT_KERNEL
215 select SYS_HAS_EARLY_PRINTK
217 Support for Atheros AR231x and Atheros AR531x based boards
220 bool "Atheros AR71XX/AR724X/AR913X based boards"
221 select ARCH_HAS_RESET_CONTROLLER
225 select DMA_NONCOHERENT
230 select SYS_HAS_CPU_MIPS32_R2
231 select SYS_HAS_EARLY_PRINTK
232 select SYS_SUPPORTS_32BIT_KERNEL
233 select SYS_SUPPORTS_BIG_ENDIAN
234 select SYS_SUPPORTS_MIPS16
235 select SYS_SUPPORTS_ZBOOT_UART_PROM
237 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
239 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
242 bool "Broadcom Generic BMIPS kernel"
243 select ARCH_HAS_RESET_CONTROLLER
244 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
246 select NO_EXCEPT_FILL
252 select BCM6345_L1_IRQ
253 select BCM7038_L1_IRQ
254 select BCM7120_L2_IRQ
255 select BRCMSTB_L2_IRQ
257 select DMA_NONCOHERENT
258 select SYS_SUPPORTS_32BIT_KERNEL
259 select SYS_SUPPORTS_LITTLE_ENDIAN
260 select SYS_SUPPORTS_BIG_ENDIAN
261 select SYS_SUPPORTS_HIGHMEM
262 select SYS_HAS_CPU_BMIPS32_3300
263 select SYS_HAS_CPU_BMIPS4350
264 select SYS_HAS_CPU_BMIPS4380
265 select SYS_HAS_CPU_BMIPS5000
267 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
268 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
269 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
270 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
271 select HARDIRQS_SW_RESEND
273 select PCI_DRIVERS_GENERIC
276 Build a generic DT-based kernel image that boots on select
277 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
278 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
279 must be set appropriately for your board.
282 bool "Broadcom BCM47XX based boards"
286 select DMA_NONCOHERENT
289 select SYS_HAS_CPU_MIPS32_R1
290 select NO_EXCEPT_FILL
291 select SYS_SUPPORTS_32BIT_KERNEL
292 select SYS_SUPPORTS_LITTLE_ENDIAN
293 select SYS_SUPPORTS_MIPS16
294 select SYS_SUPPORTS_ZBOOT
295 select SYS_HAS_EARLY_PRINTK
296 select USE_GENERIC_EARLY_PRINTK_8250
298 select LEDS_GPIO_REGISTER
301 select BCM47XX_SSB if !BCM47XX_BCMA
303 Support for BCM47XX based boards
306 bool "Broadcom BCM63XX based boards"
311 select DMA_NONCOHERENT
313 select SYS_SUPPORTS_32BIT_KERNEL
314 select SYS_SUPPORTS_BIG_ENDIAN
315 select SYS_HAS_EARLY_PRINTK
316 select SYS_HAS_CPU_BMIPS32_3300
317 select SYS_HAS_CPU_BMIPS4350
318 select SYS_HAS_CPU_BMIPS4380
321 select MIPS_L1_CACHE_SHIFT_4
322 select HAVE_LEGACY_CLK
324 Support for BCM63XX based boards
331 select DMA_NONCOHERENT
337 select PCI_GT64XXX_PCI0
338 select SYS_HAS_CPU_NEVADA
339 select SYS_HAS_EARLY_PRINTK
340 select SYS_SUPPORTS_32BIT_KERNEL
341 select SYS_SUPPORTS_64BIT_KERNEL
342 select SYS_SUPPORTS_LITTLE_ENDIAN
343 select USE_GENERIC_EARLY_PRINTK_8250
345 config MACH_DECSTATION
349 select CEVT_R4K if CPU_R4X00
351 select CSRC_R4K if CPU_R4X00
352 select CPU_DADDI_WORKAROUNDS if 64BIT
353 select CPU_R4000_WORKAROUNDS if 64BIT
354 select CPU_R4400_WORKAROUNDS if 64BIT
355 select DMA_NONCOHERENT
358 select SYS_HAS_CPU_R3000
359 select SYS_HAS_CPU_R4X00
360 select SYS_SUPPORTS_32BIT_KERNEL
361 select SYS_SUPPORTS_64BIT_KERNEL
362 select SYS_SUPPORTS_LITTLE_ENDIAN
363 select SYS_SUPPORTS_128HZ
364 select SYS_SUPPORTS_256HZ
365 select SYS_SUPPORTS_1024HZ
366 select MIPS_L1_CACHE_SHIFT_4
368 This enables support for DEC's MIPS based workstations. For details
369 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
370 DECstation porting pages on <http://decstation.unix-ag.org/>.
372 If you have one of the following DECstation Models you definitely
373 want to choose R4xx0 for the CPU Type:
380 otherwise choose R3000.
383 bool "Jazz family of machines"
386 select ARCH_MIGHT_HAVE_PC_PARPORT
387 select ARCH_MIGHT_HAVE_PC_SERIO
391 select ARCH_MAY_HAVE_PC_FDC
394 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
395 select GENERIC_ISA_DMA
396 select HAVE_PCSPKR_PLATFORM
401 select SYS_HAS_CPU_R4X00
402 select SYS_SUPPORTS_32BIT_KERNEL
403 select SYS_SUPPORTS_64BIT_KERNEL
404 select SYS_SUPPORTS_100HZ
405 select SYS_SUPPORTS_LITTLE_ENDIAN
407 This a family of machines based on the MIPS R4030 chipset which was
408 used by several vendors to build RISC/os and Windows NT workstations.
409 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
410 Olivetti M700-10 workstations.
412 config MACH_INGENIC_SOC
413 bool "Ingenic SoC based machines"
416 select SYS_SUPPORTS_ZBOOT_UART16550
417 select CPU_SUPPORTS_CPUFREQ
418 select MIPS_EXTERNAL_TIMER
421 bool "Lantiq based platforms"
422 select DMA_NONCOHERENT
426 select NO_EXCEPT_FILL
427 select SYS_HAS_CPU_MIPS32_R1
428 select SYS_HAS_CPU_MIPS32_R2
429 select SYS_SUPPORTS_BIG_ENDIAN
430 select SYS_SUPPORTS_32BIT_KERNEL
431 select SYS_SUPPORTS_MIPS16
432 select SYS_SUPPORTS_MULTITHREADING
433 select SYS_SUPPORTS_VPE_LOADER
434 select SYS_HAS_EARLY_PRINTK
438 select HAVE_LEGACY_CLK
441 select PINCTRL_LANTIQ
442 select ARCH_HAS_RESET_CONTROLLER
443 select RESET_CONTROLLER
445 config MACH_LOONGSON32
446 bool "Loongson 32-bit family of machines"
447 select SYS_SUPPORTS_ZBOOT
449 This enables support for the Loongson-1 family of machines.
451 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
452 the Institute of Computing Technology (ICT), Chinese Academy of
455 config MACH_LOONGSON2EF
456 bool "Loongson-2E/F family of machines"
457 select SYS_SUPPORTS_ZBOOT
459 This enables the support of early Loongson-2E/F family of machines.
461 config MACH_LOONGSON64
462 bool "Loongson 64-bit family of machines"
463 select ARCH_SPARSEMEM_ENABLE
464 select ARCH_MIGHT_HAVE_PC_PARPORT
465 select ARCH_MIGHT_HAVE_PC_SERIO
466 select GENERIC_ISA_DMA_SUPPORT_BROKEN
475 select NO_EXCEPT_FILL
476 select NR_CPUS_DEFAULT_64
477 select USE_GENERIC_EARLY_PRINTK_8250
478 select PCI_DRIVERS_GENERIC
479 select SYS_HAS_CPU_LOONGSON64
480 select SYS_HAS_EARLY_PRINTK
481 select SYS_SUPPORTS_SMP
482 select SYS_SUPPORTS_HOTPLUG_CPU
483 select SYS_SUPPORTS_NUMA
484 select SYS_SUPPORTS_64BIT_KERNEL
485 select SYS_SUPPORTS_HIGHMEM
486 select SYS_SUPPORTS_LITTLE_ENDIAN
487 select SYS_SUPPORTS_ZBOOT
488 select SYS_SUPPORTS_RELOCATABLE
493 select PCI_HOST_GENERIC
494 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
496 This enables the support of Loongson-2/3 family of machines.
498 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
499 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
500 and Loongson-2F which will be removed), developed by the Institute
501 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
504 bool "MIPS Malta board"
505 select ARCH_MAY_HAVE_PC_FDC
506 select ARCH_MIGHT_HAVE_PC_PARPORT
507 select ARCH_MIGHT_HAVE_PC_SERIO
512 select CLKSRC_MIPS_GIC
515 select DMA_NONCOHERENT
516 select GENERIC_ISA_DMA
517 select HAVE_PCSPKR_PLATFORM
523 select MIPS_CPU_SCACHE
525 select MIPS_L1_CACHE_SHIFT_6
527 select PCI_GT64XXX_PCI0
530 select SYS_HAS_CPU_MIPS32_R1
531 select SYS_HAS_CPU_MIPS32_R2
532 select SYS_HAS_CPU_MIPS32_R3_5
533 select SYS_HAS_CPU_MIPS32_R5
534 select SYS_HAS_CPU_MIPS32_R6
535 select SYS_HAS_CPU_MIPS64_R1
536 select SYS_HAS_CPU_MIPS64_R2
537 select SYS_HAS_CPU_MIPS64_R6
538 select SYS_HAS_CPU_NEVADA
539 select SYS_HAS_CPU_RM7000
540 select SYS_SUPPORTS_32BIT_KERNEL
541 select SYS_SUPPORTS_64BIT_KERNEL
542 select SYS_SUPPORTS_BIG_ENDIAN
543 select SYS_SUPPORTS_HIGHMEM
544 select SYS_SUPPORTS_LITTLE_ENDIAN
545 select SYS_SUPPORTS_MICROMIPS
546 select SYS_SUPPORTS_MIPS16
547 select SYS_SUPPORTS_MIPS_CPS
548 select SYS_SUPPORTS_MULTITHREADING
549 select SYS_SUPPORTS_RELOCATABLE
550 select SYS_SUPPORTS_SMARTMIPS
551 select SYS_SUPPORTS_VPE_LOADER
552 select SYS_SUPPORTS_ZBOOT
554 select WAR_ICACHE_REFILLS
555 select ZONE_DMA32 if 64BIT
557 This enables support for the MIPS Technologies Malta evaluation
561 bool "Microchip PIC32 Family"
563 This enables support for the Microchip PIC32 family of platforms.
565 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
568 config MACH_NINTENDO64
569 bool "Nintendo 64 console"
572 select SYS_HAS_CPU_R4300
573 select SYS_SUPPORTS_BIG_ENDIAN
574 select SYS_SUPPORTS_ZBOOT
575 select SYS_SUPPORTS_32BIT_KERNEL
576 select SYS_SUPPORTS_64BIT_KERNEL
577 select DMA_NONCOHERENT
581 bool "Ralink based machines"
586 select DMA_NONCOHERENT
589 select SYS_HAS_CPU_MIPS32_R2
590 select SYS_SUPPORTS_32BIT_KERNEL
591 select SYS_SUPPORTS_LITTLE_ENDIAN
592 select SYS_SUPPORTS_MIPS16
593 select SYS_SUPPORTS_ZBOOT
594 select SYS_HAS_EARLY_PRINTK
595 select ARCH_HAS_RESET_CONTROLLER
596 select RESET_CONTROLLER
598 config MACH_REALTEK_RTL
599 bool "Realtek RTL838x/RTL839x based machines"
601 select DMA_NONCOHERENT
605 select SYS_HAS_CPU_MIPS32_R1
606 select SYS_HAS_CPU_MIPS32_R2
607 select SYS_SUPPORTS_BIG_ENDIAN
608 select SYS_SUPPORTS_32BIT_KERNEL
609 select SYS_SUPPORTS_MIPS16
610 select SYS_SUPPORTS_MULTITHREADING
611 select SYS_SUPPORTS_VPE_LOADER
617 bool "SGI IP22 (Indy/Indigo2)"
622 select ARCH_MIGHT_HAVE_PC_SERIO
626 select DEFAULT_SGI_PARTITION
627 select DMA_NONCOHERENT
631 select IP22_CPU_SCACHE
633 select GENERIC_ISA_DMA_SUPPORT_BROKEN
635 select SGI_HAS_INDYDOG
641 select SYS_HAS_CPU_R4X00
642 select SYS_HAS_CPU_R5000
643 select SYS_HAS_EARLY_PRINTK
644 select SYS_SUPPORTS_32BIT_KERNEL
645 select SYS_SUPPORTS_64BIT_KERNEL
646 select SYS_SUPPORTS_BIG_ENDIAN
647 select WAR_R4600_V1_INDEX_ICACHEOP
648 select WAR_R4600_V1_HIT_CACHEOP
649 select WAR_R4600_V2_HIT_CACHEOP
650 select MIPS_L1_CACHE_SHIFT_7
652 This are the SGI Indy, Challenge S and Indigo2, as well as certain
653 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
654 that runs on these, say Y here.
657 bool "SGI IP27 (Origin200/2000)"
658 select ARCH_HAS_PHYS_TO_DMA
659 select ARCH_SPARSEMEM_ENABLE
662 select ARC_CMDLINE_ONLY
664 select DEFAULT_SGI_PARTITION
666 select SYS_HAS_EARLY_PRINTK
669 select IRQ_DOMAIN_HIERARCHY
670 select NR_CPUS_DEFAULT_64
671 select PCI_DRIVERS_GENERIC
672 select PCI_XTALK_BRIDGE
673 select SYS_HAS_CPU_R10000
674 select SYS_SUPPORTS_64BIT_KERNEL
675 select SYS_SUPPORTS_BIG_ENDIAN
676 select SYS_SUPPORTS_NUMA
677 select SYS_SUPPORTS_SMP
678 select WAR_R10000_LLSC
679 select MIPS_L1_CACHE_SHIFT_7
681 select HAVE_ARCH_NODEDATA_EXTENSION
683 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
684 workstations. To compile a Linux kernel that runs on these, say Y
688 bool "SGI IP28 (Indigo2 R10k)"
693 select ARCH_MIGHT_HAVE_PC_SERIO
697 select DEFAULT_SGI_PARTITION
698 select DMA_NONCOHERENT
699 select GENERIC_ISA_DMA_SUPPORT_BROKEN
705 select SGI_HAS_INDYDOG
711 select SYS_HAS_CPU_R10000
712 select SYS_HAS_EARLY_PRINTK
713 select SYS_SUPPORTS_64BIT_KERNEL
714 select SYS_SUPPORTS_BIG_ENDIAN
715 select WAR_R10000_LLSC
716 select MIPS_L1_CACHE_SHIFT_7
718 This is the SGI Indigo2 with R10000 processor. To compile a Linux
719 kernel that runs on these, say Y here.
722 bool "SGI IP30 (Octane/Octane2)"
723 select ARCH_HAS_PHYS_TO_DMA
730 select SYNC_R4K if SMP
734 select IRQ_DOMAIN_HIERARCHY
735 select PCI_DRIVERS_GENERIC
736 select PCI_XTALK_BRIDGE
737 select SYS_HAS_EARLY_PRINTK
738 select SYS_HAS_CPU_R10000
739 select SYS_SUPPORTS_64BIT_KERNEL
740 select SYS_SUPPORTS_BIG_ENDIAN
741 select SYS_SUPPORTS_SMP
742 select WAR_R10000_LLSC
743 select MIPS_L1_CACHE_SHIFT_7
746 These are the SGI Octane and Octane2 graphics workstations. To
747 compile a Linux kernel that runs on these, say Y here.
753 select ARCH_HAS_PHYS_TO_DMA
759 select DMA_NONCOHERENT
762 select R5000_CPU_SCACHE
763 select RM7000_CPU_SCACHE
764 select SYS_HAS_CPU_R5000
765 select SYS_HAS_CPU_R10000 if BROKEN
766 select SYS_HAS_CPU_RM7000
767 select SYS_HAS_CPU_NEVADA
768 select SYS_SUPPORTS_64BIT_KERNEL
769 select SYS_SUPPORTS_BIG_ENDIAN
770 select WAR_ICACHE_REFILLS
772 If you want this kernel to run on SGI O2 workstation, say Y here.
775 bool "Sibyte BCM91125C-CRhone"
777 select SIBYTE_BCM1125
779 select SYS_HAS_CPU_SB1
780 select SYS_SUPPORTS_BIG_ENDIAN
781 select SYS_SUPPORTS_HIGHMEM
782 select SYS_SUPPORTS_LITTLE_ENDIAN
785 bool "Sibyte BCM91125E-Rhone"
789 select SYS_HAS_CPU_SB1
790 select SYS_SUPPORTS_BIG_ENDIAN
791 select SYS_SUPPORTS_LITTLE_ENDIAN
794 bool "Sibyte BCM91250A-SWARM"
796 select HAVE_PATA_PLATFORM
799 select SYS_HAS_CPU_SB1
800 select SYS_SUPPORTS_BIG_ENDIAN
801 select SYS_SUPPORTS_HIGHMEM
802 select SYS_SUPPORTS_LITTLE_ENDIAN
803 select ZONE_DMA32 if 64BIT
804 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
806 config SIBYTE_LITTLESUR
807 bool "Sibyte BCM91250C2-LittleSur"
809 select HAVE_PATA_PLATFORM
812 select SYS_HAS_CPU_SB1
813 select SYS_SUPPORTS_BIG_ENDIAN
814 select SYS_SUPPORTS_HIGHMEM
815 select SYS_SUPPORTS_LITTLE_ENDIAN
816 select ZONE_DMA32 if 64BIT
818 config SIBYTE_SENTOSA
819 bool "Sibyte BCM91250E-Sentosa"
823 select SYS_HAS_CPU_SB1
824 select SYS_SUPPORTS_BIG_ENDIAN
825 select SYS_SUPPORTS_LITTLE_ENDIAN
826 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
829 bool "Sibyte BCM91480B-BigSur"
831 select NR_CPUS_DEFAULT_4
832 select SIBYTE_BCM1x80
834 select SYS_HAS_CPU_SB1
835 select SYS_SUPPORTS_BIG_ENDIAN
836 select SYS_SUPPORTS_HIGHMEM
837 select SYS_SUPPORTS_LITTLE_ENDIAN
838 select ZONE_DMA32 if 64BIT
839 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
842 bool "SNI RM200/300/400"
845 select FW_ARC if CPU_LITTLE_ENDIAN
846 select FW_ARC32 if CPU_LITTLE_ENDIAN
847 select FW_SNIPROM if CPU_BIG_ENDIAN
848 select ARCH_MAY_HAVE_PC_FDC
849 select ARCH_MIGHT_HAVE_PC_PARPORT
850 select ARCH_MIGHT_HAVE_PC_SERIO
854 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
855 select DMA_NONCOHERENT
856 select GENERIC_ISA_DMA
858 select HAVE_PCSPKR_PLATFORM
864 select MIPS_L1_CACHE_SHIFT_6
865 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
866 select SYS_HAS_CPU_R4X00
867 select SYS_HAS_CPU_R5000
868 select SYS_HAS_CPU_R10000
869 select R5000_CPU_SCACHE
870 select SYS_HAS_EARLY_PRINTK
871 select SYS_SUPPORTS_32BIT_KERNEL
872 select SYS_SUPPORTS_64BIT_KERNEL
873 select SYS_SUPPORTS_BIG_ENDIAN
874 select SYS_SUPPORTS_HIGHMEM
875 select SYS_SUPPORTS_LITTLE_ENDIAN
876 select WAR_R4600_V2_HIT_CACHEOP
878 The SNI RM200/300/400 are MIPS-based machines manufactured by
879 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
880 Technology and now in turn merged with Fujitsu. Say Y here to
881 support this machine type.
884 bool "Toshiba TX49 series based machines"
885 select WAR_TX49XX_ICACHE_INDEX_INV
887 config MIKROTIK_RB532
888 bool "Mikrotik RB532 boards"
891 select DMA_NONCOHERENT
894 select SYS_HAS_CPU_MIPS32_R1
895 select SYS_SUPPORTS_32BIT_KERNEL
896 select SYS_SUPPORTS_LITTLE_ENDIAN
900 select MIPS_L1_CACHE_SHIFT_4
902 Support the Mikrotik(tm) RouterBoard 532 series,
903 based on the IDT RC32434 SoC.
905 config CAVIUM_OCTEON_SOC
906 bool "Cavium Networks Octeon SoC based boards"
908 select ARCH_HAS_PHYS_TO_DMA
910 select PHYS_ADDR_T_64BIT
911 select SYS_SUPPORTS_64BIT_KERNEL
912 select SYS_SUPPORTS_BIG_ENDIAN
914 select EDAC_ATOMIC_SCRUB
915 select SYS_SUPPORTS_LITTLE_ENDIAN
916 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
917 select SYS_HAS_EARLY_PRINTK
918 select SYS_HAS_CPU_CAVIUM_OCTEON
920 select HAVE_PLAT_DELAY
921 select HAVE_PLAT_FW_INIT_CMDLINE
922 select HAVE_PLAT_MEMCPY
926 select ARCH_SPARSEMEM_ENABLE
927 select SYS_SUPPORTS_SMP
928 select NR_CPUS_DEFAULT_64
929 select MIPS_NR_CPU_NR_MAP_1024
932 select MTD_COMPLEX_MAPPINGS
934 select SYS_SUPPORTS_RELOCATABLE
936 This option supports all of the Octeon reference boards from Cavium
937 Networks. It builds a kernel that dynamically determines the Octeon
938 CPU type and supports all known board reference implementations.
939 Some of the supported boards are:
946 Say Y here for most Octeon reference boards.
950 source "arch/mips/alchemy/Kconfig"
951 source "arch/mips/ath25/Kconfig"
952 source "arch/mips/ath79/Kconfig"
953 source "arch/mips/bcm47xx/Kconfig"
954 source "arch/mips/bcm63xx/Kconfig"
955 source "arch/mips/bmips/Kconfig"
956 source "arch/mips/generic/Kconfig"
957 source "arch/mips/ingenic/Kconfig"
958 source "arch/mips/jazz/Kconfig"
959 source "arch/mips/lantiq/Kconfig"
960 source "arch/mips/pic32/Kconfig"
961 source "arch/mips/ralink/Kconfig"
962 source "arch/mips/sgi-ip27/Kconfig"
963 source "arch/mips/sibyte/Kconfig"
964 source "arch/mips/txx9/Kconfig"
965 source "arch/mips/cavium-octeon/Kconfig"
966 source "arch/mips/loongson2ef/Kconfig"
967 source "arch/mips/loongson32/Kconfig"
968 source "arch/mips/loongson64/Kconfig"
972 config GENERIC_HWEIGHT
976 config GENERIC_CALIBRATE_DELAY
980 config SCHED_OMIT_FRAME_POINTER
985 # Select some configuration options automatically based on user selections.
990 config ARCH_MAY_HAVE_PC_FDC
1021 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1027 config MIPS_CLOCK_VSYSCALL
1028 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
1037 config ARCH_SUPPORTS_UPROBES
1040 config DMA_NONCOHERENT
1043 # MIPS allows mixing "slightly different" Cacheability and Coherency
1044 # Attribute bits. It is believed that the uncached access through
1045 # KSEG1 and the implementation specific "uncached accelerated" used
1046 # by pgprot_writcombine can be mixed, and the latter sometimes provides
1047 # significant advantages.
1049 select ARCH_HAS_SETUP_DMA_OPS
1050 select ARCH_HAS_DMA_WRITE_COMBINE
1051 select ARCH_HAS_DMA_PREP_COHERENT
1052 select ARCH_HAS_SYNC_DMA_FOR_CPU
1053 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
1054 select ARCH_HAS_DMA_SET_UNCACHED
1055 select DMA_NONCOHERENT_MMAP
1056 select NEED_DMA_MAP_STATE
1058 config SYS_HAS_EARLY_PRINTK
1061 config SYS_SUPPORTS_HOTPLUG_CPU
1064 config MIPS_BONITO64
1073 config NO_IOPORT_MAP
1077 def_bool CPU_NO_LOAD_STORE_LR
1079 config GENERIC_ISA_DMA
1081 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
1084 config GENERIC_ISA_DMA_SUPPORT_BROKEN
1086 select GENERIC_ISA_DMA
1088 config HAVE_PLAT_DELAY
1091 config HAVE_PLAT_FW_INIT_CMDLINE
1094 config HAVE_PLAT_MEMCPY
1100 config SYS_SUPPORTS_RELOCATABLE
1103 Selected if the platform supports relocating the kernel.
1104 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1105 to allow access to command line and entropy sources.
1108 # Endianness selection. Sufficiently obscure so many users don't know what to
1109 # answer,so we try hard to limit the available choices. Also the use of a
1110 # choice statement should be more obvious to the user.
1113 prompt "Endianness selection"
1115 Some MIPS machines can be configured for either little or big endian
1116 byte order. These modes require different kernels and a different
1117 Linux distribution. In general there is one preferred byteorder for a
1118 particular system but some systems are just as commonly used in the
1119 one or the other endianness.
1121 config CPU_BIG_ENDIAN
1123 depends on SYS_SUPPORTS_BIG_ENDIAN
1125 config CPU_LITTLE_ENDIAN
1126 bool "Little endian"
1127 depends on SYS_SUPPORTS_LITTLE_ENDIAN
1134 config SYS_SUPPORTS_APM_EMULATION
1137 config SYS_SUPPORTS_BIG_ENDIAN
1140 config SYS_SUPPORTS_LITTLE_ENDIAN
1143 config MIPS_HUGE_TLB_SUPPORT
1144 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
1152 config PCI_GT64XXX_PCI0
1155 config PCI_XTALK_BRIDGE
1158 config NO_EXCEPT_FILL
1164 config SWAP_IO_SPACE
1167 config SGI_HAS_INDYDOG
1179 config SGI_HAS_ZILOG
1182 config SGI_HAS_I8042
1185 config DEFAULT_SGI_PARTITION
1197 config MIPS_L1_CACHE_SHIFT_4
1200 config MIPS_L1_CACHE_SHIFT_5
1203 config MIPS_L1_CACHE_SHIFT_6
1206 config MIPS_L1_CACHE_SHIFT_7
1209 config MIPS_L1_CACHE_SHIFT
1211 default "7" if MIPS_L1_CACHE_SHIFT_7
1212 default "6" if MIPS_L1_CACHE_SHIFT_6
1213 default "5" if MIPS_L1_CACHE_SHIFT_5
1214 default "4" if MIPS_L1_CACHE_SHIFT_4
1217 config ARC_CMDLINE_ONLY
1221 bool "ARC console support"
1222 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
1236 menu "CPU selection"
1242 config CPU_LOONGSON64
1243 bool "Loongson 64-bit CPU"
1244 depends on SYS_HAS_CPU_LOONGSON64
1245 select ARCH_HAS_PHYS_TO_DMA
1247 select CPU_HAS_PREFETCH
1248 select CPU_SUPPORTS_64BIT_KERNEL
1249 select CPU_SUPPORTS_HIGHMEM
1250 select CPU_SUPPORTS_HUGEPAGES
1251 select CPU_SUPPORTS_MSA
1252 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
1253 select CPU_MIPSR2_IRQ_VI
1254 select WEAK_ORDERING
1255 select WEAK_REORDERING_BEYOND_LLSC
1256 select MIPS_ASID_BITS_VARIABLE
1257 select MIPS_PGD_C0_CONTEXT
1258 select MIPS_L1_CACHE_SHIFT_6
1259 select MIPS_FP_SUPPORT
1264 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1265 cores implements the MIPS64R2 instruction set with many extensions,
1266 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1267 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1268 Loongson-2E/2F is not covered here and will be removed in future.
1270 config LOONGSON3_ENHANCEMENT
1271 bool "New Loongson-3 CPU Enhancements"
1273 depends on CPU_LOONGSON64
1275 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1276 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1277 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1278 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1279 Fast TLB refill support, etc.
1281 This option enable those enhancements which are not probed at run
1282 time. If you want a generic kernel to run on all Loongson 3 machines,
1283 please say 'N' here. If you want a high-performance kernel to run on
1284 new Loongson-3 machines only, please say 'Y' here.
1286 config CPU_LOONGSON3_WORKAROUNDS
1287 bool "Loongson-3 LLSC Workarounds"
1289 depends on CPU_LOONGSON64
1291 Loongson-3 processors have the llsc issues which require workarounds.
1292 Without workarounds the system may hang unexpectedly.
1294 Say Y, unless you know what you are doing.
1296 config CPU_LOONGSON3_CPUCFG_EMULATION
1297 bool "Emulate the CPUCFG instruction on older Loongson cores"
1299 depends on CPU_LOONGSON64
1301 Loongson-3A R4 and newer have the CPUCFG instruction available for
1302 userland to query CPU capabilities, much like CPUID on x86. This
1303 option provides emulation of the instruction on older Loongson
1304 cores, back to Loongson-3A1000.
1306 If unsure, please say Y.
1308 config CPU_LOONGSON2E
1310 depends on SYS_HAS_CPU_LOONGSON2E
1311 select CPU_LOONGSON2EF
1313 The Loongson 2E processor implements the MIPS III instruction set
1314 with many extensions.
1316 It has an internal FPGA northbridge, which is compatible to
1319 config CPU_LOONGSON2F
1321 depends on SYS_HAS_CPU_LOONGSON2F
1322 select CPU_LOONGSON2EF
1324 The Loongson 2F processor implements the MIPS III instruction set
1325 with many extensions.
1327 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1328 have a similar programming interface with FPGA northbridge used in
1331 config CPU_LOONGSON1B
1333 depends on SYS_HAS_CPU_LOONGSON1B
1334 select CPU_LOONGSON32
1335 select LEDS_GPIO_REGISTER
1337 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1338 Release 1 instruction set and part of the MIPS32 Release 2
1341 config CPU_LOONGSON1C
1343 depends on SYS_HAS_CPU_LOONGSON1C
1344 select CPU_LOONGSON32
1345 select LEDS_GPIO_REGISTER
1347 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1348 Release 1 instruction set and part of the MIPS32 Release 2
1351 config CPU_MIPS32_R1
1352 bool "MIPS32 Release 1"
1353 depends on SYS_HAS_CPU_MIPS32_R1
1354 select CPU_HAS_PREFETCH
1355 select CPU_SUPPORTS_32BIT_KERNEL
1356 select CPU_SUPPORTS_HIGHMEM
1358 Choose this option to build a kernel for release 1 or later of the
1359 MIPS32 architecture. Most modern embedded systems with a 32-bit
1360 MIPS processor are based on a MIPS32 processor. If you know the
1361 specific type of processor in your system, choose those that one
1362 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1363 Release 2 of the MIPS32 architecture is available since several
1364 years so chances are you even have a MIPS32 Release 2 processor
1365 in which case you should choose CPU_MIPS32_R2 instead for better
1368 config CPU_MIPS32_R2
1369 bool "MIPS32 Release 2"
1370 depends on SYS_HAS_CPU_MIPS32_R2
1371 select CPU_HAS_PREFETCH
1372 select CPU_SUPPORTS_32BIT_KERNEL
1373 select CPU_SUPPORTS_HIGHMEM
1374 select CPU_SUPPORTS_MSA
1377 Choose this option to build a kernel for release 2 or later of the
1378 MIPS32 architecture. Most modern embedded systems with a 32-bit
1379 MIPS processor are based on a MIPS32 processor. If you know the
1380 specific type of processor in your system, choose those that one
1381 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1383 config CPU_MIPS32_R5
1384 bool "MIPS32 Release 5"
1385 depends on SYS_HAS_CPU_MIPS32_R5
1386 select CPU_HAS_PREFETCH
1387 select CPU_SUPPORTS_32BIT_KERNEL
1388 select CPU_SUPPORTS_HIGHMEM
1389 select CPU_SUPPORTS_MSA
1391 select MIPS_O32_FP64_SUPPORT
1393 Choose this option to build a kernel for release 5 or later of the
1394 MIPS32 architecture. New MIPS processors, starting with the Warrior
1395 family, are based on a MIPS32r5 processor. If you own an older
1396 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1398 config CPU_MIPS32_R6
1399 bool "MIPS32 Release 6"
1400 depends on SYS_HAS_CPU_MIPS32_R6
1401 select CPU_HAS_PREFETCH
1402 select CPU_NO_LOAD_STORE_LR
1403 select CPU_SUPPORTS_32BIT_KERNEL
1404 select CPU_SUPPORTS_HIGHMEM
1405 select CPU_SUPPORTS_MSA
1407 select MIPS_O32_FP64_SUPPORT
1409 Choose this option to build a kernel for release 6 or later of the
1410 MIPS32 architecture. New MIPS processors, starting with the Warrior
1411 family, are based on a MIPS32r6 processor. If you own an older
1412 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1414 config CPU_MIPS64_R1
1415 bool "MIPS64 Release 1"
1416 depends on SYS_HAS_CPU_MIPS64_R1
1417 select CPU_HAS_PREFETCH
1418 select CPU_SUPPORTS_32BIT_KERNEL
1419 select CPU_SUPPORTS_64BIT_KERNEL
1420 select CPU_SUPPORTS_HIGHMEM
1421 select CPU_SUPPORTS_HUGEPAGES
1423 Choose this option to build a kernel for release 1 or later of the
1424 MIPS64 architecture. Many modern embedded systems with a 64-bit
1425 MIPS processor are based on a MIPS64 processor. If you know the
1426 specific type of processor in your system, choose those that one
1427 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1428 Release 2 of the MIPS64 architecture is available since several
1429 years so chances are you even have a MIPS64 Release 2 processor
1430 in which case you should choose CPU_MIPS64_R2 instead for better
1433 config CPU_MIPS64_R2
1434 bool "MIPS64 Release 2"
1435 depends on SYS_HAS_CPU_MIPS64_R2
1436 select CPU_HAS_PREFETCH
1437 select CPU_SUPPORTS_32BIT_KERNEL
1438 select CPU_SUPPORTS_64BIT_KERNEL
1439 select CPU_SUPPORTS_HIGHMEM
1440 select CPU_SUPPORTS_HUGEPAGES
1441 select CPU_SUPPORTS_MSA
1444 Choose this option to build a kernel for release 2 or later of the
1445 MIPS64 architecture. Many modern embedded systems with a 64-bit
1446 MIPS processor are based on a MIPS64 processor. If you know the
1447 specific type of processor in your system, choose those that one
1448 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1450 config CPU_MIPS64_R5
1451 bool "MIPS64 Release 5"
1452 depends on SYS_HAS_CPU_MIPS64_R5
1453 select CPU_HAS_PREFETCH
1454 select CPU_SUPPORTS_32BIT_KERNEL
1455 select CPU_SUPPORTS_64BIT_KERNEL
1456 select CPU_SUPPORTS_HIGHMEM
1457 select CPU_SUPPORTS_HUGEPAGES
1458 select CPU_SUPPORTS_MSA
1459 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1462 Choose this option to build a kernel for release 5 or later of the
1463 MIPS64 architecture. This is a intermediate MIPS architecture
1464 release partly implementing release 6 features. Though there is no
1465 any hardware known to be based on this release.
1467 config CPU_MIPS64_R6
1468 bool "MIPS64 Release 6"
1469 depends on SYS_HAS_CPU_MIPS64_R6
1470 select CPU_HAS_PREFETCH
1471 select CPU_NO_LOAD_STORE_LR
1472 select CPU_SUPPORTS_32BIT_KERNEL
1473 select CPU_SUPPORTS_64BIT_KERNEL
1474 select CPU_SUPPORTS_HIGHMEM
1475 select CPU_SUPPORTS_HUGEPAGES
1476 select CPU_SUPPORTS_MSA
1477 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1480 Choose this option to build a kernel for release 6 or later of the
1481 MIPS64 architecture. New MIPS processors, starting with the Warrior
1482 family, are based on a MIPS64r6 processor. If you own an older
1483 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1486 bool "MIPS Warrior P5600"
1487 depends on SYS_HAS_CPU_P5600
1488 select CPU_HAS_PREFETCH
1489 select CPU_SUPPORTS_32BIT_KERNEL
1490 select CPU_SUPPORTS_HIGHMEM
1491 select CPU_SUPPORTS_MSA
1492 select CPU_SUPPORTS_CPUFREQ
1493 select CPU_MIPSR2_IRQ_VI
1494 select CPU_MIPSR2_IRQ_EI
1496 select MIPS_O32_FP64_SUPPORT
1498 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
1499 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
1500 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1501 level features like up to six P5600 calculation cores, CM2 with L2
1502 cache, IOCU/IOMMU (though might be unused depending on the system-
1503 specific IP core configuration), GIC, CPC, virtualisation module,
1508 depends on SYS_HAS_CPU_R3000
1511 select CPU_SUPPORTS_32BIT_KERNEL
1512 select CPU_SUPPORTS_HIGHMEM
1514 Please make sure to pick the right CPU type. Linux/MIPS is not
1515 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
1516 *not* work on R4000 machines and vice versa. However, since most
1517 of the supported machines have an R4000 (or similar) CPU, R4x00
1518 might be a safe bet. If the resulting kernel does not work,
1519 try to recompile with R3000.
1523 depends on SYS_HAS_CPU_R4300
1524 select CPU_SUPPORTS_32BIT_KERNEL
1525 select CPU_SUPPORTS_64BIT_KERNEL
1527 MIPS Technologies R4300-series processors.
1531 depends on SYS_HAS_CPU_R4X00
1532 select CPU_SUPPORTS_32BIT_KERNEL
1533 select CPU_SUPPORTS_64BIT_KERNEL
1534 select CPU_SUPPORTS_HUGEPAGES
1536 MIPS Technologies R4000-series processors other than 4300, including
1537 the R4000, R4400, R4600, and 4700.
1541 depends on SYS_HAS_CPU_TX49XX
1542 select CPU_HAS_PREFETCH
1543 select CPU_SUPPORTS_32BIT_KERNEL
1544 select CPU_SUPPORTS_64BIT_KERNEL
1545 select CPU_SUPPORTS_HUGEPAGES
1549 depends on SYS_HAS_CPU_R5000
1550 select CPU_SUPPORTS_32BIT_KERNEL
1551 select CPU_SUPPORTS_64BIT_KERNEL
1552 select CPU_SUPPORTS_HUGEPAGES
1554 MIPS Technologies R5000-series processors other than the Nevada.
1558 depends on SYS_HAS_CPU_R5500
1559 select CPU_SUPPORTS_32BIT_KERNEL
1560 select CPU_SUPPORTS_64BIT_KERNEL
1561 select CPU_SUPPORTS_HUGEPAGES
1563 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1568 depends on SYS_HAS_CPU_NEVADA
1569 select CPU_SUPPORTS_32BIT_KERNEL
1570 select CPU_SUPPORTS_64BIT_KERNEL
1571 select CPU_SUPPORTS_HUGEPAGES
1573 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1577 depends on SYS_HAS_CPU_R10000
1578 select CPU_HAS_PREFETCH
1579 select CPU_SUPPORTS_32BIT_KERNEL
1580 select CPU_SUPPORTS_64BIT_KERNEL
1581 select CPU_SUPPORTS_HIGHMEM
1582 select CPU_SUPPORTS_HUGEPAGES
1584 MIPS Technologies R10000-series processors.
1588 depends on SYS_HAS_CPU_RM7000
1589 select CPU_HAS_PREFETCH
1590 select CPU_SUPPORTS_32BIT_KERNEL
1591 select CPU_SUPPORTS_64BIT_KERNEL
1592 select CPU_SUPPORTS_HIGHMEM
1593 select CPU_SUPPORTS_HUGEPAGES
1597 depends on SYS_HAS_CPU_SB1
1598 select CPU_SUPPORTS_32BIT_KERNEL
1599 select CPU_SUPPORTS_64BIT_KERNEL
1600 select CPU_SUPPORTS_HIGHMEM
1601 select CPU_SUPPORTS_HUGEPAGES
1602 select WEAK_ORDERING
1604 config CPU_CAVIUM_OCTEON
1605 bool "Cavium Octeon processor"
1606 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1607 select CPU_HAS_PREFETCH
1608 select CPU_SUPPORTS_64BIT_KERNEL
1609 select WEAK_ORDERING
1610 select CPU_SUPPORTS_HIGHMEM
1611 select CPU_SUPPORTS_HUGEPAGES
1612 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1613 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
1614 select MIPS_L1_CACHE_SHIFT_7
1617 The Cavium Octeon processor is a highly integrated chip containing
1618 many ethernet hardware widgets for networking tasks. The processor
1619 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1620 Full details can be found at http://www.caviumnetworks.com.
1623 bool "Broadcom BMIPS"
1624 depends on SYS_HAS_CPU_BMIPS
1626 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
1627 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
1628 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
1629 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
1630 select CPU_SUPPORTS_32BIT_KERNEL
1631 select DMA_NONCOHERENT
1633 select SWAP_IO_SPACE
1634 select WEAK_ORDERING
1635 select CPU_SUPPORTS_HIGHMEM
1636 select CPU_HAS_PREFETCH
1637 select CPU_SUPPORTS_CPUFREQ
1638 select MIPS_EXTERNAL_TIMER
1639 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1641 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1645 config CPU_MIPS32_3_5_FEATURES
1646 bool "MIPS32 Release 3.5 Features"
1647 depends on SYS_HAS_CPU_MIPS32_R3_5
1648 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
1651 Choose this option to build a kernel for release 2 or later of the
1652 MIPS32 architecture including features from the 3.5 release such as
1653 support for Enhanced Virtual Addressing (EVA).
1655 config CPU_MIPS32_3_5_EVA
1656 bool "Enhanced Virtual Addressing (EVA)"
1657 depends on CPU_MIPS32_3_5_FEATURES
1661 Choose this option if you want to enable the Enhanced Virtual
1662 Addressing (EVA) on your MIPS32 core (such as proAptiv).
1663 One of its primary benefits is an increase in the maximum size
1664 of lowmem (up to 3GB). If unsure, say 'N' here.
1666 config CPU_MIPS32_R5_FEATURES
1667 bool "MIPS32 Release 5 Features"
1668 depends on SYS_HAS_CPU_MIPS32_R5
1669 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
1671 Choose this option to build a kernel for release 2 or later of the
1672 MIPS32 architecture including features from release 5 such as
1673 support for Extended Physical Addressing (XPA).
1675 config CPU_MIPS32_R5_XPA
1676 bool "Extended Physical Addressing (XPA)"
1677 depends on CPU_MIPS32_R5_FEATURES
1679 depends on !PAGE_SIZE_4KB
1680 depends on SYS_SUPPORTS_HIGHMEM
1683 select PHYS_ADDR_T_64BIT
1686 Choose this option if you want to enable the Extended Physical
1687 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
1688 benefit is to increase physical addressing equal to or greater
1689 than 40 bits. Note that this has the side effect of turning on
1690 64-bit addressing which in turn makes the PTEs 64-bit in size.
1691 If unsure, say 'N' here.
1694 config CPU_NOP_WORKAROUNDS
1697 config CPU_JUMP_WORKAROUNDS
1700 config CPU_LOONGSON2F_WORKAROUNDS
1701 bool "Loongson 2F Workarounds"
1703 select CPU_NOP_WORKAROUNDS
1704 select CPU_JUMP_WORKAROUNDS
1706 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1707 require workarounds. Without workarounds the system may hang
1708 unexpectedly. For more information please refer to the gas
1709 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1711 Loongson 2F03 and later have fixed these issues and no workarounds
1712 are needed. The workarounds have no significant side effect on them
1713 but may decrease the performance of the system so this option should
1714 be disabled unless the kernel is intended to be run on 2F01 or 2F02
1717 If unsure, please say Y.
1718 endif # CPU_LOONGSON2F
1720 config SYS_SUPPORTS_ZBOOT
1722 select HAVE_KERNEL_GZIP
1723 select HAVE_KERNEL_BZIP2
1724 select HAVE_KERNEL_LZ4
1725 select HAVE_KERNEL_LZMA
1726 select HAVE_KERNEL_LZO
1727 select HAVE_KERNEL_XZ
1728 select HAVE_KERNEL_ZSTD
1730 config SYS_SUPPORTS_ZBOOT_UART16550
1732 select SYS_SUPPORTS_ZBOOT
1734 config SYS_SUPPORTS_ZBOOT_UART_PROM
1736 select SYS_SUPPORTS_ZBOOT
1738 config CPU_LOONGSON2EF
1740 select CPU_SUPPORTS_32BIT_KERNEL
1741 select CPU_SUPPORTS_64BIT_KERNEL
1742 select CPU_SUPPORTS_HIGHMEM
1743 select CPU_SUPPORTS_HUGEPAGES
1745 config CPU_LOONGSON32
1749 select CPU_HAS_PREFETCH
1750 select CPU_SUPPORTS_32BIT_KERNEL
1751 select CPU_SUPPORTS_HIGHMEM
1752 select CPU_SUPPORTS_CPUFREQ
1754 config CPU_BMIPS32_3300
1755 select SMP_UP if SMP
1758 config CPU_BMIPS4350
1760 select SYS_SUPPORTS_SMP
1761 select SYS_SUPPORTS_HOTPLUG_CPU
1763 config CPU_BMIPS4380
1765 select MIPS_L1_CACHE_SHIFT_6
1766 select SYS_SUPPORTS_SMP
1767 select SYS_SUPPORTS_HOTPLUG_CPU
1770 config CPU_BMIPS5000
1772 select MIPS_CPU_SCACHE
1773 select MIPS_L1_CACHE_SHIFT_7
1774 select SYS_SUPPORTS_SMP
1775 select SYS_SUPPORTS_HOTPLUG_CPU
1778 config SYS_HAS_CPU_LOONGSON64
1780 select CPU_SUPPORTS_CPUFREQ
1783 config SYS_HAS_CPU_LOONGSON2E
1786 config SYS_HAS_CPU_LOONGSON2F
1788 select CPU_SUPPORTS_CPUFREQ
1789 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1791 config SYS_HAS_CPU_LOONGSON1B
1794 config SYS_HAS_CPU_LOONGSON1C
1797 config SYS_HAS_CPU_MIPS32_R1
1800 config SYS_HAS_CPU_MIPS32_R2
1803 config SYS_HAS_CPU_MIPS32_R3_5
1806 config SYS_HAS_CPU_MIPS32_R5
1809 config SYS_HAS_CPU_MIPS32_R6
1812 config SYS_HAS_CPU_MIPS64_R1
1815 config SYS_HAS_CPU_MIPS64_R2
1818 config SYS_HAS_CPU_MIPS64_R5
1821 config SYS_HAS_CPU_MIPS64_R6
1824 config SYS_HAS_CPU_P5600
1827 config SYS_HAS_CPU_R3000
1830 config SYS_HAS_CPU_R4300
1833 config SYS_HAS_CPU_R4X00
1836 config SYS_HAS_CPU_TX49XX
1839 config SYS_HAS_CPU_R5000
1842 config SYS_HAS_CPU_R5500
1845 config SYS_HAS_CPU_NEVADA
1848 config SYS_HAS_CPU_R10000
1851 config SYS_HAS_CPU_RM7000
1854 config SYS_HAS_CPU_SB1
1857 config SYS_HAS_CPU_CAVIUM_OCTEON
1860 config SYS_HAS_CPU_BMIPS
1863 config SYS_HAS_CPU_BMIPS32_3300
1865 select SYS_HAS_CPU_BMIPS
1867 config SYS_HAS_CPU_BMIPS4350
1869 select SYS_HAS_CPU_BMIPS
1871 config SYS_HAS_CPU_BMIPS4380
1873 select SYS_HAS_CPU_BMIPS
1875 config SYS_HAS_CPU_BMIPS5000
1877 select SYS_HAS_CPU_BMIPS
1880 # CPU may reorder R->R, R->W, W->R, W->W
1881 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1883 config WEAK_ORDERING
1887 # CPU may reorder reads and writes beyond LL/SC
1888 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1890 config WEAK_REORDERING_BEYOND_LLSC
1895 # These two indicate any level of the MIPS32 and MIPS64 architecture
1899 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
1900 CPU_MIPS32_R6 || CPU_P5600
1904 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
1905 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1908 # These indicate the revision of the architecture
1912 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1916 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1918 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1923 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1925 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1930 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
1932 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1933 select HAVE_ARCH_BITREVERSE
1934 select MIPS_ASID_BITS_VARIABLE
1935 select MIPS_CRC_SUPPORT
1938 config TARGET_ISA_REV
1940 default 1 if CPU_MIPSR1
1941 default 2 if CPU_MIPSR2
1942 default 5 if CPU_MIPSR5
1943 default 6 if CPU_MIPSR6
1946 Reflects the ISA revision being targeted by the kernel build. This
1947 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1955 config SYS_SUPPORTS_32BIT_KERNEL
1957 config SYS_SUPPORTS_64BIT_KERNEL
1959 config CPU_SUPPORTS_32BIT_KERNEL
1961 config CPU_SUPPORTS_64BIT_KERNEL
1963 config CPU_SUPPORTS_CPUFREQ
1965 config CPU_SUPPORTS_ADDRWINCFG
1967 config CPU_SUPPORTS_HUGEPAGES
1969 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
1970 config MIPS_PGD_C0_CONTEXT
1973 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1976 # Set to y for ptrace access to watch registers.
1978 config HARDWARE_WATCHPOINTS
1980 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1985 prompt "Kernel code model"
1987 You should only select this option if you have a workload that
1988 actually benefits from 64-bit processing or if your machine has
1989 large memory. You will only be presented a single option in this
1990 menu if your system does not support both 32-bit and 64-bit kernels.
1993 bool "32-bit kernel"
1994 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1997 Select this option if you want to build a 32-bit kernel.
2000 bool "64-bit kernel"
2001 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
2003 Select this option if you want to build a 64-bit kernel.
2007 config MIPS_VA_BITS_48
2008 bool "48 bits virtual memory"
2011 Support a maximum at least 48 bits of application virtual
2012 memory. Default is 40 bits or less, depending on the CPU.
2013 For page sizes 16k and above, this option results in a small
2014 memory overhead for page tables. For 4k page size, a fourth
2015 level of page tables is added which imposes both a memory
2016 overhead as well as slower TLB fault handling.
2020 config ZBOOT_LOAD_ADDRESS
2021 hex "Compressed kernel load address"
2022 default 0xffffffff80400000 if BCM47XX
2024 depends on SYS_SUPPORTS_ZBOOT
2026 The address to load compressed kernel, aka vmlinuz.
2028 This is only used if non-zero.
2031 prompt "Kernel page size"
2032 default PAGE_SIZE_4KB
2034 config PAGE_SIZE_4KB
2036 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
2038 This option select the standard 4kB Linux page size. On some
2039 R3000-family processors this is the only available page size. Using
2040 4kB page size will minimize memory consumption and is therefore
2041 recommended for low memory systems.
2043 config PAGE_SIZE_8KB
2045 depends on CPU_CAVIUM_OCTEON
2046 depends on !MIPS_VA_BITS_48
2048 Using 8kB page size will result in higher performance kernel at
2049 the price of higher memory consumption. This option is available
2050 only on cnMIPS processors. Note that you will need a suitable Linux
2051 distribution to support this.
2053 config PAGE_SIZE_16KB
2055 depends on !CPU_R3000
2057 Using 16kB page size will result in higher performance kernel at
2058 the price of higher memory consumption. This option is available on
2059 all non-R3000 family processors. Note that you will need a suitable
2060 Linux distribution to support this.
2062 config PAGE_SIZE_32KB
2064 depends on CPU_CAVIUM_OCTEON
2065 depends on !MIPS_VA_BITS_48
2067 Using 32kB page size will result in higher performance kernel at
2068 the price of higher memory consumption. This option is available
2069 only on cnMIPS cores. Note that you will need a suitable Linux
2070 distribution to support this.
2072 config PAGE_SIZE_64KB
2074 depends on !CPU_R3000
2076 Using 64kB page size will result in higher performance kernel at
2077 the price of higher memory consumption. This option is available on
2078 all non-R3000 family processor. Not that at the time of this
2079 writing this option is still high experimental.
2083 config ARCH_FORCE_MAX_ORDER
2084 int "Maximum zone order"
2085 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
2086 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2087 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2090 The kernel memory allocator divides physically contiguous memory
2091 blocks into "zones", where each zone is a power of two number of
2092 pages. This option selects the largest power of two that the kernel
2093 keeps in the memory allocator. If you need to allocate very large
2094 blocks of physically contiguous memory, then you may need to
2095 increase this value.
2097 The page size is not necessarily 4KB. Keep this in mind
2098 when choosing a value for this option.
2103 config IP22_CPU_SCACHE
2108 # Support for a MIPS32 / MIPS64 style S-caches
2110 config MIPS_CPU_SCACHE
2114 config R5000_CPU_SCACHE
2118 config RM7000_CPU_SCACHE
2122 config SIBYTE_DMA_PAGEOPS
2123 bool "Use DMA to clear/copy pages"
2126 Instead of using the CPU to zero and copy pages, use a Data Mover
2127 channel. These DMA channels are otherwise unused by the standard
2128 SiByte Linux port. Seems to give a small performance benefit.
2130 config CPU_HAS_PREFETCH
2133 config CPU_GENERIC_DUMP_TLB
2135 default y if !CPU_R3000
2137 config MIPS_FP_SUPPORT
2138 bool "Floating Point support" if EXPERT
2141 Select y to include support for floating point in the kernel
2142 including initialization of FPU hardware, FP context save & restore
2143 and emulation of an FPU where necessary. Without this support any
2144 userland program attempting to use floating point instructions will
2147 If you know that your userland will not attempt to use floating point
2148 instructions then you can say n here to shrink the kernel a little.
2152 config CPU_R2300_FPU
2154 depends on MIPS_FP_SUPPORT
2155 default y if CPU_R3000
2162 depends on MIPS_FP_SUPPORT
2163 default y if !CPU_R2300_FPU
2165 config CPU_R4K_CACHE_TLB
2167 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
2170 bool "MIPS MT SMP support (1 TC on each available VPE)"
2172 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
2173 select CPU_MIPSR2_IRQ_VI
2174 select CPU_MIPSR2_IRQ_EI
2179 select SYS_SUPPORTS_SMP
2180 select SYS_SUPPORTS_SCHED_SMT
2181 select MIPS_PERF_SHARED_TC_COUNTERS
2183 This is a kernel model which is known as SMVP. This is supported
2184 on cores with the MT ASE and uses the available VPEs to implement
2185 virtual processors which supports SMP. This is equivalent to the
2186 Intel Hyperthreading feature. For further information go to
2187 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2193 bool "SMT (multithreading) scheduler support"
2194 depends on SYS_SUPPORTS_SCHED_SMT
2197 SMT scheduler support improves the CPU scheduler's decision making
2198 when dealing with MIPS MT enabled cores at a cost of slightly
2199 increased overhead in some places. If unsure say N here.
2201 config SYS_SUPPORTS_SCHED_SMT
2204 config SYS_SUPPORTS_MULTITHREADING
2207 config MIPS_MT_FPAFF
2208 bool "Dynamic FPU affinity for FP-intensive threads"
2210 depends on MIPS_MT_SMP
2212 config MIPSR2_TO_R6_EMULATOR
2213 bool "MIPS R2-to-R6 emulator"
2214 depends on CPU_MIPSR6
2215 depends on MIPS_FP_SUPPORT
2218 Choose this option if you want to run non-R6 MIPS userland code.
2219 Even if you say 'Y' here, the emulator will still be disabled by
2220 default. You can enable it using the 'mipsr2emu' kernel option.
2221 The only reason this is a build-time option is to save ~14K from the
2224 config SYS_SUPPORTS_VPE_LOADER
2226 depends on SYS_SUPPORTS_MULTITHREADING
2228 Indicates that the platform supports the VPE loader, and provides
2231 config MIPS_VPE_LOADER
2232 bool "VPE loader support."
2233 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
2234 select CPU_MIPSR2_IRQ_VI
2235 select CPU_MIPSR2_IRQ_EI
2238 Includes a loader for loading an elf relocatable object
2239 onto another VPE and running it.
2241 config MIPS_VPE_LOADER_MT
2244 depends on MIPS_VPE_LOADER
2246 config MIPS_VPE_LOADER_TOM
2247 bool "Load VPE program into memory hidden from linux"
2248 depends on MIPS_VPE_LOADER
2251 The loader can use memory that is present but has been hidden from
2252 Linux using the kernel command line option "mem=xxMB". It's up to
2253 you to ensure the amount you put in the option and the space your
2254 program requires is less or equal to the amount physically present.
2256 config MIPS_VPE_APSP_API
2257 bool "Enable support for AP/SP API (RTLX)"
2258 depends on MIPS_VPE_LOADER
2260 config MIPS_VPE_APSP_API_MT
2263 depends on MIPS_VPE_APSP_API
2266 bool "MIPS Coherent Processing System support"
2267 depends on SYS_SUPPORTS_MIPS_CPS
2269 select MIPS_CPS_PM if HOTPLUG_CPU
2271 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
2272 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
2273 select SYS_SUPPORTS_HOTPLUG_CPU
2274 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
2275 select SYS_SUPPORTS_SMP
2276 select WEAK_ORDERING
2277 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
2279 Select this if you wish to run an SMP kernel across multiple cores
2280 within a MIPS Coherent Processing System. When this option is
2281 enabled the kernel will probe for other cores and boot them with
2282 no external assistance. It is safe to enable this when hardware
2283 support is unavailable.
2296 config SB1_PASS_2_WORKAROUNDS
2298 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
2301 config SB1_PASS_2_1_WORKAROUNDS
2303 depends on CPU_SB1 && CPU_SB1_PASS_2
2307 prompt "SmartMIPS or microMIPS ASE support"
2309 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
2312 Select this if you want neither microMIPS nor SmartMIPS support
2314 config CPU_HAS_SMARTMIPS
2315 depends on SYS_SUPPORTS_SMARTMIPS
2318 SmartMIPS is a extension of the MIPS32 architecture aimed at
2319 increased security at both hardware and software level for
2320 smartcards. Enabling this option will allow proper use of the
2321 SmartMIPS instructions by Linux applications. However a kernel with
2322 this option will not work on a MIPS core without SmartMIPS core. If
2323 you don't know you probably don't have SmartMIPS and should say N
2326 config CPU_MICROMIPS
2327 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
2330 When this option is enabled the kernel will be built using the
2336 bool "Support for the MIPS SIMD Architecture"
2337 depends on CPU_SUPPORTS_MSA
2338 depends on MIPS_FP_SUPPORT
2339 depends on 64BIT || MIPS_O32_FP64_SUPPORT
2341 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2342 and a set of SIMD instructions to operate on them. When this option
2343 is enabled the kernel will support allocating & switching MSA
2344 vector register contexts. If you know that your kernel will only be
2345 running on CPUs which do not support MSA or that your userland will
2346 not be making use of it then you may wish to say N here to reduce
2347 the size & complexity of your kernel.
2358 depends on !CPU_DIEI_BROKEN
2361 config CPU_DIEI_BROKEN
2367 config CPU_NO_LOAD_STORE_LR
2370 CPU lacks support for unaligned load and store instructions:
2371 LWL, LWR, SWL, SWR (Load/store word left/right).
2372 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
2376 # Vectored interrupt mode is an R2 feature
2378 config CPU_MIPSR2_IRQ_VI
2382 # Extended interrupt mode is an R2 feature
2384 config CPU_MIPSR2_IRQ_EI
2389 depends on !CPU_R3000
2396 # Work around the "daddi" and "daddiu" CPU errata:
2398 # - The `daddi' instruction fails to trap on overflow.
2399 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2402 # - The `daddiu' instruction can produce an incorrect result.
2403 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2405 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2407 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
2408 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
2409 config CPU_DADDI_WORKAROUNDS
2412 # Work around certain R4000 CPU errata (as implemented by GCC):
2414 # - A double-word or a variable shift may give an incorrect result
2415 # if executed immediately after starting an integer division:
2416 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2418 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2421 # - A double-word or a variable shift may give an incorrect result
2422 # if executed while an integer multiplication is in progress:
2423 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2426 # - An integer division may give an incorrect result if started in
2427 # a delay slot of a taken branch or a jump:
2428 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2430 config CPU_R4000_WORKAROUNDS
2432 select CPU_R4400_WORKAROUNDS
2434 # Work around certain R4400 CPU errata (as implemented by GCC):
2436 # - A double-word or a variable shift may give an incorrect result
2437 # if executed immediately after starting an integer division:
2438 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2439 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2440 config CPU_R4400_WORKAROUNDS
2443 config CPU_R4X00_BUGS64
2445 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2447 config MIPS_ASID_SHIFT
2449 default 6 if CPU_R3000
2452 config MIPS_ASID_BITS
2454 default 0 if MIPS_ASID_BITS_VARIABLE
2455 default 6 if CPU_R3000
2458 config MIPS_ASID_BITS_VARIABLE
2461 config MIPS_CRC_SUPPORT
2464 # R4600 erratum. Due to the lack of errata information the exact
2465 # technical details aren't known. I've experimentally found that disabling
2466 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2468 config WAR_R4600_V1_INDEX_ICACHEOP
2471 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2473 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
2474 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
2475 # executed if there is no other dcache activity. If the dcache is
2476 # accessed for another instruction immediately preceding when these
2477 # cache instructions are executing, it is possible that the dcache
2478 # tag match outputs used by these cache instructions will be
2479 # incorrect. These cache instructions should be preceded by at least
2480 # four instructions that are not any kind of load or store
2483 # This is not allowed: lw
2487 # cache Hit_Writeback_Invalidate_D
2489 # This is allowed: lw
2494 # cache Hit_Writeback_Invalidate_D
2495 config WAR_R4600_V1_HIT_CACHEOP
2498 # Writeback and invalidate the primary cache dcache before DMA.
2500 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
2501 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
2502 # operate correctly if the internal data cache refill buffer is empty. These
2503 # CACHE instructions should be separated from any potential data cache miss
2504 # by a load instruction to an uncached address to empty the response buffer."
2505 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
2507 config WAR_R4600_V2_HIT_CACHEOP
2510 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2511 # the line which this instruction itself exists, the following
2512 # operation is not guaranteed."
2514 # Workaround: do two phase flushing for Index_Invalidate_I
2515 config WAR_TX49XX_ICACHE_INDEX_INV
2518 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2519 # opposes it being called that) where invalid instructions in the same
2520 # I-cache line worth of instructions being fetched may case spurious
2522 config WAR_ICACHE_REFILLS
2525 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2526 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2527 config WAR_R10000_LLSC
2530 # 34K core erratum: "Problems Executing the TLBR Instruction"
2531 config WAR_MIPS34K_MISSED_ITLB
2535 # - Highmem only makes sense for the 32-bit kernel.
2536 # - The current highmem code will only work properly on physically indexed
2537 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2538 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
2539 # moment we protect the user and offer the highmem option only on machines
2540 # where it's known to be safe. This will not offer highmem on a few systems
2541 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
2542 # indexed CPUs but we're playing safe.
2543 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2544 # know they might have memory configurations that could make use of highmem
2548 bool "High Memory Support"
2549 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
2552 config CPU_SUPPORTS_HIGHMEM
2555 config SYS_SUPPORTS_HIGHMEM
2558 config SYS_SUPPORTS_SMARTMIPS
2561 config SYS_SUPPORTS_MICROMIPS
2564 config SYS_SUPPORTS_MIPS16
2567 This option must be set if a kernel might be executed on a MIPS16-
2568 enabled CPU even if MIPS16 is not actually being used. In other
2569 words, it makes the kernel MIPS16-tolerant.
2571 config CPU_SUPPORTS_MSA
2574 config ARCH_FLATMEM_ENABLE
2576 depends on !NUMA && !CPU_LOONGSON2EF
2578 config ARCH_SPARSEMEM_ENABLE
2583 depends on SYS_SUPPORTS_NUMA
2585 select HAVE_SETUP_PER_CPU_AREA
2586 select NEED_PER_CPU_EMBED_FIRST_CHUNK
2588 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2589 Access). This option improves performance on systems with more
2590 than two nodes; on two node systems it is generally better to
2591 leave it disabled; on single node systems leave this option
2594 config SYS_SUPPORTS_NUMA
2597 config HAVE_ARCH_NODEDATA_EXTENSION
2601 bool "Relocatable kernel"
2602 depends on SYS_SUPPORTS_RELOCATABLE
2603 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
2604 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
2605 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
2606 CPU_P5600 || CAVIUM_OCTEON_SOC || \
2609 This builds a kernel image that retains relocation information
2610 so it can be loaded someplace besides the default 1MB.
2611 The relocations make the kernel binary about 15% larger,
2612 but are discarded at runtime
2614 config RELOCATION_TABLE_SIZE
2615 hex "Relocation table size"
2616 depends on RELOCATABLE
2617 range 0x0 0x01000000
2618 default "0x00200000" if CPU_LOONGSON64
2619 default "0x00100000"
2621 A table of relocation data will be appended to the kernel binary
2622 and parsed at boot to fix up the relocated kernel.
2624 This option allows the amount of space reserved for the table to be
2625 adjusted, although the default of 1Mb should be ok in most cases.
2627 The build will fail and a valid size suggested if this is too small.
2629 If unsure, leave at the default value.
2631 config RANDOMIZE_BASE
2632 bool "Randomize the address of the kernel image"
2633 depends on RELOCATABLE
2635 Randomizes the physical and virtual address at which the
2636 kernel image is loaded, as a security feature that
2637 deters exploit attempts relying on knowledge of the location
2638 of kernel internals.
2640 Entropy is generated using any coprocessor 0 registers available.
2642 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2646 config RANDOMIZE_BASE_MAX_OFFSET
2647 hex "Maximum kASLR offset" if EXPERT
2648 depends on RANDOMIZE_BASE
2649 range 0x0 0x40000000 if EVA || 64BIT
2650 range 0x0 0x08000000
2651 default "0x01000000"
2653 When kASLR is active, this provides the maximum offset that will
2654 be applied to the kernel image. It should be set according to the
2655 amount of physical RAM available in the target system minus
2656 PHYSICAL_START and must be a power of 2.
2658 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2659 EVA or 64-bit. The default is 16Mb.
2666 config HW_PERF_EVENTS
2667 bool "Enable hardware performance counter support for perf events"
2668 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2671 Enable hardware performance counter support for perf events. If
2672 disabled, perf events will use software events only.
2675 bool "Enable DMI scanning"
2676 depends on MACH_LOONGSON64
2677 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2680 Enabled scanning of DMI to identify machine quirks. Say Y
2681 here unless you have verified that your setup is not
2682 affected by entries in the DMI blacklist. Required by PNP
2686 bool "Multi-Processing support"
2687 depends on SYS_SUPPORTS_SMP
2689 This enables support for systems with more than one CPU. If you have
2690 a system with only one CPU, say N. If you have a system with more
2691 than one CPU, say Y.
2693 If you say N here, the kernel will run on uni- and multiprocessor
2694 machines, but will use only one CPU of a multiprocessor machine. If
2695 you say Y here, the kernel will run on many, but not all,
2696 uniprocessor machines. On a uniprocessor machine, the kernel
2697 will run faster if you say N here.
2699 People using multiprocessor machines who say Y here should also say
2700 Y to "Enhanced Real Time Clock Support", below.
2702 See also the SMP-HOWTO available at
2703 <https://www.tldp.org/docs.html#howto>.
2705 If you don't know what to do here, say N.
2708 bool "Support for hot-pluggable CPUs"
2709 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2711 Say Y here to allow turning CPUs off and on. CPUs can be
2712 controlled through /sys/devices/system/cpu.
2713 (Note: power management support will enable this option
2714 automatically on SMP systems. )
2715 Say N if you want to disable CPU hotplug.
2720 config SYS_SUPPORTS_MIPS_CPS
2723 config SYS_SUPPORTS_SMP
2726 config NR_CPUS_DEFAULT_4
2729 config NR_CPUS_DEFAULT_8
2732 config NR_CPUS_DEFAULT_16
2735 config NR_CPUS_DEFAULT_32
2738 config NR_CPUS_DEFAULT_64
2742 int "Maximum number of CPUs (2-256)"
2745 default "4" if NR_CPUS_DEFAULT_4
2746 default "8" if NR_CPUS_DEFAULT_8
2747 default "16" if NR_CPUS_DEFAULT_16
2748 default "32" if NR_CPUS_DEFAULT_32
2749 default "64" if NR_CPUS_DEFAULT_64
2751 This allows you to specify the maximum number of CPUs which this
2752 kernel will support. The maximum supported value is 32 for 32-bit
2753 kernel and 64 for 64-bit kernels; the minimum value which makes
2754 sense is 1 for Qemu (useful only for kernel debugging purposes)
2755 and 2 for all others.
2757 This is purely to save memory - each supported CPU adds
2758 approximately eight kilobytes to the kernel image. For best
2759 performance should round up your number of processors to the next
2762 config MIPS_PERF_SHARED_TC_COUNTERS
2765 config MIPS_NR_CPU_NR_MAP_1024
2768 config MIPS_NR_CPU_NR_MAP
2771 default 1024 if MIPS_NR_CPU_NR_MAP_1024
2772 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2775 # Timer Interrupt Frequency Configuration
2779 prompt "Timer frequency"
2782 Allows the configuration of the timer frequency.
2785 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2788 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2791 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2794 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2797 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2800 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2803 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2806 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2810 config SYS_SUPPORTS_24HZ
2813 config SYS_SUPPORTS_48HZ
2816 config SYS_SUPPORTS_100HZ
2819 config SYS_SUPPORTS_128HZ
2822 config SYS_SUPPORTS_250HZ
2825 config SYS_SUPPORTS_256HZ
2828 config SYS_SUPPORTS_1000HZ
2831 config SYS_SUPPORTS_1024HZ
2834 config SYS_SUPPORTS_ARBIT_HZ
2836 default y if !SYS_SUPPORTS_24HZ && \
2837 !SYS_SUPPORTS_48HZ && \
2838 !SYS_SUPPORTS_100HZ && \
2839 !SYS_SUPPORTS_128HZ && \
2840 !SYS_SUPPORTS_250HZ && \
2841 !SYS_SUPPORTS_256HZ && \
2842 !SYS_SUPPORTS_1000HZ && \
2843 !SYS_SUPPORTS_1024HZ
2849 default 100 if HZ_100
2850 default 128 if HZ_128
2851 default 250 if HZ_250
2852 default 256 if HZ_256
2853 default 1000 if HZ_1000
2854 default 1024 if HZ_1024
2857 def_bool HIGH_RES_TIMERS
2859 config ARCH_SUPPORTS_KEXEC
2862 config ARCH_SUPPORTS_CRASH_DUMP
2865 config PHYSICAL_START
2866 hex "Physical address where the kernel is loaded"
2867 default "0xffffffff84000000"
2868 depends on CRASH_DUMP
2870 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2871 If you plan to use kernel for capturing the crash dump change
2872 this value to start of the reserved region (the "X" value as
2873 specified in the "crashkernel=YM@XM" command line boot parameter
2874 passed to the panic-ed kernel).
2876 config MIPS_O32_FP64_SUPPORT
2877 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2878 depends on 32BIT || MIPS32_O32
2880 When this is enabled, the kernel will support use of 64-bit floating
2881 point registers with binaries using the O32 ABI along with the
2882 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2883 32-bit MIPS systems this support is at the cost of increasing the
2884 size and complexity of the compiled FPU emulator. Thus if you are
2885 running a MIPS32 system and know that none of your userland binaries
2886 will require 64-bit floating point, you may wish to reduce the size
2887 of your kernel & potentially improve FP emulation performance by
2890 Although binutils currently supports use of this flag the details
2891 concerning its effect upon the O32 ABI in userland are still being
2892 worked on. In order to avoid userland becoming dependent upon current
2893 behaviour before the details have been finalised, this option should
2894 be considered experimental and only enabled by those working upon
2902 select OF_EARLY_FLATTREE
2912 prompt "Kernel appended dtb support" if USE_OF
2913 default MIPS_NO_APPENDED_DTB
2915 config MIPS_NO_APPENDED_DTB
2918 Do not enable appended dtb support.
2920 config MIPS_ELF_APPENDED_DTB
2923 With this option, the boot code will look for a device tree binary
2924 DTB) included in the vmlinux ELF section .appended_dtb. By default
2925 it is empty and the DTB can be appended using binutils command
2928 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
2930 This is meant as a backward compatibility convenience for those
2931 systems with a bootloader that can't be upgraded to accommodate
2932 the documented boot protocol using a device tree.
2934 config MIPS_RAW_APPENDED_DTB
2935 bool "vmlinux.bin or vmlinuz.bin"
2937 With this option, the boot code will look for a device tree binary
2938 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
2939 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
2941 This is meant as a backward compatibility convenience for those
2942 systems with a bootloader that can't be upgraded to accommodate
2943 the documented boot protocol using a device tree.
2945 Beware that there is very little in terms of protection against
2946 this option being confused by leftover garbage in memory that might
2947 look like a DTB header after a reboot if no actual DTB is appended
2948 to vmlinux.bin. Do not leave this option active in a production kernel
2949 if you don't intend to always append a DTB.
2953 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2954 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2955 !MACH_LOONGSON64 && !MIPS_MALTA && \
2957 default MIPS_CMDLINE_FROM_BOOTLOADER
2959 config MIPS_CMDLINE_FROM_DTB
2961 bool "Dtb kernel arguments if available"
2963 config MIPS_CMDLINE_DTB_EXTEND
2965 bool "Extend dtb kernel arguments with bootloader arguments"
2967 config MIPS_CMDLINE_FROM_BOOTLOADER
2968 bool "Bootloader kernel arguments if available"
2970 config MIPS_CMDLINE_BUILTIN_EXTEND
2971 depends on CMDLINE_BOOL
2972 bool "Extend builtin kernel arguments with bootloader arguments"
2977 config LOCKDEP_SUPPORT
2981 config STACKTRACE_SUPPORT
2985 config PGTABLE_LEVELS
2987 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
2988 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
2991 config MIPS_AUTO_PFN_OFFSET
2994 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2996 config PCI_DRIVERS_GENERIC
2997 select PCI_DOMAINS_GENERIC if PCI
3000 config PCI_DRIVERS_LEGACY
3001 def_bool !PCI_DRIVERS_GENERIC
3002 select NO_GENERIC_PCI_IOPORT_MAP
3003 select PCI_DOMAINS if PCI
3006 # ISA support is now enabled via select. Too many systems still have the one
3007 # or other ISA chip on the board that users don't know about so don't expect
3008 # users to choose the right thing ...
3014 bool "TURBOchannel support"
3015 depends on MACH_DECSTATION
3017 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
3018 processors. TURBOchannel programming specifications are available
3020 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
3022 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3023 Linux driver support status is documented at:
3024 <http://www.linux-mips.org/wiki/DECstation>
3030 config ARCH_MMAP_RND_BITS_MIN
3034 config ARCH_MMAP_RND_BITS_MAX
3038 config ARCH_MMAP_RND_COMPAT_BITS_MIN
3041 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3048 select MIPS_EXTERNAL_TIMER
3054 config MIPS32_COMPAT
3061 bool "Kernel support for o32 binaries"
3063 select ARCH_WANT_OLD_COMPAT_IPC
3065 select MIPS32_COMPAT
3067 Select this option if you want to run o32 binaries. These are pure
3068 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3069 existing binaries are in this format.
3074 bool "Kernel support for n32 binaries"
3076 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3078 select MIPS32_COMPAT
3080 Select this option if you want to run n32 binaries. These are
3081 64-bit binaries using 32-bit quantities for addressing and certain
3082 data that would normally be 64-bit. They are used in special
3087 config CC_HAS_MNO_BRANCH_LIKELY
3089 depends on $(cc-option,-mno-branch-likely)
3091 # https://github.com/llvm/llvm-project/issues/61045
3092 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
3093 def_bool y if CC_IS_CLANG
3095 menu "Power management options"
3097 config ARCH_HIBERNATION_POSSIBLE
3099 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3101 config ARCH_SUSPEND_POSSIBLE
3103 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3105 source "kernel/power/Kconfig"
3109 config MIPS_EXTERNAL_TIMER
3112 menu "CPU Power Management"
3114 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3115 source "drivers/cpufreq/Kconfig"
3116 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3118 source "drivers/cpuidle/Kconfig"
3122 source "arch/mips/kvm/Kconfig"
3124 source "arch/mips/vdso/Kconfig"