1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/delay.h>
4 #include <linux/interrupt.h>
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
8 #include <linux/sched/debug.h>
9 #include <linux/types.h>
10 #include <linux/ioport.h>
12 #include <asm/hwtest.h>
14 #include <asm/irq_regs.h>
17 #define GFPIC_REG_IRQ_PENDING 0x04
18 #define GFPIC_REG_IRQ_DISABLE_ALL 0x08
19 #define GFPIC_REG_IRQ_DISABLE 0x0c
20 #define GFPIC_REG_IRQ_ENABLE 0x10
22 extern void show_registers(struct pt_regs *regs);
24 static struct resource picres[6];
25 static const char *picname[6] = {
35 * 6 goldfish-pic for CPU IRQ #1 to IRQ #6
36 * CPU IRQ #1 -> PIC #1
37 * IRQ #1 to IRQ #31 -> unused
38 * IRQ #32 -> goldfish-tty
39 * CPU IRQ #2 -> PIC #2
40 * IRQ #1 to IRQ #32 -> virtio-mmio from 1 to 32
41 * CPU IRQ #3 -> PIC #3
42 * IRQ #1 to IRQ #32 -> virtio-mmio from 33 to 64
43 * CPU IRQ #4 -> PIC #4
44 * IRQ #1 to IRQ #32 -> virtio-mmio from 65 to 96
45 * CPU IRQ #5 -> PIC #5
46 * IRQ #1 to IRQ #32 -> virtio-mmio from 97 to 128
47 * CPU IRQ #6 -> PIC #6
48 * IRQ #1 -> goldfish-timer
49 * IRQ #2 -> goldfish-rtc
50 * IRQ #3 to IRQ #32 -> unused
54 static u32 gfpic_read(int pic, int reg)
56 void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio +
59 return ioread32be(base + reg);
62 static void gfpic_write(u32 value, int pic, int reg)
64 void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio +
67 iowrite32be(value, base + reg);
70 #define GF_PIC(irq) ((irq - IRQ_USER) / 32)
71 #define GF_IRQ(irq) ((irq - IRQ_USER) % 32)
73 static void virt_irq_enable(struct irq_data *data)
75 gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq),
76 GFPIC_REG_IRQ_ENABLE);
79 static void virt_irq_disable(struct irq_data *data)
81 gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq),
82 GFPIC_REG_IRQ_DISABLE);
85 static unsigned int virt_irq_startup(struct irq_data *data)
87 virt_irq_enable(data);
91 static irqreturn_t virt_nmi_handler(int irq, void *dev_id)
95 if (READ_ONCE(in_nmi))
97 WRITE_ONCE(in_nmi, 1);
99 pr_warn("Non-Maskable Interrupt\n");
100 show_registers(get_irq_regs());
102 WRITE_ONCE(in_nmi, 0);
106 static struct irq_chip virt_irq_chip = {
108 .irq_enable = virt_irq_enable,
109 .irq_disable = virt_irq_disable,
110 .irq_startup = virt_irq_startup,
111 .irq_shutdown = virt_irq_disable,
114 static void goldfish_pic_irq(struct irq_desc *desc)
117 unsigned int irq_num;
118 unsigned int pic = desc->irq_data.irq - 1;
120 irq_pending = gfpic_read(pic, GFPIC_REG_IRQ_PENDING);
121 irq_num = IRQ_USER + pic * 32;
125 generic_handle_irq(irq_num);
128 } while (irq_pending);
131 void __init virt_init_IRQ(void)
135 m68k_setup_irq_controller(&virt_irq_chip, handle_simple_irq, IRQ_USER,
136 NUM_VIRT_SOURCES - IRQ_USER);
138 for (i = 0; i < 6; i++) {
140 picres[i] = (struct resource)
141 DEFINE_RES_MEM_NAMED(virt_bi_data.pic.mmio + i * 0x1000,
143 if (request_resource(&iomem_resource, &picres[i])) {
144 pr_err("Cannot allocate %s resource\n", picname[i]);
148 irq_set_chained_handler(virt_bi_data.pic.irq + i,
152 if (request_irq(IRQ_AUTO_7, virt_nmi_handler, 0, "NMI",
154 pr_err("Couldn't register NMI\n");