2 * device.c -- common ColdFire SoC device support
4 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/init.h>
14 #include <linux/spi/spi.h>
15 #include <linux/gpio.h>
16 #include <linux/fec.h>
17 #include <linux/dmaengine.h>
18 #include <asm/traps.h>
19 #include <asm/coldfire.h>
20 #include <asm/mcfsim.h>
21 #include <asm/mcfuart.h>
22 #include <asm/mcfqspi.h>
23 #include <linux/platform_data/edma.h>
24 #include <linux/platform_data/dma-mcf-edma.h>
25 #include <linux/platform_data/mmc-esdhc-mcf.h>
28 * All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
30 static struct mcf_platform_uart mcf_uart_platform_data[] = {
32 .mapbase = MCFUART_BASE0,
36 .mapbase = MCFUART_BASE1,
41 .mapbase = MCFUART_BASE2,
47 .mapbase = MCFUART_BASE3,
53 .mapbase = MCFUART_BASE4,
59 .mapbase = MCFUART_BASE5,
65 .mapbase = MCFUART_BASE6,
71 .mapbase = MCFUART_BASE7,
77 .mapbase = MCFUART_BASE8,
83 .mapbase = MCFUART_BASE9,
90 static struct platform_device mcf_uart = {
93 .dev.platform_data = mcf_uart_platform_data,
96 #if IS_ENABLED(CONFIG_FEC)
99 #define FEC_NAME "enet-fec"
100 static struct fec_platform_data fec_pdata = {
101 .phy = PHY_INTERFACE_MODE_RMII,
103 #define FEC_PDATA (&fec_pdata)
105 #define FEC_NAME "fec"
106 #define FEC_PDATA NULL
110 * Some ColdFire cores contain the Fast Ethernet Controller (FEC)
111 * block. It is Freescale's own hardware block. Some ColdFires
114 static struct resource mcf_fec0_resources[] = {
116 .start = MCFFEC_BASE0,
117 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
118 .flags = IORESOURCE_MEM,
121 .start = MCF_IRQ_FECRX0,
122 .end = MCF_IRQ_FECRX0,
123 .flags = IORESOURCE_IRQ,
126 .start = MCF_IRQ_FECTX0,
127 .end = MCF_IRQ_FECTX0,
128 .flags = IORESOURCE_IRQ,
131 .start = MCF_IRQ_FECENTC0,
132 .end = MCF_IRQ_FECENTC0,
133 .flags = IORESOURCE_IRQ,
137 static struct platform_device mcf_fec0 = {
140 .num_resources = ARRAY_SIZE(mcf_fec0_resources),
141 .resource = mcf_fec0_resources,
143 .dma_mask = &mcf_fec0.dev.coherent_dma_mask,
144 .coherent_dma_mask = DMA_BIT_MASK(32),
145 .platform_data = FEC_PDATA,
150 static struct resource mcf_fec1_resources[] = {
152 .start = MCFFEC_BASE1,
153 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
154 .flags = IORESOURCE_MEM,
157 .start = MCF_IRQ_FECRX1,
158 .end = MCF_IRQ_FECRX1,
159 .flags = IORESOURCE_IRQ,
162 .start = MCF_IRQ_FECTX1,
163 .end = MCF_IRQ_FECTX1,
164 .flags = IORESOURCE_IRQ,
167 .start = MCF_IRQ_FECENTC1,
168 .end = MCF_IRQ_FECENTC1,
169 .flags = IORESOURCE_IRQ,
173 static struct platform_device mcf_fec1 = {
176 .num_resources = ARRAY_SIZE(mcf_fec1_resources),
177 .resource = mcf_fec1_resources,
179 .dma_mask = &mcf_fec1.dev.coherent_dma_mask,
180 .coherent_dma_mask = DMA_BIT_MASK(32),
181 .platform_data = FEC_PDATA,
184 #endif /* MCFFEC_BASE1 */
185 #endif /* CONFIG_FEC */
187 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
189 * The ColdFire QSPI module is an SPI protocol hardware block used
190 * on a number of different ColdFire CPUs.
192 static struct resource mcf_qspi_resources[] = {
194 .start = MCFQSPI_BASE,
195 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
196 .flags = IORESOURCE_MEM,
199 .start = MCF_IRQ_QSPI,
201 .flags = IORESOURCE_IRQ,
205 static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
209 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
211 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
214 status = gpio_direction_output(MCFQSPI_CS0, 1);
216 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
220 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
222 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
225 status = gpio_direction_output(MCFQSPI_CS1, 1);
227 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
231 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
233 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
236 status = gpio_direction_output(MCFQSPI_CS2, 1);
238 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
243 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
245 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
248 status = gpio_direction_output(MCFQSPI_CS3, 1);
250 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
251 gpio_free(MCFQSPI_CS3);
259 gpio_free(MCFQSPI_CS2);
261 gpio_free(MCFQSPI_CS1);
263 gpio_free(MCFQSPI_CS0);
268 static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
271 gpio_free(MCFQSPI_CS3);
273 gpio_free(MCFQSPI_CS2);
274 gpio_free(MCFQSPI_CS1);
275 gpio_free(MCFQSPI_CS0);
278 static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
279 u8 chip_select, bool cs_high)
281 switch (chip_select) {
283 gpio_set_value(MCFQSPI_CS0, cs_high);
286 gpio_set_value(MCFQSPI_CS1, cs_high);
289 gpio_set_value(MCFQSPI_CS2, cs_high);
293 gpio_set_value(MCFQSPI_CS3, cs_high);
299 static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
300 u8 chip_select, bool cs_high)
302 switch (chip_select) {
304 gpio_set_value(MCFQSPI_CS0, !cs_high);
307 gpio_set_value(MCFQSPI_CS1, !cs_high);
310 gpio_set_value(MCFQSPI_CS2, !cs_high);
314 gpio_set_value(MCFQSPI_CS3, !cs_high);
320 static struct mcfqspi_cs_control mcf_cs_control = {
321 .setup = mcf_cs_setup,
322 .teardown = mcf_cs_teardown,
323 .select = mcf_cs_select,
324 .deselect = mcf_cs_deselect,
327 static struct mcfqspi_platform_data mcf_qspi_data = {
330 .cs_control = &mcf_cs_control,
333 static struct platform_device mcf_qspi = {
336 .num_resources = ARRAY_SIZE(mcf_qspi_resources),
337 .resource = mcf_qspi_resources,
338 .dev.platform_data = &mcf_qspi_data,
340 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
342 #if IS_ENABLED(CONFIG_I2C_IMX)
343 static struct resource mcf_i2c0_resources[] = {
345 .start = MCFI2C_BASE0,
346 .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
347 .flags = IORESOURCE_MEM,
350 .start = MCF_IRQ_I2C0,
352 .flags = IORESOURCE_IRQ,
356 static struct platform_device mcf_i2c0 = {
359 .num_resources = ARRAY_SIZE(mcf_i2c0_resources),
360 .resource = mcf_i2c0_resources,
364 static struct resource mcf_i2c1_resources[] = {
366 .start = MCFI2C_BASE1,
367 .end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1,
368 .flags = IORESOURCE_MEM,
371 .start = MCF_IRQ_I2C1,
373 .flags = IORESOURCE_IRQ,
377 static struct platform_device mcf_i2c1 = {
380 .num_resources = ARRAY_SIZE(mcf_i2c1_resources),
381 .resource = mcf_i2c1_resources,
384 #endif /* MCFI2C_BASE1 */
388 static struct resource mcf_i2c2_resources[] = {
390 .start = MCFI2C_BASE2,
391 .end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1,
392 .flags = IORESOURCE_MEM,
395 .start = MCF_IRQ_I2C2,
397 .flags = IORESOURCE_IRQ,
401 static struct platform_device mcf_i2c2 = {
404 .num_resources = ARRAY_SIZE(mcf_i2c2_resources),
405 .resource = mcf_i2c2_resources,
408 #endif /* MCFI2C_BASE2 */
412 static struct resource mcf_i2c3_resources[] = {
414 .start = MCFI2C_BASE3,
415 .end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1,
416 .flags = IORESOURCE_MEM,
419 .start = MCF_IRQ_I2C3,
421 .flags = IORESOURCE_IRQ,
425 static struct platform_device mcf_i2c3 = {
428 .num_resources = ARRAY_SIZE(mcf_i2c3_resources),
429 .resource = mcf_i2c3_resources,
432 #endif /* MCFI2C_BASE3 */
436 static struct resource mcf_i2c4_resources[] = {
438 .start = MCFI2C_BASE4,
439 .end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1,
440 .flags = IORESOURCE_MEM,
443 .start = MCF_IRQ_I2C4,
445 .flags = IORESOURCE_IRQ,
449 static struct platform_device mcf_i2c4 = {
452 .num_resources = ARRAY_SIZE(mcf_i2c4_resources),
453 .resource = mcf_i2c4_resources,
456 #endif /* MCFI2C_BASE4 */
460 static struct resource mcf_i2c5_resources[] = {
462 .start = MCFI2C_BASE5,
463 .end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1,
464 .flags = IORESOURCE_MEM,
467 .start = MCF_IRQ_I2C5,
469 .flags = IORESOURCE_IRQ,
473 static struct platform_device mcf_i2c5 = {
476 .num_resources = ARRAY_SIZE(mcf_i2c5_resources),
477 .resource = mcf_i2c5_resources,
480 #endif /* MCFI2C_BASE5 */
481 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
483 #if IS_ENABLED(CONFIG_MCF_EDMA)
485 static const struct dma_slave_map mcf_edma_map[] = {
486 { "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) },
487 { "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) },
488 { "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) },
489 { "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) },
490 { "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) },
491 { "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) },
492 { "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) },
493 { "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) },
494 { "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) },
495 { "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) },
496 { "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) },
497 { "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) },
498 { "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) },
499 { "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) },
500 { "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) },
501 { "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) },
504 static struct mcf_edma_platform_data mcf_edma_data = {
506 .slave_map = mcf_edma_map,
507 .slavecnt = ARRAY_SIZE(mcf_edma_map),
510 static struct resource mcf_edma_resources[] = {
512 .start = MCFEDMA_BASE,
513 .end = MCFEDMA_BASE + MCFEDMA_SIZE - 1,
514 .flags = IORESOURCE_MEM,
517 .start = MCFEDMA_IRQ_INTR0,
518 .end = MCFEDMA_IRQ_INTR0 + 15,
519 .flags = IORESOURCE_IRQ,
520 .name = "edma-tx-00-15",
523 .start = MCFEDMA_IRQ_INTR16,
524 .end = MCFEDMA_IRQ_INTR16 + 39,
525 .flags = IORESOURCE_IRQ,
526 .name = "edma-tx-16-55",
529 .start = MCFEDMA_IRQ_INTR56,
530 .end = MCFEDMA_IRQ_INTR56,
531 .flags = IORESOURCE_IRQ,
532 .name = "edma-tx-56-63",
535 .start = MCFEDMA_IRQ_ERR,
536 .end = MCFEDMA_IRQ_ERR,
537 .flags = IORESOURCE_IRQ,
542 static u64 mcf_edma_dmamask = DMA_BIT_MASK(32);
544 static struct platform_device mcf_edma = {
547 .num_resources = ARRAY_SIZE(mcf_edma_resources),
548 .resource = mcf_edma_resources,
550 .dma_mask = &mcf_edma_dmamask,
551 .coherent_dma_mask = DMA_BIT_MASK(32),
552 .platform_data = &mcf_edma_data,
555 #endif /* IS_ENABLED(CONFIG_MCF_EDMA) */
558 static struct mcf_esdhc_platform_data mcf_esdhc_data = {
560 .cd_type = ESDHC_CD_NONE,
563 static struct resource mcf_esdhc_resources[] = {
565 .start = MCFSDHC_BASE,
566 .end = MCFSDHC_BASE + MCFSDHC_SIZE - 1,
567 .flags = IORESOURCE_MEM,
569 .start = MCF_IRQ_SDHC,
571 .flags = IORESOURCE_IRQ,
575 static struct platform_device mcf_esdhc = {
576 .name = "sdhci-esdhc-mcf",
578 .num_resources = ARRAY_SIZE(mcf_esdhc_resources),
579 .resource = mcf_esdhc_resources,
580 .dev.platform_data = &mcf_esdhc_data,
582 #endif /* MCFSDHC_BASE */
584 #if IS_ENABLED(CONFIG_CAN_FLEXCAN)
586 #include <linux/can/platform/flexcan.h>
588 static struct flexcan_platform_data mcf5441x_flexcan_info = {
590 .clock_frequency = 120000000,
593 static struct resource mcf5441x_flexcan0_resource[] = {
595 .start = MCFFLEXCAN_BASE0,
596 .end = MCFFLEXCAN_BASE0 + MCFFLEXCAN_SIZE,
597 .flags = IORESOURCE_MEM,
600 .start = MCF_IRQ_IFL0,
602 .flags = IORESOURCE_IRQ,
605 .start = MCF_IRQ_BOFF0,
606 .end = MCF_IRQ_BOFF0,
607 .flags = IORESOURCE_IRQ,
610 .start = MCF_IRQ_ERR0,
612 .flags = IORESOURCE_IRQ,
616 static struct platform_device mcf_flexcan0 = {
617 .name = "flexcan-mcf5441x",
619 .num_resources = ARRAY_SIZE(mcf5441x_flexcan0_resource),
620 .resource = mcf5441x_flexcan0_resource,
621 .dev.platform_data = &mcf5441x_flexcan_info,
623 #endif /* IS_ENABLED(CONFIG_CAN_FLEXCAN) */
625 static struct platform_device *mcf_devices[] __initdata = {
627 #if IS_ENABLED(CONFIG_FEC)
633 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
636 #if IS_ENABLED(CONFIG_I2C_IMX)
654 #if IS_ENABLED(CONFIG_MCF_EDMA)
660 #if IS_ENABLED(CONFIG_CAN_FLEXCAN)
666 * Some ColdFire UARTs let you set the IRQ line to use.
668 static void __init mcf_uart_set_irq(void)
671 /* UART0 interrupt setup */
672 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
673 writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
674 mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
676 /* UART1 interrupt setup */
677 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
678 writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
679 mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
683 static int __init mcf_init_devices(void)
686 platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
690 arch_initcall(mcf_init_devices);