1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
5 prompt "CPU family support"
6 default M68KCLASSIC if MMU
7 default COLDFIRE if !MMU
9 The Freescale (was Motorola) M68K family of processors implements
10 the full 68000 processor instruction set.
11 The Freescale ColdFire family of processors is a modern derivative
12 of the 68000 processor family. They are mainly targeted at embedded
13 applications, and are all System-On-Chip (SOC) devices, as opposed
14 to stand alone CPUs. They implement a subset of the original 68000
15 processor instruction set.
16 If you anticipate running this kernel on a computer with a classic
17 MC68xxx processor, select M68KCLASSIC.
18 If you anticipate running this kernel on a computer with a ColdFire
19 processor, select COLDFIRE.
22 bool "Classic M68K CPU family support"
23 select HAVE_ARCH_PFN_VALID
26 bool "Coldfire CPU family support"
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select CPU_HAS_NO_BITFIELDS
29 select CPU_HAS_NO_MULDIV64
32 select HAVE_LEGACY_CLK
41 select CPU_HAS_NO_BITFIELDS
42 select CPU_HAS_NO_MULDIV64
43 select CPU_HAS_NO_UNALIGNED
45 select CPU_NO_EFFICIENT_FFS
48 The Freescale (was Motorola) 68000 CPU is the first generation of
49 the well known M68K family of processors. The CPU core as well as
50 being available as a stand alone CPU was also used in many
51 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
56 select CPU_HAS_NO_BITFIELDS
57 select CPU_HAS_NO_UNALIGNED
58 select CPU_NO_EFFICIENT_FFS
60 The Freescale (was then Motorola) CPU32 is a CPU core that is
61 based on the 68020 processor. For the most part it is used in
62 System-On-Chip parts, and does not contain a paging MMU.
68 select CPU_HAS_ADDRESS_SPACES
70 If you anticipate running this kernel on a computer with a MC68020
71 processor, say Y. Otherwise, say N. Note that the 68020 requires a
72 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
73 Sun 3, which provides its own version.
77 depends on MMU && !MMU_SUN3
79 select CPU_HAS_ADDRESS_SPACES
81 If you anticipate running this kernel on a computer with a MC68030
82 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
83 work, as it does not include an MMU (Memory Management Unit).
87 depends on MMU && !MMU_SUN3
89 select CPU_HAS_ADDRESS_SPACES
91 If you anticipate running this kernel on a computer with a MC68LC040
92 or MC68040 processor, say Y. Otherwise, say N. Note that an
93 MC68EC040 will not work, as it does not include an MMU (Memory
98 depends on MMU && !MMU_SUN3
100 select CPU_HAS_ADDRESS_SPACES
102 If you anticipate running this kernel on a computer with a MC68060
103 processor, say Y. Otherwise, say N.
110 Motorola 68328 processor support.
117 Motorola 68EX328 processor support.
124 Motorola 68VZ328 processor support.
131 prompt "ColdFire SoC type"
134 Select the type of ColdFire System-on-Chip (SoC) that you want
140 select COLDFIRE_SW_A7
142 select CPU_NO_EFFICIENT_FFS
144 Motorola ColdFire 5206 processor support.
149 select COLDFIRE_SW_A7
151 select CPU_NO_EFFICIENT_FFS
153 Motorola ColdFire 5206e processor support.
158 select GENERIC_CLOCKEVENTS
159 select HAVE_CACHE_SPLIT
161 Freescale Coldfire 5207/5208 processor support.
166 select GENERIC_CLOCKEVENTS
167 select HAVE_CACHE_SPLIT
170 Freescale Coldfire 5230/1/2/4/5 processor support
175 select COLDFIRE_SW_A7
177 select CPU_NO_EFFICIENT_FFS
179 Motorola ColdFire 5249 processor support.
184 select COLDFIRE_SW_A7
186 select CPU_NO_EFFICIENT_FFS
188 Freescale (Motorola) Coldfire 5251/5253 processor support.
194 select HAVE_CACHE_SPLIT
196 select GENERIC_CLOCKEVENTS
198 Freescale (Motorola) ColdFire 5270/5271 processor support.
203 select COLDFIRE_SW_A7
205 select CPU_NO_EFFICIENT_FFS
207 Motorola ColdFire 5272 processor support.
213 select HAVE_CACHE_SPLIT
215 select GENERIC_CLOCKEVENTS
217 Freescale (Motorola) ColdFire 5274/5275 processor support.
222 select GENERIC_CLOCKEVENTS
223 select HAVE_CACHE_SPLIT
226 Motorola ColdFire 5280/5282 processor support.
231 select COLDFIRE_SW_A7
234 select CPU_NO_EFFICIENT_FFS
236 Motorola ColdFire 5307 processor support.
244 Freescale (Motorola) ColdFire 532x processor support.
252 Freescale ColdFire 537x processor support.
257 select COLDFIRE_SW_A7
260 select CPU_NO_EFFICIENT_FFS
262 Motorola ColdFire 5407 processor support.
267 select MMU_COLDFIRE if MMU
271 select CPU_NO_EFFICIENT_FFS
273 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
277 select MMU_COLDFIRE if MMU
282 select CPU_NO_EFFICIENT_FFS
284 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
288 select MMU_COLDFIRE if MMU
289 select GENERIC_CLOCKEVENTS
292 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
309 comment "Processor Specific Options"
312 bool "Math emulation support"
315 At some point in the future, this will cause floating-point math
316 instructions to be emulated by the kernel on machines that lack a
317 floating-point math coprocessor. Thrill-seekers and chronically
318 sleep-deprived psychotic hacker types can say Y now, everyone else
319 should probably wait a while.
321 config M68KFPU_EMU_EXTRAPREC
322 bool "Math emulation extra precision"
323 depends on M68KFPU_EMU
325 The fpu uses normally a few bit more during calculations for
326 correct rounding, the emulator can (often) do the same but this
327 extra calculation can cost quite some time, so you can disable
328 it here. The emulator will then "only" calculate with a 64 bit
329 mantissa and round slightly incorrect, what is more than enough
332 config M68KFPU_EMU_ONLY
333 bool "Math emulation only kernel"
334 depends on M68KFPU_EMU
336 This option prevents any floating-point instructions from being
337 compiled into the kernel, thereby the kernel doesn't save any
338 floating point context anymore during task switches, so this
339 kernel will only be usable on machines without a floating-point
340 math coprocessor. This makes the kernel a bit faster as no tests
341 needs to be executed whether a floating-point instruction in the
342 kernel should be executed or not.
345 bool "Advanced configuration options"
348 This gives you access to some advanced options for the CPU. The
349 defaults should be fine for most users, but these options may make
350 it possible for you to improve performance somewhat if you know what
353 Note that the answer to this question won't directly affect the
354 kernel: saying N will just cause the configurator to skip all
355 the questions about these options.
357 Most users should say N to this question.
360 bool "Use read-modify-write instructions"
363 This allows to use certain instructions that work with indivisible
364 read-modify-write bus cycles. While this is faster than the
365 workaround of disabling interrupts, it can conflict with DMA
366 ( = direct memory access) on many Amiga systems, and it is also said
367 to destabilize other machines. It is very likely that this will
368 cause serious problems on any Amiga or Atari Medusa if set. The only
369 configuration where it should work are 68030-based Ataris, where it
370 apparently improves performance. But you've been warned! Unless you
371 really know what you are doing, say N. Try Y only if you're quite
374 config SINGLE_MEMORY_CHUNK
375 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
377 default y if SUN3 || MMU_COLDFIRE
379 Ignore all but the first contiguous chunk of physical memory for VM
380 purposes. This will save a few bytes kernel size and may speed up
382 When this option os set to N, you may want to lower "Maximum zone
383 order" to save memory that could be wasted for unused memory map.
386 config ARCH_DISCONTIGMEM_ENABLE
388 def_bool MMU && !SINGLE_MEMORY_CHUNK
390 config FORCE_MAX_ZONEORDER
391 int "Maximum zone order" if ADVANCED
392 depends on !SINGLE_MEMORY_CHUNK
395 The kernel memory allocator divides physically contiguous memory
396 blocks into "zones", where each zone is a power of two number of
397 pages. This option selects the largest power of two that the kernel
398 keeps in the memory allocator. If you need to allocate very large
399 blocks of physically contiguous memory, then you may need to
402 For systems that have holes in their physical address space this
403 value also defines the minimal size of the hole that allows
404 freeing unused memory map.
406 This config option is actually maximum order plus one. For example,
407 a value of 11 means that the largest free memory block is 2^10 pages.
409 config 060_WRITETHROUGH
410 bool "Use write-through caching for 68060 supervisor accesses"
411 depends on ADVANCED && M68060
413 The 68060 generally uses copyback caching of recently accessed data.
414 Copyback caching means that memory writes will be held in an on-chip
415 cache and only written back to memory some time later. Saying Y
416 here will force supervisor (kernel) accesses to use writethrough
417 caching. Writethrough caching means that data is written to memory
418 straight away, so that cache and memory data always agree.
419 Writethrough caching is less efficient, but is needed for some
420 drivers on 68060 based systems where the 68060 bus snooping signal
421 is hardwired on. The 53c710 SCSI driver is known to suffer from
432 depends on DISCONTIGMEM
434 config CPU_HAS_NO_BITFIELDS
437 config CPU_HAS_NO_MULDIV64
440 config CPU_HAS_NO_UNALIGNED
443 config CPU_HAS_ADDRESS_SPACES
449 config COLDFIRE_SW_A7
452 config HAVE_CACHE_SPLIT
465 int "Set the core clock frequency"
466 default "25000000" if M5206
467 default "54000000" if M5206e
468 default "166666666" if M520x
469 default "140000000" if M5249
470 default "150000000" if M527x || M523x
471 default "90000000" if M5307
472 default "50000000" if M5407
473 default "266000000" if M54xx
477 Define the CPU clock frequency in use. This is the core clock
478 frequency, it may or may not be the same as the external clock
479 crystal fitted to your board. Some processors have an internal
480 PLL and can have their frequency programmed at run time, others
481 use internal dividers. In general the kernel won't setup a PLL
482 if it is fitted (there are some exceptions). This value will be
483 specific to the exact CPU that you are using.
486 bool "Old mask 5307 (1H55J) silicon"
489 Build support for the older revision ColdFire 5307 silicon.
490 Specifically this is the 1H55J mask revision.
494 prompt "Split Cache Configuration"
500 Use all of the ColdFire CPU cache memory as an instruction cache.
505 Use all of the ColdFire CPU cache memory as a data cache.
510 Split the ColdFire CPU cache, and use half as an instruction cache
511 and half as a data cache.
517 prompt "Data cache mode"
518 default CACHE_WRITETHRU
520 config CACHE_WRITETHRU
523 The ColdFire CPU cache is set into Write-through mode.
525 config CACHE_COPYBACK
528 The ColdFire CPU cache is set into Copy-back mode.