1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
5 prompt "CPU family support"
6 default M68KCLASSIC if MMU
7 default COLDFIRE if !MMU
9 The Freescale (was Motorola) M68K family of processors implements
10 the full 68000 processor instruction set.
11 The Freescale ColdFire family of processors is a modern derivative
12 of the 68000 processor family. They are mainly targeted at embedded
13 applications, and are all System-On-Chip (SOC) devices, as opposed
14 to stand alone CPUs. They implement a subset of the original 68000
15 processor instruction set.
16 If you anticipate running this kernel on a computer with a classic
17 MC68xxx processor, select M68KCLASSIC.
18 If you anticipate running this kernel on a computer with a ColdFire
19 processor, select COLDFIRE.
22 bool "Classic M68K CPU family support"
23 select HAVE_ARCH_PFN_VALID
26 bool "Coldfire CPU family support"
27 select CPU_HAS_NO_BITFIELDS
29 select CPU_HAS_NO_MULDIV64
32 select HAVE_LEGACY_CLK
41 select CPU_HAS_NO_BITFIELDS
43 select CPU_HAS_NO_MULDIV64
44 select CPU_HAS_NO_UNALIGNED
46 select CPU_NO_EFFICIENT_FFS
48 select LEGACY_TIMER_TICK
50 The Freescale (was Motorola) 68000 CPU is the first generation of
51 the well known M68K family of processors. The CPU core as well as
52 being available as a stand alone CPU was also used in many
53 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
60 select CPU_HAS_ADDRESS_SPACES
62 If you anticipate running this kernel on a computer with a MC68020
63 processor, say Y. Otherwise, say N. Note that the 68020 requires a
64 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
65 Sun 3, which provides its own version.
69 depends on MMU && !MMU_SUN3
71 select CPU_HAS_ADDRESS_SPACES
73 If you anticipate running this kernel on a computer with a MC68030
74 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
75 work, as it does not include an MMU (Memory Management Unit).
79 depends on MMU && !MMU_SUN3
81 select CPU_HAS_ADDRESS_SPACES
83 If you anticipate running this kernel on a computer with a MC68LC040
84 or MC68040 processor, say Y. Otherwise, say N. Note that an
85 MC68EC040 will not work, as it does not include an MMU (Memory
90 depends on MMU && !MMU_SUN3
92 select CPU_HAS_ADDRESS_SPACES
94 If you anticipate running this kernel on a computer with a MC68060
95 processor, say Y. Otherwise, say N.
102 Motorola 68328 processor support.
109 Motorola 68EX328 processor support.
116 Motorola 68VZ328 processor support.
123 prompt "ColdFire SoC type"
126 Select the type of ColdFire System-on-Chip (SoC) that you want
132 select COLDFIRE_SW_A7
133 select COLDFIRE_TIMERS
135 select CPU_NO_EFFICIENT_FFS
137 Motorola ColdFire 5206 processor support.
142 select COLDFIRE_SW_A7
143 select COLDFIRE_TIMERS
145 select CPU_NO_EFFICIENT_FFS
147 Motorola ColdFire 5206e processor support.
152 select COLDFIRE_PIT_TIMER
153 select HAVE_CACHE_SPLIT
155 Freescale Coldfire 5207/5208 processor support.
160 select COLDFIRE_PIT_TIMER
161 select HAVE_CACHE_SPLIT
164 Freescale Coldfire 5230/1/2/4/5 processor support
169 select COLDFIRE_SW_A7
170 select COLDFIRE_TIMERS
172 select CPU_NO_EFFICIENT_FFS
174 Motorola ColdFire 5249 processor support.
179 select COLDFIRE_SW_A7
180 select COLDFIRE_TIMERS
182 select CPU_NO_EFFICIENT_FFS
184 Freescale (Motorola) Coldfire 5251/5253 processor support.
189 select COLDFIRE_PIT_TIMER
191 select HAVE_CACHE_SPLIT
194 Freescale (Motorola) ColdFire 5270/5271 processor support.
199 select COLDFIRE_SW_A7
200 select COLDFIRE_TIMERS
202 select CPU_NO_EFFICIENT_FFS
204 Motorola ColdFire 5272 processor support.
209 select COLDFIRE_PIT_TIMER
211 select HAVE_CACHE_SPLIT
214 Freescale (Motorola) ColdFire 5274/5275 processor support.
219 select COLDFIRE_PIT_TIMER
220 select HAVE_CACHE_SPLIT
223 Motorola ColdFire 5280/5282 processor support.
228 select COLDFIRE_TIMERS
229 select COLDFIRE_SW_A7
232 select CPU_NO_EFFICIENT_FFS
234 Motorola ColdFire 5307 processor support.
239 select COLDFIRE_TIMERS
243 Freescale (Motorola) ColdFire 532x processor support.
248 select COLDFIRE_TIMERS
252 Freescale ColdFire 537x processor support.
257 select COLDFIRE_SW_A7
258 select COLDFIRE_TIMERS
261 select CPU_NO_EFFICIENT_FFS
263 Motorola ColdFire 5407 processor support.
268 select COLDFIRE_SLTIMERS
269 select MMU_COLDFIRE if MMU
273 select CPU_NO_EFFICIENT_FFS
275 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
279 select COLDFIRE_SLTIMERS
280 select MMU_COLDFIRE if MMU
285 select CPU_NO_EFFICIENT_FFS
287 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
291 select COLDFIRE_PIT_TIMER
292 select MMU_COLDFIRE if MMU
295 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
309 config COLDFIRE_PIT_TIMER
312 config COLDFIRE_TIMERS
314 select LEGACY_TIMER_TICK
316 config COLDFIRE_SLTIMERS
318 select LEGACY_TIMER_TICK
322 comment "Processor Specific Options"
325 bool "Math emulation support"
326 depends on M68KCLASSIC && FPU
328 At some point in the future, this will cause floating-point math
329 instructions to be emulated by the kernel on machines that lack a
330 floating-point math coprocessor. Thrill-seekers and chronically
331 sleep-deprived psychotic hacker types can say Y now, everyone else
332 should probably wait a while.
334 config M68KFPU_EMU_EXTRAPREC
335 bool "Math emulation extra precision"
336 depends on M68KFPU_EMU
338 The fpu uses normally a few bit more during calculations for
339 correct rounding, the emulator can (often) do the same but this
340 extra calculation can cost quite some time, so you can disable
341 it here. The emulator will then "only" calculate with a 64 bit
342 mantissa and round slightly incorrect, what is more than enough
345 config M68KFPU_EMU_ONLY
346 bool "Math emulation only kernel"
347 depends on M68KFPU_EMU
349 This option prevents any floating-point instructions from being
350 compiled into the kernel, thereby the kernel doesn't save any
351 floating point context anymore during task switches, so this
352 kernel will only be usable on machines without a floating-point
353 math coprocessor. This makes the kernel a bit faster as no tests
354 needs to be executed whether a floating-point instruction in the
355 kernel should be executed or not.
358 bool "Advanced configuration options"
361 This gives you access to some advanced options for the CPU. The
362 defaults should be fine for most users, but these options may make
363 it possible for you to improve performance somewhat if you know what
366 Note that the answer to this question won't directly affect the
367 kernel: saying N will just cause the configurator to skip all
368 the questions about these options.
370 Most users should say N to this question.
373 bool "Use read-modify-write instructions"
374 depends on ADVANCED && !CPU_HAS_NO_CAS
376 This allows to use certain instructions that work with indivisible
377 read-modify-write bus cycles. While this is faster than the
378 workaround of disabling interrupts, it can conflict with DMA
379 ( = direct memory access) on many Amiga systems, and it is also said
380 to destabilize other machines. It is very likely that this will
381 cause serious problems on any Amiga or Atari Medusa if set. The only
382 configuration where it should work are 68030-based Ataris, where it
383 apparently improves performance. But you've been warned! Unless you
384 really know what you are doing, say N. Try Y only if you're quite
387 config SINGLE_MEMORY_CHUNK
388 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
390 default y if SUN3 || MMU_COLDFIRE
392 Ignore all but the first contiguous chunk of physical memory for VM
393 purposes. This will save a few bytes kernel size and may speed up
395 When this option os set to N, you may want to lower "Maximum zone
396 order" to save memory that could be wasted for unused memory map.
399 config ARCH_FORCE_MAX_ORDER
400 int "Order of maximal physically contiguous allocations" if ADVANCED
401 depends on !SINGLE_MEMORY_CHUNK
404 The kernel page allocator limits the size of maximal physically
405 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
406 defines the maximal power of two of number of pages that can be
407 allocated as a single contiguous block. This option allows
408 overriding the default setting when ability to allocate very
409 large blocks of physically contiguous memory is required.
411 For systems that have holes in their physical address space this
412 value also defines the minimal size of the hole that allows
413 freeing unused memory map.
415 Don't change if unsure.
417 config 060_WRITETHROUGH
418 bool "Use write-through caching for 68060 supervisor accesses"
419 depends on ADVANCED && M68060
421 The 68060 generally uses copyback caching of recently accessed data.
422 Copyback caching means that memory writes will be held in an on-chip
423 cache and only written back to memory some time later. Saying Y
424 here will force supervisor (kernel) accesses to use writethrough
425 caching. Writethrough caching means that data is written to memory
426 straight away, so that cache and memory data always agree.
427 Writethrough caching is less efficient, but is needed for some
428 drivers on 68060 based systems where the 68060 bus snooping signal
429 is hardwired on. The 53c710 SCSI driver is known to suffer from
437 config CPU_HAS_NO_BITFIELDS
440 config CPU_HAS_NO_CAS
443 config CPU_HAS_NO_MULDIV64
446 config CPU_HAS_NO_UNALIGNED
449 config CPU_HAS_ADDRESS_SPACES
451 select ALTERNATE_USER_ADDRESS_SPACE
456 config COLDFIRE_SW_A7
459 config HAVE_CACHE_SPLIT
472 int "Set the core clock frequency"
473 default "25000000" if M5206
474 default "54000000" if M5206e
475 default "166666666" if M520x
476 default "140000000" if M5249
477 default "150000000" if M527x || M523x
478 default "90000000" if M5307
479 default "50000000" if M5407
480 default "266000000" if M54xx
484 Define the CPU clock frequency in use. This is the core clock
485 frequency, it may or may not be the same as the external clock
486 crystal fitted to your board. Some processors have an internal
487 PLL and can have their frequency programmed at run time, others
488 use internal dividers. In general the kernel won't setup a PLL
489 if it is fitted (there are some exceptions). This value will be
490 specific to the exact CPU that you are using.
493 bool "Old mask 5307 (1H55J) silicon"
496 Build support for the older revision ColdFire 5307 silicon.
497 Specifically this is the 1H55J mask revision.
501 prompt "Split Cache Configuration"
507 Use all of the ColdFire CPU cache memory as an instruction cache.
512 Use all of the ColdFire CPU cache memory as a data cache.
517 Split the ColdFire CPU cache, and use half as an instruction cache
518 and half as a data cache.
520 endif # HAVE_CACHE_SPLIT
524 prompt "Data cache mode"
525 default CACHE_WRITETHRU
527 config CACHE_WRITETHRU
530 The ColdFire CPU cache is set into Write-through mode.
532 config CACHE_COPYBACK
535 The ColdFire CPU cache is set into Copy-back mode.
537 endif # HAVE_CACHE_CB
539 # Coldfire cores that do not have a data cache configured can do coherent DMA.
540 config COLDFIRE_COHERENT_DMA
544 depends on !HAVE_CACHE_CB && !CACHE_D && !CACHE_BOTH
546 config M68K_NONCOHERENT_DMA
549 depends on HAS_DMA && !COLDFIRE_COHERENT_DMA