1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
5 prompt "CPU family support"
6 default M68KCLASSIC if MMU
7 default COLDFIRE if !MMU
9 The Freescale (was Motorola) M68K family of processors implements
10 the full 68000 processor instruction set.
11 The Freescale ColdFire family of processors is a modern derivative
12 of the 68000 processor family. They are mainly targeted at embedded
13 applications, and are all System-On-Chip (SOC) devices, as opposed
14 to stand alone CPUs. They implement a subset of the original 68000
15 processor instruction set.
16 If you anticipate running this kernel on a computer with a classic
17 MC68xxx processor, select M68KCLASSIC.
18 If you anticipate running this kernel on a computer with a ColdFire
19 processor, select COLDFIRE.
22 bool "Classic M68K CPU family support"
23 select HAVE_ARCH_PFN_VALID
26 bool "Coldfire CPU family support"
27 select CPU_HAS_NO_BITFIELDS
29 select CPU_HAS_NO_MULDIV64
32 select HAVE_LEGACY_CLK
33 select HAVE_PAGE_SIZE_8KB if !MMU
42 select CPU_HAS_NO_BITFIELDS
44 select CPU_HAS_NO_MULDIV64
45 select CPU_HAS_NO_UNALIGNED
47 select CPU_NO_EFFICIENT_FFS
49 select HAVE_PAGE_SIZE_4KB
50 select LEGACY_TIMER_TICK
52 The Freescale (was Motorola) 68000 CPU is the first generation of
53 the well known M68K family of processors. The CPU core as well as
54 being available as a stand alone CPU was also used in many
55 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
62 select CPU_HAS_ADDRESS_SPACES
64 If you anticipate running this kernel on a computer with a MC68020
65 processor, say Y. Otherwise, say N. Note that the 68020 requires a
66 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
67 Sun 3, which provides its own version.
71 depends on MMU && !MMU_SUN3
73 select CPU_HAS_ADDRESS_SPACES
75 If you anticipate running this kernel on a computer with a MC68030
76 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
77 work, as it does not include an MMU (Memory Management Unit).
81 depends on MMU && !MMU_SUN3
83 select CPU_HAS_ADDRESS_SPACES
85 If you anticipate running this kernel on a computer with a MC68LC040
86 or MC68040 processor, say Y. Otherwise, say N. Note that an
87 MC68EC040 will not work, as it does not include an MMU (Memory
92 depends on MMU && !MMU_SUN3
94 select CPU_HAS_ADDRESS_SPACES
96 If you anticipate running this kernel on a computer with a MC68060
97 processor, say Y. Otherwise, say N.
104 Motorola 68328 processor support.
111 Motorola 68EX328 processor support.
118 Motorola 68VZ328 processor support.
125 prompt "ColdFire SoC type"
128 Select the type of ColdFire System-on-Chip (SoC) that you want
134 select COLDFIRE_SW_A7
135 select COLDFIRE_TIMERS
137 select CPU_NO_EFFICIENT_FFS
139 Motorola ColdFire 5206 processor support.
144 select COLDFIRE_SW_A7
145 select COLDFIRE_TIMERS
147 select CPU_NO_EFFICIENT_FFS
149 Motorola ColdFire 5206e processor support.
154 select COLDFIRE_PIT_TIMER
155 select HAVE_CACHE_SPLIT
157 Freescale Coldfire 5207/5208 processor support.
162 select COLDFIRE_PIT_TIMER
163 select HAVE_CACHE_SPLIT
166 Freescale Coldfire 5230/1/2/4/5 processor support
171 select COLDFIRE_SW_A7
172 select COLDFIRE_TIMERS
174 select CPU_NO_EFFICIENT_FFS
176 Motorola ColdFire 5249 processor support.
181 select COLDFIRE_SW_A7
182 select COLDFIRE_TIMERS
184 select CPU_NO_EFFICIENT_FFS
186 Freescale (Motorola) Coldfire 5251/5253 processor support.
191 select COLDFIRE_PIT_TIMER
193 select HAVE_CACHE_SPLIT
196 Freescale (Motorola) ColdFire 5270/5271 processor support.
201 select COLDFIRE_SW_A7
202 select COLDFIRE_TIMERS
204 select CPU_NO_EFFICIENT_FFS
206 Motorola ColdFire 5272 processor support.
211 select COLDFIRE_PIT_TIMER
213 select HAVE_CACHE_SPLIT
216 Freescale (Motorola) ColdFire 5274/5275 processor support.
221 select COLDFIRE_PIT_TIMER
222 select HAVE_CACHE_SPLIT
225 Motorola ColdFire 5280/5282 processor support.
230 select COLDFIRE_TIMERS
231 select COLDFIRE_SW_A7
234 select CPU_NO_EFFICIENT_FFS
236 Motorola ColdFire 5307 processor support.
241 select COLDFIRE_TIMERS
245 Freescale (Motorola) ColdFire 532x processor support.
250 select COLDFIRE_TIMERS
254 Freescale ColdFire 537x processor support.
259 select COLDFIRE_SW_A7
260 select COLDFIRE_TIMERS
263 select CPU_NO_EFFICIENT_FFS
265 Motorola ColdFire 5407 processor support.
270 select COLDFIRE_SLTIMERS
271 select MMU_COLDFIRE if MMU
275 select CPU_NO_EFFICIENT_FFS
277 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
281 select COLDFIRE_SLTIMERS
282 select MMU_COLDFIRE if MMU
287 select CPU_NO_EFFICIENT_FFS
289 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
293 select COLDFIRE_PIT_TIMER
294 select MMU_COLDFIRE if MMU
297 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
311 config COLDFIRE_PIT_TIMER
314 config COLDFIRE_TIMERS
316 select LEGACY_TIMER_TICK
318 config COLDFIRE_SLTIMERS
320 select LEGACY_TIMER_TICK
324 comment "Processor Specific Options"
327 bool "Math emulation support"
328 depends on M68KCLASSIC && FPU
330 At some point in the future, this will cause floating-point math
331 instructions to be emulated by the kernel on machines that lack a
332 floating-point math coprocessor. Thrill-seekers and chronically
333 sleep-deprived psychotic hacker types can say Y now, everyone else
334 should probably wait a while.
336 config M68KFPU_EMU_EXTRAPREC
337 bool "Math emulation extra precision"
338 depends on M68KFPU_EMU
340 The fpu uses normally a few bit more during calculations for
341 correct rounding, the emulator can (often) do the same but this
342 extra calculation can cost quite some time, so you can disable
343 it here. The emulator will then "only" calculate with a 64 bit
344 mantissa and round slightly incorrect, what is more than enough
347 config M68KFPU_EMU_ONLY
348 bool "Math emulation only kernel"
349 depends on M68KFPU_EMU
351 This option prevents any floating-point instructions from being
352 compiled into the kernel, thereby the kernel doesn't save any
353 floating point context anymore during task switches, so this
354 kernel will only be usable on machines without a floating-point
355 math coprocessor. This makes the kernel a bit faster as no tests
356 needs to be executed whether a floating-point instruction in the
357 kernel should be executed or not.
360 bool "Advanced configuration options"
363 This gives you access to some advanced options for the CPU. The
364 defaults should be fine for most users, but these options may make
365 it possible for you to improve performance somewhat if you know what
368 Note that the answer to this question won't directly affect the
369 kernel: saying N will just cause the configurator to skip all
370 the questions about these options.
372 Most users should say N to this question.
375 bool "Use read-modify-write instructions"
376 depends on ADVANCED && !CPU_HAS_NO_CAS
378 This allows to use certain instructions that work with indivisible
379 read-modify-write bus cycles. While this is faster than the
380 workaround of disabling interrupts, it can conflict with DMA
381 ( = direct memory access) on many Amiga systems, and it is also said
382 to destabilize other machines. It is very likely that this will
383 cause serious problems on any Amiga or Atari Medusa if set. The only
384 configuration where it should work are 68030-based Ataris, where it
385 apparently improves performance. But you've been warned! Unless you
386 really know what you are doing, say N. Try Y only if you're quite
389 config SINGLE_MEMORY_CHUNK
390 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
392 default y if SUN3 || MMU_COLDFIRE
394 Ignore all but the first contiguous chunk of physical memory for VM
395 purposes. This will save a few bytes kernel size and may speed up
397 When this option os set to N, you may want to lower "Maximum zone
398 order" to save memory that could be wasted for unused memory map.
401 config ARCH_FORCE_MAX_ORDER
402 int "Order of maximal physically contiguous allocations" if ADVANCED
403 depends on !SINGLE_MEMORY_CHUNK
406 The kernel page allocator limits the size of maximal physically
407 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
408 defines the maximal power of two of number of pages that can be
409 allocated as a single contiguous block. This option allows
410 overriding the default setting when ability to allocate very
411 large blocks of physically contiguous memory is required.
413 For systems that have holes in their physical address space this
414 value also defines the minimal size of the hole that allows
415 freeing unused memory map.
417 Don't change if unsure.
419 config 060_WRITETHROUGH
420 bool "Use write-through caching for 68060 supervisor accesses"
421 depends on ADVANCED && M68060
423 The 68060 generally uses copyback caching of recently accessed data.
424 Copyback caching means that memory writes will be held in an on-chip
425 cache and only written back to memory some time later. Saying Y
426 here will force supervisor (kernel) accesses to use writethrough
427 caching. Writethrough caching means that data is written to memory
428 straight away, so that cache and memory data always agree.
429 Writethrough caching is less efficient, but is needed for some
430 drivers on 68060 based systems where the 68060 bus snooping signal
431 is hardwired on. The 53c710 SCSI driver is known to suffer from
439 config CPU_HAS_NO_BITFIELDS
442 config CPU_HAS_NO_CAS
445 config CPU_HAS_NO_MULDIV64
448 config CPU_HAS_NO_UNALIGNED
451 config CPU_HAS_ADDRESS_SPACES
453 select ALTERNATE_USER_ADDRESS_SPACE
458 config COLDFIRE_SW_A7
461 config HAVE_CACHE_SPLIT
474 int "Set the core clock frequency"
475 default "25000000" if M5206
476 default "54000000" if M5206e
477 default "166666666" if M520x
478 default "140000000" if M5249
479 default "150000000" if M527x || M523x
480 default "90000000" if M5307
481 default "50000000" if M5407
482 default "266000000" if M54xx
486 Define the CPU clock frequency in use. This is the core clock
487 frequency, it may or may not be the same as the external clock
488 crystal fitted to your board. Some processors have an internal
489 PLL and can have their frequency programmed at run time, others
490 use internal dividers. In general the kernel won't setup a PLL
491 if it is fitted (there are some exceptions). This value will be
492 specific to the exact CPU that you are using.
495 bool "Old mask 5307 (1H55J) silicon"
498 Build support for the older revision ColdFire 5307 silicon.
499 Specifically this is the 1H55J mask revision.
503 prompt "Split Cache Configuration"
509 Use all of the ColdFire CPU cache memory as an instruction cache.
514 Use all of the ColdFire CPU cache memory as a data cache.
519 Split the ColdFire CPU cache, and use half as an instruction cache
520 and half as a data cache.
522 endif # HAVE_CACHE_SPLIT
526 prompt "Data cache mode"
527 default CACHE_WRITETHRU
529 config CACHE_WRITETHRU
532 The ColdFire CPU cache is set into Write-through mode.
534 config CACHE_COPYBACK
537 The ColdFire CPU cache is set into Copy-back mode.
539 endif # HAVE_CACHE_CB
541 # Coldfire cores that do not have a data cache configured can do coherent DMA.
542 config COLDFIRE_COHERENT_DMA
546 depends on !HAVE_CACHE_CB && !CACHE_D && !CACHE_BOTH
548 config M68K_NONCOHERENT_DMA
551 depends on HAS_DMA && !COLDFIRE_COHERENT_DMA