1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
5 #include <linux/init.h>
6 #include <linux/sched.h>
9 #include <linux/hugetlb.h>
10 #include <linux/export.h>
13 #include <asm/bootinfo.h>
14 #include <asm/mmu_context.h>
15 #include <asm/pgtable.h>
18 void local_flush_tlb_all(void)
20 invtlb_all(INVTLB_CURRENT_ALL, 0, 0);
22 EXPORT_SYMBOL(local_flush_tlb_all);
24 void local_flush_tlb_user(void)
26 invtlb_all(INVTLB_CURRENT_GFALSE, 0, 0);
28 EXPORT_SYMBOL(local_flush_tlb_user);
30 void local_flush_tlb_kernel(void)
32 invtlb_all(INVTLB_CURRENT_GTRUE, 0, 0);
34 EXPORT_SYMBOL(local_flush_tlb_kernel);
37 * All entries common to a mm share an asid. To effectively flush
38 * these entries, we just bump the asid.
40 void local_flush_tlb_mm(struct mm_struct *mm)
46 cpu = smp_processor_id();
48 if (asid_valid(mm, cpu))
49 drop_mmu_context(mm, cpu);
51 cpumask_clear_cpu(cpu, mm_cpumask(mm));
56 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
59 struct mm_struct *mm = vma->vm_mm;
60 int cpu = smp_processor_id();
62 if (asid_valid(mm, cpu)) {
63 unsigned long size, flags;
65 local_irq_save(flags);
66 start = round_down(start, PAGE_SIZE << 1);
67 end = round_up(end, PAGE_SIZE << 1);
68 size = (end - start) >> (PAGE_SHIFT + 1);
69 if (size <= (current_cpu_data.tlbsizestlbsets ?
70 current_cpu_data.tlbsize / 8 :
71 current_cpu_data.tlbsize / 2)) {
72 int asid = cpu_asid(cpu, mm);
75 invtlb(INVTLB_ADDR_GFALSE_AND_ASID, asid, start);
76 start += (PAGE_SIZE << 1);
79 drop_mmu_context(mm, cpu);
81 local_irq_restore(flags);
83 cpumask_clear_cpu(cpu, mm_cpumask(mm));
87 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
89 unsigned long size, flags;
91 local_irq_save(flags);
92 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
93 size = (size + 1) >> 1;
94 if (size <= (current_cpu_data.tlbsizestlbsets ?
95 current_cpu_data.tlbsize / 8 :
96 current_cpu_data.tlbsize / 2)) {
98 start &= (PAGE_MASK << 1);
99 end += ((PAGE_SIZE << 1) - 1);
100 end &= (PAGE_MASK << 1);
102 while (start < end) {
103 invtlb_addr(INVTLB_ADDR_GTRUE_OR_ASID, 0, start);
104 start += (PAGE_SIZE << 1);
107 local_flush_tlb_kernel();
109 local_irq_restore(flags);
112 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
114 int cpu = smp_processor_id();
116 if (asid_valid(vma->vm_mm, cpu)) {
119 newpid = cpu_asid(cpu, vma->vm_mm);
120 page &= (PAGE_MASK << 1);
121 invtlb(INVTLB_ADDR_GFALSE_AND_ASID, newpid, page);
123 cpumask_clear_cpu(cpu, mm_cpumask(vma->vm_mm));
128 * This one is only used for pages with the global bit set so we don't care
129 * much about the ASID.
131 void local_flush_tlb_one(unsigned long page)
133 page &= (PAGE_MASK << 1);
134 invtlb_addr(INVTLB_ADDR_GTRUE_OR_ASID, 0, page);
137 static void __update_hugetlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
139 #ifdef CONFIG_HUGETLB_PAGE
144 local_irq_save(flags);
146 address &= (PAGE_MASK << 1);
147 write_csr_entryhi(address);
149 idx = read_csr_tlbidx();
150 write_csr_pagesize(PS_HUGE_SIZE);
151 lo = pmd_to_entrylo(pte_val(*ptep));
152 write_csr_entrylo0(lo);
153 write_csr_entrylo1(lo + (HPAGE_SIZE >> 1));
159 write_csr_pagesize(PS_DEFAULT_SIZE);
161 local_irq_restore(flags);
165 void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
171 * Handle debugger faulting in for debugee.
173 if (current->active_mm != vma->vm_mm)
176 if (pte_val(*ptep) & _PAGE_HUGE) {
177 __update_hugetlb(vma, address, ptep);
181 local_irq_save(flags);
183 if ((unsigned long)ptep & sizeof(pte_t))
186 address &= (PAGE_MASK << 1);
187 write_csr_entryhi(address);
189 idx = read_csr_tlbidx();
190 write_csr_pagesize(PS_DEFAULT_SIZE);
191 write_csr_entrylo0(pte_val(*ptep++));
192 write_csr_entrylo1(pte_val(*ptep));
198 local_irq_restore(flags);
201 static void setup_ptwalker(void)
203 unsigned long pwctl0, pwctl1;
204 unsigned long pgd_i = 0, pgd_w = 0;
205 unsigned long pud_i = 0, pud_w = 0;
206 unsigned long pmd_i = 0, pmd_w = 0;
207 unsigned long pte_i = 0, pte_w = 0;
210 pgd_w = PAGE_SHIFT - 3;
211 #if CONFIG_PGTABLE_LEVELS > 3
213 pud_w = PAGE_SHIFT - 3;
215 #if CONFIG_PGTABLE_LEVELS > 2
217 pmd_w = PAGE_SHIFT - 3;
220 pte_w = PAGE_SHIFT - 3;
222 pwctl0 = pte_i | pte_w << 5 | pmd_i << 10 | pmd_w << 15 | pud_i << 20 | pud_w << 25;
223 pwctl1 = pgd_i | pgd_w << 6;
225 csr_write64(pwctl0, LOONGARCH_CSR_PWCTL0);
226 csr_write64(pwctl1, LOONGARCH_CSR_PWCTL1);
227 csr_write64((long)swapper_pg_dir, LOONGARCH_CSR_PGDH);
228 csr_write64((long)invalid_pg_dir, LOONGARCH_CSR_PGDL);
229 csr_write64((long)smp_processor_id(), LOONGARCH_CSR_TMID);
232 static void output_pgtable_bits_defines(void)
234 #define pr_define(fmt, ...) \
235 pr_debug("#define " fmt, ##__VA_ARGS__)
237 pr_debug("#include <asm/asm.h>\n");
238 pr_debug("#include <asm/regdef.h>\n");
241 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
242 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
243 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
244 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
245 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
246 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
247 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
249 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
254 static unsigned long pcpu_handlers[NR_CPUS];
256 extern long exception_handlers[VECSIZE * 128 / sizeof(long)];
258 void setup_tlb_handler(int cpu)
261 local_flush_tlb_all();
263 /* The tlb handlers are generated only once */
265 memcpy((void *)tlbrentry, handle_tlb_refill, 0x80);
266 local_flush_icache_range(tlbrentry, tlbrentry + 0x80);
267 set_handler(EXCCODE_TLBI * VECSIZE, handle_tlb_load, VECSIZE);
268 set_handler(EXCCODE_TLBL * VECSIZE, handle_tlb_load, VECSIZE);
269 set_handler(EXCCODE_TLBS * VECSIZE, handle_tlb_store, VECSIZE);
270 set_handler(EXCCODE_TLBM * VECSIZE, handle_tlb_modify, VECSIZE);
271 set_handler(EXCCODE_TLBNR * VECSIZE, handle_tlb_protect, VECSIZE);
272 set_handler(EXCCODE_TLBNX * VECSIZE, handle_tlb_protect, VECSIZE);
273 set_handler(EXCCODE_TLBPE * VECSIZE, handle_tlb_protect, VECSIZE);
279 const int vec_sz = sizeof(exception_handlers);
281 if (pcpu_handlers[cpu])
284 page = alloc_pages_node(cpu_to_node(cpu), GFP_ATOMIC, get_order(vec_sz));
288 addr = page_address(page);
289 pcpu_handlers[cpu] = (unsigned long)addr;
290 memcpy((void *)addr, (void *)eentry, vec_sz);
291 local_flush_icache_range((unsigned long)addr, (unsigned long)addr + vec_sz);
292 csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_EENTRY);
293 csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_MERRENTRY);
294 csr_write64(pcpu_handlers[cpu] + 80*VECSIZE, LOONGARCH_CSR_TLBRENTRY);
299 void tlb_init(int cpu)
301 write_csr_pagesize(PS_DEFAULT_SIZE);
302 write_csr_stlbpgsize(PS_DEFAULT_SIZE);
303 write_csr_tlbrefill_pagesize(PS_DEFAULT_SIZE);
305 setup_tlb_handler(cpu);
306 output_pgtable_bits_defines();