1 // SPDX-License-Identifier: GPL-2.0
3 * Author: Huacai Chen <chenhuacai@loongson.cn>
4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 #include <linux/bitops.h>
8 #include <linux/compiler.h>
9 #include <linux/context_tracking.h>
10 #include <linux/entry-common.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/kexec.h>
14 #include <linux/module.h>
15 #include <linux/extable.h>
17 #include <linux/sched/mm.h>
18 #include <linux/sched/debug.h>
19 #include <linux/smp.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/memblock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ptrace.h>
25 #include <linux/kgdb.h>
26 #include <linux/kdebug.h>
27 #include <linux/kprobes.h>
28 #include <linux/notifier.h>
29 #include <linux/irq.h>
30 #include <linux/perf_event.h>
32 #include <asm/addrspace.h>
33 #include <asm/bootinfo.h>
34 #include <asm/branch.h>
35 #include <asm/break.h>
38 #include <asm/loongarch.h>
39 #include <asm/mmu_context.h>
40 #include <asm/pgtable.h>
41 #include <asm/ptrace.h>
42 #include <asm/sections.h>
43 #include <asm/siginfo.h>
44 #include <asm/stacktrace.h>
46 #include <asm/types.h>
47 #include <asm/unwind.h>
49 #include "access-helper.h"
51 extern asmlinkage void handle_ade(void);
52 extern asmlinkage void handle_ale(void);
53 extern asmlinkage void handle_sys(void);
54 extern asmlinkage void handle_bp(void);
55 extern asmlinkage void handle_ri(void);
56 extern asmlinkage void handle_fpu(void);
57 extern asmlinkage void handle_fpe(void);
58 extern asmlinkage void handle_lbt(void);
59 extern asmlinkage void handle_lsx(void);
60 extern asmlinkage void handle_lasx(void);
61 extern asmlinkage void handle_reserved(void);
62 extern asmlinkage void handle_watch(void);
63 extern asmlinkage void handle_vint(void);
65 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
66 const char *loglvl, bool user)
69 struct unwind_state state;
70 struct pt_regs *pregs = (struct pt_regs *)regs;
75 printk("%sCall Trace:", loglvl);
76 for (unwind_start(&state, task, pregs);
77 !unwind_done(&state); unwind_next_frame(&state)) {
78 addr = unwind_get_return_address(&state);
79 print_ip_sym(loglvl, addr);
81 printk("%s\n", loglvl);
84 static void show_stacktrace(struct task_struct *task,
85 const struct pt_regs *regs, const char *loglvl, bool user)
88 const int field = 2 * sizeof(unsigned long);
89 unsigned long stackdata;
90 unsigned long *sp = (unsigned long *)regs->regs[3];
92 printk("%sStack :", loglvl);
94 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
95 if (i && ((i % (64 / field)) == 0)) {
97 printk("%s ", loglvl);
104 if (__get_addr(&stackdata, sp++, user)) {
105 pr_cont(" (Bad stack address)");
109 pr_cont(" %0*lx", field, stackdata);
113 show_backtrace(task, regs, loglvl, user);
116 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
124 regs.regs[3] = (unsigned long)sp;
126 if (!task || task == current)
127 prepare_frametrace(®s);
129 regs.csr_era = task->thread.reg01;
131 regs.regs[3] = task->thread.reg03;
132 regs.regs[22] = task->thread.reg22;
136 show_stacktrace(task, ®s, loglvl, false);
139 static void show_code(unsigned int *pc, bool user)
146 for(i = -3 ; i < 6 ; i++) {
147 if (__get_inst(&insn, pc + i, user)) {
148 pr_cont(" (Bad address in era)\n");
151 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
156 static void __show_regs(const struct pt_regs *regs)
158 const int field = 2 * sizeof(unsigned long);
159 unsigned int excsubcode;
160 unsigned int exccode;
163 show_regs_print_info(KERN_DEFAULT);
166 * Saved main processor registers
168 for (i = 0; i < 32; ) {
171 pr_cont(" %0*lx", field, regs->regs[i]);
179 * Saved csr registers
181 printk("era : %0*lx %pS\n", field, regs->csr_era,
182 (void *) regs->csr_era);
183 printk("ra : %0*lx %pS\n", field, regs->regs[1],
184 (void *) regs->regs[1]);
186 printk("CSR crmd: %08lx ", regs->csr_crmd);
187 printk("CSR prmd: %08lx ", regs->csr_prmd);
188 printk("CSR euen: %08lx ", regs->csr_euen);
189 printk("CSR ecfg: %08lx ", regs->csr_ecfg);
190 printk("CSR estat: %08lx ", regs->csr_estat);
194 exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
195 excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
196 printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode);
198 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
199 printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
201 printk("PrId : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
202 cpu_family_string());
205 void show_regs(struct pt_regs *regs)
207 __show_regs((struct pt_regs *)regs);
211 void show_registers(struct pt_regs *regs)
215 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
216 current->comm, current->pid, current_thread_info(), current);
218 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
219 show_code((void *)regs->csr_era, user_mode(regs));
223 static DEFINE_RAW_SPINLOCK(die_lock);
225 void __noreturn die(const char *str, struct pt_regs *regs)
227 static int die_counter;
232 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
233 SIGSEGV) == NOTIFY_STOP)
237 raw_spin_lock_irq(&die_lock);
240 printk("%s[#%d]:\n", str, ++die_counter);
241 show_registers(regs);
242 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
243 raw_spin_unlock_irq(&die_lock);
247 if (regs && kexec_should_crash(current))
251 panic("Fatal exception in interrupt");
254 panic("Fatal exception");
259 static inline void setup_vint_size(unsigned int size)
265 if (vs == 0 || vs > 7)
266 panic("vint_size %d Not support yet", vs);
268 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG);
272 * Send SIGFPE according to FCSR Cause bits, which must have already
273 * been masked against Enable bits. This is impotant as Inexact can
274 * happen together with Overflow or Underflow, and `ptrace' can set
277 void force_fcsr_sig(unsigned long fcsr, void __user *fault_addr,
278 struct task_struct *tsk)
280 int si_code = FPE_FLTUNK;
282 if (fcsr & FPU_CSR_INV_X)
283 si_code = FPE_FLTINV;
284 else if (fcsr & FPU_CSR_DIV_X)
285 si_code = FPE_FLTDIV;
286 else if (fcsr & FPU_CSR_OVF_X)
287 si_code = FPE_FLTOVF;
288 else if (fcsr & FPU_CSR_UDF_X)
289 si_code = FPE_FLTUND;
290 else if (fcsr & FPU_CSR_INE_X)
291 si_code = FPE_FLTRES;
293 force_sig_fault(SIGFPE, si_code, fault_addr);
296 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr)
305 force_fcsr_sig(fcsr, fault_addr, current);
309 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
313 mmap_read_lock(current->mm);
314 if (vma_lookup(current->mm, (unsigned long)fault_addr))
315 si_code = SEGV_ACCERR;
317 si_code = SEGV_MAPERR;
318 mmap_read_unlock(current->mm);
319 force_sig_fault(SIGSEGV, si_code, fault_addr);
329 * Delayed fp exceptions when doing a lazy ctx switch
331 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr)
334 void __user *fault_addr;
335 irqentry_state_t state = irqentry_enter(regs);
337 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
338 SIGFPE) == NOTIFY_STOP)
341 /* Clear FCSR.Cause before enabling interrupts */
342 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr));
345 die_if_kernel("FP exception in kernel code", regs);
348 fault_addr = (void __user *) regs->csr_era;
350 /* Send a signal if required. */
351 process_fpemu_return(sig, fault_addr, fcsr);
355 irqentry_exit(regs, state);
358 asmlinkage void noinstr do_ade(struct pt_regs *regs)
360 irqentry_state_t state = irqentry_enter(regs);
362 die_if_kernel("Kernel ade access", regs);
363 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr);
365 irqentry_exit(regs, state);
369 int unaligned_enabled __read_mostly = 1; /* Enabled by default */
370 int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */
372 asmlinkage void noinstr do_ale(struct pt_regs *regs)
374 irqentry_state_t state = irqentry_enter(regs);
376 #ifndef CONFIG_ARCH_STRICT_ALIGN
377 die_if_kernel("Kernel ale access", regs);
378 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
382 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr);
385 * Did we catch a fault trying to load an instruction?
387 if (regs->csr_badvaddr == regs->csr_era)
389 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
391 if (!unaligned_enabled)
393 if (!no_unaligned_warning)
394 show_registers(regs);
396 pc = (unsigned int *)exception_era(regs);
398 emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc);
403 die_if_kernel("Kernel ale access", regs);
404 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
407 irqentry_exit(regs, state);
410 #ifdef CONFIG_GENERIC_BUG
411 int is_valid_bugaddr(unsigned long addr)
415 #endif /* CONFIG_GENERIC_BUG */
417 static void bug_handler(struct pt_regs *regs)
419 switch (report_bug(regs->csr_era, regs)) {
420 case BUG_TRAP_TYPE_BUG:
421 case BUG_TRAP_TYPE_NONE:
422 die_if_kernel("Oops - BUG", regs);
426 case BUG_TRAP_TYPE_WARN:
427 /* Skip the BUG instruction and continue */
428 regs->csr_era += LOONGARCH_INSN_SIZE;
433 asmlinkage void noinstr do_bp(struct pt_regs *regs)
435 bool user = user_mode(regs);
436 unsigned int opcode, bcode;
437 unsigned long era = exception_era(regs);
438 irqentry_state_t state = irqentry_enter(regs);
440 if (regs->csr_prmd & CSR_PRMD_PIE)
443 current->thread.trap_nr = read_csr_excode();
444 if (__get_inst(&opcode, (u32 *)era, user))
447 bcode = (opcode & 0x7fff);
450 * notify the kprobe handlers, if instruction is likely to
455 if (kprobe_breakpoint_handler(regs))
459 case BRK_KPROBE_SSTEPBP:
460 if (kprobe_singlestep_handler(regs))
465 if (notify_die(DIE_UPROBE, "Uprobe", regs, bcode,
466 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
470 case BRK_UPROBE_XOLBP:
471 if (notify_die(DIE_UPROBE_XOL, "Uprobe_XOL", regs, bcode,
472 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
477 if (notify_die(DIE_TRAP, "Break", regs, bcode,
478 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
489 die_if_kernel("Break instruction in kernel code", regs);
490 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era);
493 die_if_kernel("Break instruction in kernel code", regs);
494 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era);
497 die_if_kernel("Break instruction in kernel code", regs);
498 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era);
503 if (regs->csr_prmd & CSR_PRMD_PIE)
506 irqentry_exit(regs, state);
514 asmlinkage void noinstr do_watch(struct pt_regs *regs)
516 irqentry_state_t state = irqentry_enter(regs);
518 #ifndef CONFIG_HAVE_HW_BREAKPOINT
519 pr_warn("Hardware watch point handler not implemented!\n");
521 if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) {
522 int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1);
523 unsigned long pc = instruction_pointer(regs);
524 union loongarch_instruction *ip = (union loongarch_instruction *)pc;
528 * When the ll-sc combo is encountered, it is regarded as an single
529 * instruction. So don't clear llbit and reset CSR.FWPS.Skip until
530 * the llsc execution is completed.
532 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
533 csr_write32(CSR_LLBCTL_KLO, LOONGARCH_CSR_LLBCTL);
537 if (pc == current->thread.single_step) {
539 * Certain insns are occasionally not skipped when CSR.FWPS.Skip is
540 * set, such as fld.d/fst.d. So singlestep needs to compare whether
541 * the csr_era is equal to the value of singlestep which last time set.
543 if (!is_self_loop_ins(ip, regs)) {
545 * Check if the given instruction the target pc is equal to the
546 * current pc, If yes, then we should not set the CSR.FWPS.SKIP
547 * bit to break the original instruction stream.
549 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
554 breakpoint_handler(regs);
555 watchpoint_handler(regs);
561 irqentry_exit(regs, state);
564 asmlinkage void noinstr do_ri(struct pt_regs *regs)
567 unsigned int opcode = 0;
568 unsigned int __user *era = (unsigned int __user *)exception_era(regs);
569 irqentry_state_t state = irqentry_enter(regs);
572 current->thread.trap_nr = read_csr_excode();
574 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
575 SIGILL) == NOTIFY_STOP)
578 die_if_kernel("Reserved instruction in kernel code", regs);
580 if (unlikely(get_user(opcode, era) < 0)) {
582 current->thread.error_code = 1;
589 irqentry_exit(regs, state);
592 static void init_restore_fp(void)
595 /* First time FP context user. */
598 /* This task has formerly used the FP context */
603 BUG_ON(!is_fp_enabled());
606 asmlinkage void noinstr do_fpu(struct pt_regs *regs)
608 irqentry_state_t state = irqentry_enter(regs);
611 die_if_kernel("do_fpu invoked from kernel context!", regs);
618 irqentry_exit(regs, state);
621 asmlinkage void noinstr do_lsx(struct pt_regs *regs)
623 irqentry_state_t state = irqentry_enter(regs);
629 irqentry_exit(regs, state);
632 asmlinkage void noinstr do_lasx(struct pt_regs *regs)
634 irqentry_state_t state = irqentry_enter(regs);
640 irqentry_exit(regs, state);
643 asmlinkage void noinstr do_lbt(struct pt_regs *regs)
645 irqentry_state_t state = irqentry_enter(regs);
651 irqentry_exit(regs, state);
654 asmlinkage void noinstr do_reserved(struct pt_regs *regs)
656 irqentry_state_t state = irqentry_enter(regs);
660 * Game over - no way to handle this if it ever occurs. Most probably
661 * caused by a fatal error after another hardware/software error.
663 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n",
664 read_csr_excode(), current->pid, current->comm);
665 die_if_kernel("do_reserved exception", regs);
666 force_sig(SIGUNUSED);
670 irqentry_exit(regs, state);
673 asmlinkage void cache_parity_error(void)
675 /* For the moment, report the problem and hang. */
676 pr_err("Cache error exception:\n");
677 pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL));
678 pr_err("csr_merrera == %016llx\n", csr_read64(LOONGARCH_CSR_MERRERA));
679 panic("Can't handle the cache error!");
682 asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs)
684 struct pt_regs *old_regs;
687 old_regs = set_irq_regs(regs);
688 handle_arch_irq(regs);
689 set_irq_regs(old_regs);
693 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp)
696 register unsigned long stack;
697 irqentry_state_t state = irqentry_enter(regs);
699 cpu = smp_processor_id();
701 if (on_irq_stack(cpu, sp))
702 handle_loongarch_irq(regs);
704 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START;
706 /* Save task's sp on IRQ stack for unwinding */
707 *(unsigned long *)stack = sp;
709 __asm__ __volatile__(
710 "move $s0, $sp \n" /* Preserve sp */
711 "move $sp, %[stk] \n" /* Switch stack */
712 "move $a0, %[regs] \n"
713 "bl handle_loongarch_irq \n"
714 "move $sp, $s0 \n" /* Restore sp */
716 : [stk] "r" (stack), [regs] "r" (regs)
717 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0",
718 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8",
722 irqentry_exit(regs, state);
725 unsigned long eentry;
726 unsigned long tlbrentry;
728 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K);
730 static void configure_exception_vector(void)
732 eentry = (unsigned long)exception_handlers;
733 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE;
735 csr_write64(eentry, LOONGARCH_CSR_EENTRY);
736 csr_write64(eentry, LOONGARCH_CSR_MERRENTRY);
737 csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY);
740 void per_cpu_trap_init(int cpu)
744 setup_vint_size(VECSIZE);
746 configure_exception_vector();
748 if (!cpu_data[cpu].asid_cache)
749 cpu_data[cpu].asid_cache = asid_first_version(cpu);
752 current->active_mm = &init_mm;
754 enter_lazy_tlb(&init_mm, current);
756 /* Initialise exception handlers */
758 for (i = 0; i < 64; i++)
759 set_handler(i * VECSIZE, handle_reserved, VECSIZE);
765 /* Install CPU exception handler */
766 void set_handler(unsigned long offset, void *addr, unsigned long size)
768 memcpy((void *)(eentry + offset), addr, size);
769 local_flush_icache_range(eentry + offset, eentry + offset + size);
772 static const char panic_null_cerr[] =
773 "Trying to set NULL cache error exception handler\n";
776 * Install uncached CPU exception handler.
777 * This is suitable only for the cache error exception which is the only
778 * exception handler that is being run uncached.
780 void set_merr_handler(unsigned long offset, void *addr, unsigned long size)
782 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry));
785 panic(panic_null_cerr);
787 memcpy((void *)(uncached_eentry + offset), addr, size);
790 void __init trap_init(void)
794 /* Set interrupt vector handler */
795 for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++)
796 set_handler(i * VECSIZE, handle_vint, VECSIZE);
798 set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE);
799 set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE);
800 set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE);
801 set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE);
802 set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE);
803 set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE);
804 set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE);
805 set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE);
806 set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE);
807 set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE);
808 set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE);
809 set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE);
813 local_flush_icache_range(eentry, eentry + 0x400);