1 // SPDX-License-Identifier: GPL-2.0
3 * Author: Huacai Chen <chenhuacai@loongson.cn>
4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 #include <linux/bitops.h>
8 #include <linux/compiler.h>
9 #include <linux/context_tracking.h>
10 #include <linux/entry-common.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/extable.h>
16 #include <linux/sched/mm.h>
17 #include <linux/sched/debug.h>
18 #include <linux/smp.h>
19 #include <linux/spinlock.h>
20 #include <linux/kallsyms.h>
21 #include <linux/memblock.h>
22 #include <linux/interrupt.h>
23 #include <linux/ptrace.h>
24 #include <linux/kgdb.h>
25 #include <linux/kdebug.h>
26 #include <linux/kprobes.h>
27 #include <linux/notifier.h>
28 #include <linux/irq.h>
29 #include <linux/perf_event.h>
31 #include <asm/addrspace.h>
32 #include <asm/bootinfo.h>
33 #include <asm/branch.h>
34 #include <asm/break.h>
37 #include <asm/loongarch.h>
38 #include <asm/mmu_context.h>
39 #include <asm/pgtable.h>
40 #include <asm/ptrace.h>
41 #include <asm/sections.h>
42 #include <asm/siginfo.h>
43 #include <asm/stacktrace.h>
45 #include <asm/types.h>
47 #include "access-helper.h"
49 extern asmlinkage void handle_ade(void);
50 extern asmlinkage void handle_ale(void);
51 extern asmlinkage void handle_sys(void);
52 extern asmlinkage void handle_bp(void);
53 extern asmlinkage void handle_ri(void);
54 extern asmlinkage void handle_fpu(void);
55 extern asmlinkage void handle_fpe(void);
56 extern asmlinkage void handle_lbt(void);
57 extern asmlinkage void handle_lsx(void);
58 extern asmlinkage void handle_lasx(void);
59 extern asmlinkage void handle_reserved(void);
60 extern asmlinkage void handle_watch(void);
61 extern asmlinkage void handle_vint(void);
63 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
64 const char *loglvl, bool user)
67 unsigned long *sp = (unsigned long *)(regs->regs[3] & ~3);
69 printk("%sCall Trace:", loglvl);
70 #ifdef CONFIG_KALLSYMS
71 printk("%s\n", loglvl);
73 while (!kstack_end(sp)) {
74 if (__get_addr(&addr, sp++, user)) {
75 printk("%s (Bad stack address)", loglvl);
78 if (__kernel_text_address(addr))
79 print_ip_sym(loglvl, addr);
81 printk("%s\n", loglvl);
84 static void show_stacktrace(struct task_struct *task,
85 const struct pt_regs *regs, const char *loglvl, bool user)
88 const int field = 2 * sizeof(unsigned long);
89 unsigned long stackdata;
90 unsigned long *sp = (unsigned long *)regs->regs[3];
92 printk("%sStack :", loglvl);
94 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
95 if (i && ((i % (64 / field)) == 0)) {
97 printk("%s ", loglvl);
104 if (__get_addr(&stackdata, sp++, user)) {
105 pr_cont(" (Bad stack address)");
109 pr_cont(" %0*lx", field, stackdata);
113 show_backtrace(task, regs, loglvl, user);
116 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
124 regs.regs[3] = (unsigned long)sp;
126 if (!task || task == current)
127 prepare_frametrace(®s);
129 regs.csr_era = task->thread.reg01;
131 regs.regs[3] = task->thread.reg03;
132 regs.regs[22] = task->thread.reg22;
136 show_stacktrace(task, ®s, loglvl, false);
139 static void show_code(unsigned int *pc, bool user)
146 for(i = -3 ; i < 6 ; i++) {
147 if (__get_inst(&insn, pc + i, user)) {
148 pr_cont(" (Bad address in era)\n");
151 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
156 static void __show_regs(const struct pt_regs *regs)
158 const int field = 2 * sizeof(unsigned long);
159 unsigned int excsubcode;
160 unsigned int exccode;
163 show_regs_print_info(KERN_DEFAULT);
166 * Saved main processor registers
168 for (i = 0; i < 32; ) {
171 pr_cont(" %0*lx", field, regs->regs[i]);
179 * Saved csr registers
181 printk("era : %0*lx %pS\n", field, regs->csr_era,
182 (void *) regs->csr_era);
183 printk("ra : %0*lx %pS\n", field, regs->regs[1],
184 (void *) regs->regs[1]);
186 printk("CSR crmd: %08lx ", regs->csr_crmd);
187 printk("CSR prmd: %08lx ", regs->csr_prmd);
188 printk("CSR euen: %08lx ", regs->csr_euen);
189 printk("CSR ecfg: %08lx ", regs->csr_ecfg);
190 printk("CSR estat: %08lx ", regs->csr_estat);
194 exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
195 excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
196 printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode);
198 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
199 printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
201 printk("PrId : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
202 cpu_family_string());
205 void show_regs(struct pt_regs *regs)
207 __show_regs((struct pt_regs *)regs);
211 void show_registers(struct pt_regs *regs)
215 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
216 current->comm, current->pid, current_thread_info(), current);
218 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
219 show_code((void *)regs->csr_era, user_mode(regs));
223 static DEFINE_RAW_SPINLOCK(die_lock);
225 void __noreturn die(const char *str, struct pt_regs *regs)
227 static int die_counter;
232 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
233 SIGSEGV) == NOTIFY_STOP)
237 raw_spin_lock_irq(&die_lock);
240 printk("%s[#%d]:\n", str, ++die_counter);
241 show_registers(regs);
242 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
243 raw_spin_unlock_irq(&die_lock);
248 panic("Fatal exception in interrupt");
251 panic("Fatal exception");
256 static inline void setup_vint_size(unsigned int size)
262 if (vs == 0 || vs > 7)
263 panic("vint_size %d Not support yet", vs);
265 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG);
269 * Send SIGFPE according to FCSR Cause bits, which must have already
270 * been masked against Enable bits. This is impotant as Inexact can
271 * happen together with Overflow or Underflow, and `ptrace' can set
274 void force_fcsr_sig(unsigned long fcsr, void __user *fault_addr,
275 struct task_struct *tsk)
277 int si_code = FPE_FLTUNK;
279 if (fcsr & FPU_CSR_INV_X)
280 si_code = FPE_FLTINV;
281 else if (fcsr & FPU_CSR_DIV_X)
282 si_code = FPE_FLTDIV;
283 else if (fcsr & FPU_CSR_OVF_X)
284 si_code = FPE_FLTOVF;
285 else if (fcsr & FPU_CSR_UDF_X)
286 si_code = FPE_FLTUND;
287 else if (fcsr & FPU_CSR_INE_X)
288 si_code = FPE_FLTRES;
290 force_sig_fault(SIGFPE, si_code, fault_addr);
293 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr)
302 force_fcsr_sig(fcsr, fault_addr, current);
306 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
310 mmap_read_lock(current->mm);
311 if (vma_lookup(current->mm, (unsigned long)fault_addr))
312 si_code = SEGV_ACCERR;
314 si_code = SEGV_MAPERR;
315 mmap_read_unlock(current->mm);
316 force_sig_fault(SIGSEGV, si_code, fault_addr);
326 * Delayed fp exceptions when doing a lazy ctx switch
328 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr)
331 void __user *fault_addr;
332 irqentry_state_t state = irqentry_enter(regs);
334 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
335 SIGFPE) == NOTIFY_STOP)
338 /* Clear FCSR.Cause before enabling interrupts */
339 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr));
342 die_if_kernel("FP exception in kernel code", regs);
345 fault_addr = (void __user *) regs->csr_era;
347 /* Send a signal if required. */
348 process_fpemu_return(sig, fault_addr, fcsr);
352 irqentry_exit(regs, state);
355 asmlinkage void noinstr do_ade(struct pt_regs *regs)
357 irqentry_state_t state = irqentry_enter(regs);
359 die_if_kernel("Kernel ade access", regs);
360 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr);
362 irqentry_exit(regs, state);
365 asmlinkage void noinstr do_ale(struct pt_regs *regs)
367 irqentry_state_t state = irqentry_enter(regs);
369 die_if_kernel("Kernel ale access", regs);
370 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr);
372 irqentry_exit(regs, state);
375 asmlinkage void noinstr do_bp(struct pt_regs *regs)
377 bool user = user_mode(regs);
378 unsigned int opcode, bcode;
379 unsigned long era = exception_era(regs);
380 irqentry_state_t state = irqentry_enter(regs);
383 current->thread.trap_nr = read_csr_excode();
384 if (__get_inst(&opcode, (u32 *)era, user))
387 bcode = (opcode & 0x7fff);
390 * notify the kprobe handlers, if instruction is likely to
395 if (notify_die(DIE_BREAK, "Kprobe", regs, bcode,
396 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
400 case BRK_KPROBE_SSTEPBP:
401 if (notify_die(DIE_SSTEPBP, "Kprobe_SingleStep", regs, bcode,
402 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
407 if (notify_die(DIE_UPROBE, "Uprobe", regs, bcode,
408 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
412 case BRK_UPROBE_XOLBP:
413 if (notify_die(DIE_UPROBE_XOL, "Uprobe_XOL", regs, bcode,
414 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
419 if (notify_die(DIE_TRAP, "Break", regs, bcode,
420 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
428 die_if_kernel("Kernel bug detected", regs);
432 die_if_kernel("Break instruction in kernel code", regs);
433 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era);
436 die_if_kernel("Break instruction in kernel code", regs);
437 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era);
440 die_if_kernel("Break instruction in kernel code", regs);
441 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era);
447 irqentry_exit(regs, state);
455 asmlinkage void noinstr do_watch(struct pt_regs *regs)
457 pr_warn("Hardware watch point handler not implemented!\n");
460 asmlinkage void noinstr do_ri(struct pt_regs *regs)
463 unsigned int opcode = 0;
464 unsigned int __user *era = (unsigned int __user *)exception_era(regs);
465 unsigned long old_era = regs->csr_era;
466 unsigned long old_ra = regs->regs[1];
467 irqentry_state_t state = irqentry_enter(regs);
470 current->thread.trap_nr = read_csr_excode();
472 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
473 SIGILL) == NOTIFY_STOP)
476 die_if_kernel("Reserved instruction in kernel code", regs);
478 compute_return_era(regs);
480 if (unlikely(get_user(opcode, era) < 0)) {
482 current->thread.error_code = 1;
488 if (unlikely(status > 0)) {
489 regs->csr_era = old_era; /* Undo skip-over. */
490 regs->regs[1] = old_ra;
496 irqentry_exit(regs, state);
499 static void init_restore_fp(void)
502 /* First time FP context user. */
505 /* This task has formerly used the FP context */
510 BUG_ON(!is_fp_enabled());
513 asmlinkage void noinstr do_fpu(struct pt_regs *regs)
515 irqentry_state_t state = irqentry_enter(regs);
518 die_if_kernel("do_fpu invoked from kernel context!", regs);
525 irqentry_exit(regs, state);
528 asmlinkage void noinstr do_lsx(struct pt_regs *regs)
530 irqentry_state_t state = irqentry_enter(regs);
536 irqentry_exit(regs, state);
539 asmlinkage void noinstr do_lasx(struct pt_regs *regs)
541 irqentry_state_t state = irqentry_enter(regs);
547 irqentry_exit(regs, state);
550 asmlinkage void noinstr do_lbt(struct pt_regs *regs)
552 irqentry_state_t state = irqentry_enter(regs);
558 irqentry_exit(regs, state);
561 asmlinkage void noinstr do_reserved(struct pt_regs *regs)
563 irqentry_state_t state = irqentry_enter(regs);
567 * Game over - no way to handle this if it ever occurs. Most probably
568 * caused by a fatal error after another hardware/software error.
570 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n",
571 read_csr_excode(), current->pid, current->comm);
572 die_if_kernel("do_reserved exception", regs);
573 force_sig(SIGUNUSED);
577 irqentry_exit(regs, state);
580 asmlinkage void cache_parity_error(void)
582 /* For the moment, report the problem and hang. */
583 pr_err("Cache error exception:\n");
584 pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL));
585 pr_err("csr_merrera == %016llx\n", csr_read64(LOONGARCH_CSR_MERRERA));
586 panic("Can't handle the cache error!");
589 asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs)
591 struct pt_regs *old_regs;
594 old_regs = set_irq_regs(regs);
595 handle_arch_irq(regs);
596 set_irq_regs(old_regs);
600 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp)
603 register unsigned long stack;
604 irqentry_state_t state = irqentry_enter(regs);
606 cpu = smp_processor_id();
608 if (on_irq_stack(cpu, sp))
609 handle_loongarch_irq(regs);
611 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START;
613 /* Save task's sp on IRQ stack for unwinding */
614 *(unsigned long *)stack = sp;
616 __asm__ __volatile__(
617 "move $s0, $sp \n" /* Preserve sp */
618 "move $sp, %[stk] \n" /* Switch stack */
619 "move $a0, %[regs] \n"
620 "bl handle_loongarch_irq \n"
621 "move $sp, $s0 \n" /* Restore sp */
623 : [stk] "r" (stack), [regs] "r" (regs)
624 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0",
625 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8",
629 irqentry_exit(regs, state);
632 extern void tlb_init(int cpu);
633 extern void cache_error_setup(void);
635 unsigned long eentry;
636 unsigned long tlbrentry;
638 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K);
640 static void configure_exception_vector(void)
642 eentry = (unsigned long)exception_handlers;
643 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE;
645 csr_write64(eentry, LOONGARCH_CSR_EENTRY);
646 csr_write64(eentry, LOONGARCH_CSR_MERRENTRY);
647 csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY);
650 void per_cpu_trap_init(int cpu)
654 setup_vint_size(VECSIZE);
656 configure_exception_vector();
658 if (!cpu_data[cpu].asid_cache)
659 cpu_data[cpu].asid_cache = asid_first_version(cpu);
662 current->active_mm = &init_mm;
664 enter_lazy_tlb(&init_mm, current);
666 /* Initialise exception handlers */
668 for (i = 0; i < 64; i++)
669 set_handler(i * VECSIZE, handle_reserved, VECSIZE);
675 /* Install CPU exception handler */
676 void set_handler(unsigned long offset, void *addr, unsigned long size)
678 memcpy((void *)(eentry + offset), addr, size);
679 local_flush_icache_range(eentry + offset, eentry + offset + size);
682 static const char panic_null_cerr[] =
683 "Trying to set NULL cache error exception handler\n";
686 * Install uncached CPU exception handler.
687 * This is suitable only for the cache error exception which is the only
688 * exception handler that is being run uncached.
690 void set_merr_handler(unsigned long offset, void *addr, unsigned long size)
692 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry));
695 panic(panic_null_cerr);
697 memcpy((void *)(uncached_eentry + offset), addr, size);
700 void __init trap_init(void)
704 /* Set interrupt vector handler */
705 for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++)
706 set_handler(i * VECSIZE, handle_vint, VECSIZE);
708 set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE);
709 set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE);
710 set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE);
711 set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE);
712 set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE);
713 set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE);
714 set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE);
715 set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE);
716 set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE);
717 set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE);
718 set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE);
719 set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE);
723 local_flush_icache_range(eentry, eentry + 0x400);