arch/loongarch/kernel/time.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Common time service routines for LoongArch machines.
   4  *
   5  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   6  */
   7 #include <linux/clockchips.h>
   8 #include <linux/delay.h>
   9 #include <linux/export.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched_clock.h>
  14 #include <linux/spinlock.h>
  15
  16 #include <asm/cpu-features.h>
  17 #include <asm/loongarch.h>
  18 #include <asm/time.h>
  19
  20 u64 cpu_clock_freq;
  21 EXPORT_SYMBOL(cpu_clock_freq);
  22 u64 const_clock_freq;
  23 EXPORT_SYMBOL(const_clock_freq);
  24
  25 static DEFINE_RAW_SPINLOCK(state_lock);
  26 static DEFINE_PER_CPU(struct clock_event_device, constant_clockevent_device);
  27
  28 static void constant_event_handler(struct clock_event_device *dev)
  29 {
  30 }
  31
  32 irqreturn_t constant_timer_interrupt(int irq, void *data)
  33 {
  34         int cpu = smp_processor_id();
  35         struct clock_event_device *cd;
  36
  37         /* Clear Timer Interrupt */
  38         write_csr_tintclear(CSR_TINTCLR_TI);
  39         cd = &per_cpu(constant_clockevent_device, cpu);
  40         cd->event_handler(cd);
  41
  42         return IRQ_HANDLED;
  43 }
  44
  45 static int constant_set_state_oneshot(struct clock_event_device *evt)
  46 {
  47         unsigned long timer_config;
  48
  49         raw_spin_lock(&state_lock);
  50
  51         timer_config = csr_read64(LOONGARCH_CSR_TCFG);
  52         timer_config |= CSR_TCFG_EN;
  53         timer_config &= ~CSR_TCFG_PERIOD;
  54         csr_write64(timer_config, LOONGARCH_CSR_TCFG);
  55
  56         raw_spin_unlock(&state_lock);
  57
  58         return 0;
  59 }
  60
  61 static int constant_set_state_oneshot_stopped(struct clock_event_device *evt)
  62 {
  63         unsigned long timer_config;
  64
  65         raw_spin_lock(&state_lock);
  66
  67         timer_config = csr_read64(LOONGARCH_CSR_TCFG);
  68         timer_config &= ~CSR_TCFG_EN;
  69         csr_write64(timer_config, LOONGARCH_CSR_TCFG);
  70
  71         raw_spin_unlock(&state_lock);
  72
  73         return 0;
  74 }
  75
  76 static int constant_set_state_periodic(struct clock_event_device *evt)
  77 {
  78         unsigned long period;
  79         unsigned long timer_config;
  80
  81         raw_spin_lock(&state_lock);
  82
  83         period = const_clock_freq / HZ;
  84         timer_config = period & CSR_TCFG_VAL;
  85         timer_config |= (CSR_TCFG_PERIOD | CSR_TCFG_EN);
  86         csr_write64(timer_config, LOONGARCH_CSR_TCFG);
  87
  88         raw_spin_unlock(&state_lock);
  89
  90         return 0;
  91 }
  92
  93 static int constant_set_state_shutdown(struct clock_event_device *evt)
  94 {
  95         return 0;
  96 }
  97
  98 static int constant_timer_next_event(unsigned long delta, struct clock_event_device *evt)
  99 {
 100         unsigned long timer_config;
 101
 102         delta &= CSR_TCFG_VAL;
 103         timer_config = delta | CSR_TCFG_EN;
 104         csr_write64(timer_config, LOONGARCH_CSR_TCFG);
 105
 106         return 0;
 107 }
 108
 109 static unsigned long __init get_loops_per_jiffy(void)
 110 {
 111         unsigned long lpj = (unsigned long)const_clock_freq;
 112
 113         do_div(lpj, HZ);
 114
 115         return lpj;
 116 }
 117
 118 static long init_offset __nosavedata;
 119
 120 void save_counter(void)
 121 {
 122         init_offset = drdtime();
 123 }
 124
 125 void sync_counter(void)
 126 {
 127         /* Ensure counter begin at 0 */
 128         csr_write64(init_offset, LOONGARCH_CSR_CNTC);
 129 }
 130
 131 static int get_timer_irq(void)
 132 {
 133         struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
 134
 135         if (d)
 136                 return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
 137
 138         return -EINVAL;
 139 }
 140
 141 int constant_clockevent_init(void)
 142 {
 143         int irq;
 144         unsigned int cpu = smp_processor_id();
 145         unsigned long min_delta = 0x600;
 146         unsigned long max_delta = (1UL << 48) - 1;
 147         struct clock_event_device *cd;
 148         static int timer_irq_installed = 0;
 149
 150         irq = get_timer_irq();
 151         if (irq < 0)
 152                 pr_err("Failed to map irq %d (timer)\n", irq);
 153
 154         cd = &per_cpu(constant_clockevent_device, cpu);
 155
 156         cd->name = "Constant";
 157         cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_PERCPU;
 158
 159         cd->irq = irq;
 160         cd->rating = 320;
 161         cd->cpumask = cpumask_of(cpu);
 162         cd->set_state_oneshot = constant_set_state_oneshot;
 163         cd->set_state_oneshot_stopped = constant_set_state_oneshot_stopped;
 164         cd->set_state_periodic = constant_set_state_periodic;
 165         cd->set_state_shutdown = constant_set_state_shutdown;
 166         cd->set_next_event = constant_timer_next_event;
 167         cd->event_handler = constant_event_handler;
 168
 169         clockevents_config_and_register(cd, const_clock_freq, min_delta, max_delta);
 170
 171         if (timer_irq_installed)
 172                 return 0;
 173
 174         timer_irq_installed = 1;
 175
 176         sync_counter();
 177
 178         if (request_irq(irq, constant_timer_interrupt, IRQF_PERCPU | IRQF_TIMER, "timer", NULL))
 179                 pr_err("Failed to request irq %d (timer)\n", irq);
 180
 181         lpj_fine = get_loops_per_jiffy();
 182         pr_info("Constant clock event device register\n");
 183
 184         return 0;
 185 }
 186
 187 static u64 read_const_counter(struct clocksource *clk)
 188 {
 189         return drdtime();
 190 }
 191
 192 static u64 native_sched_clock(void)
 193 {
 194         return read_const_counter(NULL);
 195 }
 196
 197 static struct clocksource clocksource_const = {
 198         .name = "Constant",
 199         .rating = 400,
 200         .read = read_const_counter,
 201         .mask = CLOCKSOURCE_MASK(64),
 202         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 203         .vdso_clock_mode = VDSO_CLOCKMODE_CPU,
 204 };
 205
 206 int __init constant_clocksource_init(void)
 207 {
 208         int res;
 209         unsigned long freq = const_clock_freq;
 210
 211         res = clocksource_register_hz(&clocksource_const, freq);
 212
 213         sched_clock_register(native_sched_clock, 64, freq);
 214
 215         pr_info("Constant clock source device register\n");
 216
 217         return res;
 218 }
 219
 220 void __init time_init(void)
 221 {
 222         if (!cpu_has_cpucfg)
 223                 const_clock_freq = cpu_clock_freq;
 224         else
 225                 const_clock_freq = calc_const_freq();
 226
 227         init_offset = -(drdtime() - csr_read64(LOONGARCH_CSR_CNTC));
 228
 229         constant_clockevent_init();
 230         constant_clocksource_init();
 231 }