arch/loongarch/kernel/smp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   4  *
   5  * Derived from MIPS:
   6  * Copyright (C) 2000, 2001 Kanoj Sarcar
   7  * Copyright (C) 2000, 2001 Ralf Baechle
   8  * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
   9  * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
  10  */
  11 #include <linux/cpu.h>
  12 #include <linux/cpumask.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/smp.h>
  17 #include <linux/threads.h>
  18 #include <linux/export.h>
  19 #include <linux/time.h>
  20 #include <linux/tracepoint.h>
  21 #include <linux/sched/hotplug.h>
  22 #include <linux/sched/task_stack.h>
  23
  24 #include <asm/cpu.h>
  25 #include <asm/idle.h>
  26 #include <asm/loongson.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/numa.h>
  29 #include <asm/processor.h>
  30 #include <asm/setup.h>
  31 #include <asm/time.h>
  32
  33 int __cpu_number_map[NR_CPUS];   /* Map physical to logical */
  34 EXPORT_SYMBOL(__cpu_number_map);
  35
  36 int __cpu_logical_map[NR_CPUS];         /* Map logical to physical */
  37 EXPORT_SYMBOL(__cpu_logical_map);
  38
  39 /* Number of threads (siblings) per CPU core */
  40 int smp_num_siblings = 1;
  41 EXPORT_SYMBOL(smp_num_siblings);
  42
  43 /* Representing the threads (siblings) of each logical CPU */
  44 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
  45 EXPORT_SYMBOL(cpu_sibling_map);
  46
  47 /* Representing the core map of multi-core chips of each logical CPU */
  48 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
  49 EXPORT_SYMBOL(cpu_core_map);
  50
  51 static DECLARE_COMPLETION(cpu_starting);
  52 static DECLARE_COMPLETION(cpu_running);
  53
  54 /*
  55  * A logcal cpu mask containing only one VPE per core to
  56  * reduce the number of IPIs on large MT systems.
  57  */
  58 cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
  59 EXPORT_SYMBOL(cpu_foreign_map);
  60
  61 /* representing cpus for which sibling maps can be computed */
  62 static cpumask_t cpu_sibling_setup_map;
  63
  64 /* representing cpus for which core maps can be computed */
  65 static cpumask_t cpu_core_setup_map;
  66
  67 struct secondary_data cpuboot_data;
  68 static DEFINE_PER_CPU(int, cpu_state);
  69
  70 enum ipi_msg_type {
  71         IPI_RESCHEDULE,
  72         IPI_CALL_FUNCTION,
  73 };
  74
  75 static const char *ipi_types[NR_IPI] __tracepoint_string = {
  76         [IPI_RESCHEDULE] = "Rescheduling interrupts",
  77         [IPI_CALL_FUNCTION] = "Function call interrupts",
  78 };
  79
  80 void show_ipi_list(struct seq_file *p, int prec)
  81 {
  82         unsigned int cpu, i;
  83
  84         for (i = 0; i < NR_IPI; i++) {
  85                 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, prec >= 4 ? " " : "");
  86                 for_each_online_cpu(cpu)
  87                         seq_printf(p, "%10u ", per_cpu(irq_stat, cpu).ipi_irqs[i]);
  88                 seq_printf(p, " LoongArch  %d  %s\n", i + 1, ipi_types[i]);
  89         }
  90 }
  91
  92 /* Send mailbox buffer via Mail_Send */
  93 static void csr_mail_send(uint64_t data, int cpu, int mailbox)
  94 {
  95         uint64_t val;
  96
  97         /* Send high 32 bits */
  98         val = IOCSR_MBUF_SEND_BLOCKING;
  99         val |= (IOCSR_MBUF_SEND_BOX_HI(mailbox) << IOCSR_MBUF_SEND_BOX_SHIFT);
 100         val |= (cpu << IOCSR_MBUF_SEND_CPU_SHIFT);
 101         val |= (data & IOCSR_MBUF_SEND_H32_MASK);
 102         iocsr_write64(val, LOONGARCH_IOCSR_MBUF_SEND);
 103
 104         /* Send low 32 bits */
 105         val = IOCSR_MBUF_SEND_BLOCKING;
 106         val |= (IOCSR_MBUF_SEND_BOX_LO(mailbox) << IOCSR_MBUF_SEND_BOX_SHIFT);
 107         val |= (cpu << IOCSR_MBUF_SEND_CPU_SHIFT);
 108         val |= (data << IOCSR_MBUF_SEND_BUF_SHIFT);
 109         iocsr_write64(val, LOONGARCH_IOCSR_MBUF_SEND);
 110 };
 111
 112 static u32 ipi_read_clear(int cpu)
 113 {
 114         u32 action;
 115
 116         /* Load the ipi register to figure out what we're supposed to do */
 117         action = iocsr_read32(LOONGARCH_IOCSR_IPI_STATUS);
 118         /* Clear the ipi register to clear the interrupt */
 119         iocsr_write32(action, LOONGARCH_IOCSR_IPI_CLEAR);
 120         smp_mb();
 121
 122         return action;
 123 }
 124
 125 static void ipi_write_action(int cpu, u32 action)
 126 {
 127         unsigned int irq = 0;
 128
 129         while ((irq = ffs(action))) {
 130                 uint32_t val = IOCSR_IPI_SEND_BLOCKING;
 131
 132                 val |= (irq - 1);
 133                 val |= (cpu << IOCSR_IPI_SEND_CPU_SHIFT);
 134                 iocsr_write32(val, LOONGARCH_IOCSR_IPI_SEND);
 135                 action &= ~BIT(irq - 1);
 136         }
 137 }
 138
 139 void loongson3_send_ipi_single(int cpu, unsigned int action)
 140 {
 141         ipi_write_action(cpu_logical_map(cpu), (u32)action);
 142 }
 143
 144 void loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
 145 {
 146         unsigned int i;
 147
 148         for_each_cpu(i, mask)
 149                 ipi_write_action(cpu_logical_map(i), (u32)action);
 150 }
 151
 152 irqreturn_t loongson3_ipi_interrupt(int irq, void *dev)
 153 {
 154         unsigned int action;
 155         unsigned int cpu = smp_processor_id();
 156
 157         action = ipi_read_clear(cpu_logical_map(cpu));
 158
 159         if (action & SMP_RESCHEDULE) {
 160                 scheduler_ipi();
 161                 per_cpu(irq_stat, cpu).ipi_irqs[IPI_RESCHEDULE]++;
 162         }
 163
 164         if (action & SMP_CALL_FUNCTION) {
 165                 generic_smp_call_function_interrupt();
 166                 per_cpu(irq_stat, cpu).ipi_irqs[IPI_CALL_FUNCTION]++;
 167         }
 168
 169         return IRQ_HANDLED;
 170 }
 171
 172 void __init loongson3_smp_setup(void)
 173 {
 174         cpu_data[0].core = cpu_logical_map(0) % loongson_sysconf.cores_per_package;
 175         cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
 176
 177         iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
 178         pr_info("Detected %i available CPU(s)\n", loongson_sysconf.nr_cpus);
 179 }
 180
 181 void __init loongson3_prepare_cpus(unsigned int max_cpus)
 182 {
 183         int i = 0;
 184
 185         for (i = 0; i < loongson_sysconf.nr_cpus; i++) {
 186                 set_cpu_present(i, true);
 187                 csr_mail_send(0, __cpu_logical_map[i], 0);
 188         }
 189
 190         per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
 191 }
 192
 193 /*
 194  * Setup the PC, SP, and TP of a secondary processor and start it running!
 195  */
 196 void loongson3_boot_secondary(int cpu, struct task_struct *idle)
 197 {
 198         unsigned long entry;
 199
 200         pr_info("Booting CPU#%d...\n", cpu);
 201
 202         entry = __pa_symbol((unsigned long)&smpboot_entry);
 203         cpuboot_data.stack = (unsigned long)__KSTK_TOS(idle);
 204         cpuboot_data.thread_info = (unsigned long)task_thread_info(idle);
 205
 206         csr_mail_send(entry, cpu_logical_map(cpu), 0);
 207
 208         loongson3_send_ipi_single(cpu, SMP_BOOT_CPU);
 209 }
 210
 211 /*
 212  * SMP init and finish on secondary CPUs
 213  */
 214 void loongson3_init_secondary(void)
 215 {
 216         unsigned int cpu = smp_processor_id();
 217         unsigned int imask = ECFGF_IP0 | ECFGF_IP1 | ECFGF_IP2 |
 218                              ECFGF_IPI | ECFGF_PMC | ECFGF_TIMER;
 219
 220         change_csr_ecfg(ECFG0_IM, imask);
 221
 222         iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
 223
 224 #ifdef CONFIG_NUMA
 225         numa_add_cpu(cpu);
 226 #endif
 227         per_cpu(cpu_state, cpu) = CPU_ONLINE;
 228         cpu_data[cpu].core =
 229                      cpu_logical_map(cpu) % loongson_sysconf.cores_per_package;
 230         cpu_data[cpu].package =
 231                      cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
 232 }
 233
 234 void loongson3_smp_finish(void)
 235 {
 236         local_irq_enable();
 237         iocsr_write64(0, LOONGARCH_IOCSR_MBUF0);
 238         pr_info("CPU#%d finished\n", smp_processor_id());
 239 }
 240
 241 #ifdef CONFIG_HOTPLUG_CPU
 242
 243 static bool io_master(int cpu)
 244 {
 245         if (cpu == 0)
 246                 return true;
 247
 248         return false;
 249 }
 250
 251 int loongson3_cpu_disable(void)
 252 {
 253         unsigned long flags;
 254         unsigned int cpu = smp_processor_id();
 255
 256         if (io_master(cpu))
 257                 return -EBUSY;
 258
 259 #ifdef CONFIG_NUMA
 260         numa_remove_cpu(cpu);
 261 #endif
 262         set_cpu_online(cpu, false);
 263         calculate_cpu_foreign_map();
 264         local_irq_save(flags);
 265         irq_migrate_all_off_this_cpu();
 266         clear_csr_ecfg(ECFG0_IM);
 267         local_irq_restore(flags);
 268         local_flush_tlb_all();
 269
 270         return 0;
 271 }
 272
 273 void loongson3_cpu_die(unsigned int cpu)
 274 {
 275         while (per_cpu(cpu_state, cpu) != CPU_DEAD)
 276                 cpu_relax();
 277
 278         mb();
 279 }
 280
 281 void play_dead(void)
 282 {
 283         register uint64_t addr;
 284         register void (*init_fn)(void);
 285
 286         idle_task_exit();
 287         local_irq_enable();
 288         set_csr_ecfg(ECFGF_IPI);
 289         __this_cpu_write(cpu_state, CPU_DEAD);
 290
 291         __smp_mb();
 292         do {
 293                 __asm__ __volatile__("idle 0\n\t");
 294                 addr = iocsr_read64(LOONGARCH_IOCSR_MBUF0);
 295         } while (addr == 0);
 296
 297         init_fn = (void *)TO_CACHE(addr);
 298         iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_CLEAR);
 299
 300         init_fn();
 301         unreachable();
 302 }
 303
 304 #endif
 305
 306 /*
 307  * Power management
 308  */
 309 #ifdef CONFIG_PM
 310
 311 static int loongson3_ipi_suspend(void)
 312 {
 313         return 0;
 314 }
 315
 316 static void loongson3_ipi_resume(void)
 317 {
 318         iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
 319 }
 320
 321 static struct syscore_ops loongson3_ipi_syscore_ops = {
 322         .resume         = loongson3_ipi_resume,
 323         .suspend        = loongson3_ipi_suspend,
 324 };
 325
 326 /*
 327  * Enable boot cpu ipi before enabling nonboot cpus
 328  * during syscore_resume.
 329  */
 330 static int __init ipi_pm_init(void)
 331 {
 332         register_syscore_ops(&loongson3_ipi_syscore_ops);
 333         return 0;
 334 }
 335
 336 core_initcall(ipi_pm_init);
 337 #endif
 338
 339 static inline void set_cpu_sibling_map(int cpu)
 340 {
 341         int i;
 342
 343         cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
 344
 345         if (smp_num_siblings <= 1)
 346                 cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
 347         else {
 348                 for_each_cpu(i, &cpu_sibling_setup_map) {
 349                         if (cpus_are_siblings(cpu, i)) {
 350                                 cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
 351                                 cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
 352                         }
 353                 }
 354         }
 355 }
 356
 357 static inline void set_cpu_core_map(int cpu)
 358 {
 359         int i;
 360
 361         cpumask_set_cpu(cpu, &cpu_core_setup_map);
 362
 363         for_each_cpu(i, &cpu_core_setup_map) {
 364                 if (cpu_data[cpu].package == cpu_data[i].package) {
 365                         cpumask_set_cpu(i, &cpu_core_map[cpu]);
 366                         cpumask_set_cpu(cpu, &cpu_core_map[i]);
 367                 }
 368         }
 369 }
 370
 371 /*
 372  * Calculate a new cpu_foreign_map mask whenever a
 373  * new cpu appears or disappears.
 374  */
 375 void calculate_cpu_foreign_map(void)
 376 {
 377         int i, k, core_present;
 378         cpumask_t temp_foreign_map;
 379
 380         /* Re-calculate the mask */
 381         cpumask_clear(&temp_foreign_map);
 382         for_each_online_cpu(i) {
 383                 core_present = 0;
 384                 for_each_cpu(k, &temp_foreign_map)
 385                         if (cpus_are_siblings(i, k))
 386                                 core_present = 1;
 387                 if (!core_present)
 388                         cpumask_set_cpu(i, &temp_foreign_map);
 389         }
 390
 391         for_each_online_cpu(i)
 392                 cpumask_andnot(&cpu_foreign_map[i],
 393                                &temp_foreign_map, &cpu_sibling_map[i]);
 394 }
 395
 396 /* Preload SMP state for boot cpu */
 397 void smp_prepare_boot_cpu(void)
 398 {
 399         unsigned int cpu, node, rr_node;
 400
 401         set_cpu_possible(0, true);
 402         set_cpu_online(0, true);
 403         set_my_cpu_offset(per_cpu_offset(0));
 404
 405         rr_node = first_node(node_online_map);
 406         for_each_possible_cpu(cpu) {
 407                 node = early_cpu_to_node(cpu);
 408
 409                 /*
 410                  * The mapping between present cpus and nodes has been
 411                  * built during MADT and SRAT parsing.
 412                  *
 413                  * If possible cpus = present cpus here, early_cpu_to_node
 414                  * will return valid node.
 415                  *
 416                  * If possible cpus > present cpus here (e.g. some possible
 417                  * cpus will be added by cpu-hotplug later), for possible but
 418                  * not present cpus, early_cpu_to_node will return NUMA_NO_NODE,
 419                  * and we just map them to online nodes in round-robin way.
 420                  * Once hotplugged, new correct mapping will be built for them.
 421                  */
 422                 if (node != NUMA_NO_NODE)
 423                         set_cpu_numa_node(cpu, node);
 424                 else {
 425                         set_cpu_numa_node(cpu, rr_node);
 426                         rr_node = next_node_in(rr_node, node_online_map);
 427                 }
 428         }
 429 }
 430
 431 /* called from main before smp_init() */
 432 void __init smp_prepare_cpus(unsigned int max_cpus)
 433 {
 434         init_new_context(current, &init_mm);
 435         current_thread_info()->cpu = 0;
 436         loongson3_prepare_cpus(max_cpus);
 437         set_cpu_sibling_map(0);
 438         set_cpu_core_map(0);
 439         calculate_cpu_foreign_map();
 440 #ifndef CONFIG_HOTPLUG_CPU
 441         init_cpu_present(cpu_possible_mask);
 442 #endif
 443 }
 444
 445 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
 446 {
 447         loongson3_boot_secondary(cpu, tidle);
 448
 449         /* Wait for CPU to start and be ready to sync counters */
 450         if (!wait_for_completion_timeout(&cpu_starting,
 451                                          msecs_to_jiffies(5000))) {
 452                 pr_crit("CPU%u: failed to start\n", cpu);
 453                 return -EIO;
 454         }
 455
 456         /* Wait for CPU to finish startup & mark itself online before return */
 457         wait_for_completion(&cpu_running);
 458
 459         return 0;
 460 }
 461
 462 /*
 463  * First C code run on the secondary CPUs after being started up by
 464  * the master.
 465  */
 466 asmlinkage void start_secondary(void)
 467 {
 468         unsigned int cpu;
 469
 470         sync_counter();
 471         cpu = smp_processor_id();
 472         set_my_cpu_offset(per_cpu_offset(cpu));
 473
 474         cpu_probe();
 475         constant_clockevent_init();
 476         loongson3_init_secondary();
 477
 478         set_cpu_sibling_map(cpu);
 479         set_cpu_core_map(cpu);
 480
 481         notify_cpu_starting(cpu);
 482
 483         /* Notify boot CPU that we're starting */
 484         complete(&cpu_starting);
 485
 486         /* The CPU is running, now mark it online */
 487         set_cpu_online(cpu, true);
 488
 489         calculate_cpu_foreign_map();
 490
 491         /*
 492          * Notify boot CPU that we're up & online and it can safely return
 493          * from __cpu_up()
 494          */
 495         complete(&cpu_running);
 496
 497         /*
 498          * irq will be enabled in loongson3_smp_finish(), enabling it too
 499          * early is dangerous.
 500          */
 501         WARN_ON_ONCE(!irqs_disabled());
 502         loongson3_smp_finish();
 503
 504         cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
 505 }
 506
 507 void __init smp_cpus_done(unsigned int max_cpus)
 508 {
 509 }
 510
 511 static void stop_this_cpu(void *dummy)
 512 {
 513         set_cpu_online(smp_processor_id(), false);
 514         calculate_cpu_foreign_map();
 515         local_irq_disable();
 516         while (true);
 517 }
 518
 519 void smp_send_stop(void)
 520 {
 521         smp_call_function(stop_this_cpu, NULL, 0);
 522 }
 523
 524 int setup_profiling_timer(unsigned int multiplier)
 525 {
 526         return 0;
 527 }
 528
 529 static void flush_tlb_all_ipi(void *info)
 530 {
 531         local_flush_tlb_all();
 532 }
 533
 534 void flush_tlb_all(void)
 535 {
 536         on_each_cpu(flush_tlb_all_ipi, NULL, 1);
 537 }
 538
 539 static void flush_tlb_mm_ipi(void *mm)
 540 {
 541         local_flush_tlb_mm((struct mm_struct *)mm);
 542 }
 543
 544 void flush_tlb_mm(struct mm_struct *mm)
 545 {
 546         if (atomic_read(&mm->mm_users) == 0)
 547                 return;         /* happens as a result of exit_mmap() */
 548
 549         preempt_disable();
 550
 551         if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
 552                 on_each_cpu_mask(mm_cpumask(mm), flush_tlb_mm_ipi, mm, 1);
 553         } else {
 554                 unsigned int cpu;
 555
 556                 for_each_online_cpu(cpu) {
 557                         if (cpu != smp_processor_id() && cpu_context(cpu, mm))
 558                                 cpu_context(cpu, mm) = 0;
 559                 }
 560                 local_flush_tlb_mm(mm);
 561         }
 562
 563         preempt_enable();
 564 }
 565
 566 struct flush_tlb_data {
 567         struct vm_area_struct *vma;
 568         unsigned long addr1;
 569         unsigned long addr2;
 570 };
 571
 572 static void flush_tlb_range_ipi(void *info)
 573 {
 574         struct flush_tlb_data *fd = info;
 575
 576         local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
 577 }
 578
 579 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 580 {
 581         struct mm_struct *mm = vma->vm_mm;
 582
 583         preempt_disable();
 584         if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
 585                 struct flush_tlb_data fd = {
 586                         .vma = vma,
 587                         .addr1 = start,
 588                         .addr2 = end,
 589                 };
 590
 591                 on_each_cpu_mask(mm_cpumask(mm), flush_tlb_range_ipi, &fd, 1);
 592         } else {
 593                 unsigned int cpu;
 594
 595                 for_each_online_cpu(cpu) {
 596                         if (cpu != smp_processor_id() && cpu_context(cpu, mm))
 597                                 cpu_context(cpu, mm) = 0;
 598                 }
 599                 local_flush_tlb_range(vma, start, end);
 600         }
 601         preempt_enable();
 602 }
 603
 604 static void flush_tlb_kernel_range_ipi(void *info)
 605 {
 606         struct flush_tlb_data *fd = info;
 607
 608         local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
 609 }
 610
 611 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
 612 {
 613         struct flush_tlb_data fd = {
 614                 .addr1 = start,
 615                 .addr2 = end,
 616         };
 617
 618         on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
 619 }
 620
 621 static void flush_tlb_page_ipi(void *info)
 622 {
 623         struct flush_tlb_data *fd = info;
 624
 625         local_flush_tlb_page(fd->vma, fd->addr1);
 626 }
 627
 628 void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 629 {
 630         preempt_disable();
 631         if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
 632                 struct flush_tlb_data fd = {
 633                         .vma = vma,
 634                         .addr1 = page,
 635                 };
 636
 637                 on_each_cpu_mask(mm_cpumask(vma->vm_mm), flush_tlb_page_ipi, &fd, 1);
 638         } else {
 639                 unsigned int cpu;
 640
 641                 for_each_online_cpu(cpu) {
 642                         if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
 643                                 cpu_context(cpu, vma->vm_mm) = 0;
 644                 }
 645                 local_flush_tlb_page(vma, page);
 646         }
 647         preempt_enable();
 648 }
 649 EXPORT_SYMBOL(flush_tlb_page);
 650
 651 static void flush_tlb_one_ipi(void *info)
 652 {
 653         unsigned long vaddr = (unsigned long) info;
 654
 655         local_flush_tlb_one(vaddr);
 656 }
 657
 658 void flush_tlb_one(unsigned long vaddr)
 659 {
 660         on_each_cpu(flush_tlb_one_ipi, (void *)vaddr, 1);
 661 }
 662 EXPORT_SYMBOL(flush_tlb_one);