1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
5 #define pr_fmt(fmt) "hw-breakpoint: " fmt
7 #include <linux/hw_breakpoint.h>
8 #include <linux/kprobes.h>
9 #include <linux/perf_event.h>
11 #include <asm/hw_breakpoint.h>
13 /* Breakpoint currently in use for each BRP. */
14 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[LOONGARCH_MAX_BRP]);
16 /* Watchpoint currently in use for each WRP. */
17 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[LOONGARCH_MAX_WRP]);
19 int hw_breakpoint_slots(int type)
22 * We can be called early, so don't rely on
23 * our static variables being initialised.
27 return get_num_brps();
29 return get_num_wrps();
31 pr_warn("unknown slot type: %d\n", type);
36 #define READ_WB_REG_CASE(OFF, N, REG, T, VAL) \
38 LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL); \
41 #define WRITE_WB_REG_CASE(OFF, N, REG, T, VAL) \
43 LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL); \
46 #define GEN_READ_WB_REG_CASES(OFF, REG, T, VAL) \
47 READ_WB_REG_CASE(OFF, 0, REG, T, VAL); \
48 READ_WB_REG_CASE(OFF, 1, REG, T, VAL); \
49 READ_WB_REG_CASE(OFF, 2, REG, T, VAL); \
50 READ_WB_REG_CASE(OFF, 3, REG, T, VAL); \
51 READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
52 READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
53 READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
54 READ_WB_REG_CASE(OFF, 7, REG, T, VAL);
56 #define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \
57 WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL); \
58 WRITE_WB_REG_CASE(OFF, 1, REG, T, VAL); \
59 WRITE_WB_REG_CASE(OFF, 2, REG, T, VAL); \
60 WRITE_WB_REG_CASE(OFF, 3, REG, T, VAL); \
61 WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL); \
62 WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL); \
63 WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL); \
64 WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL);
66 static u64 read_wb_reg(int reg, int n, int t)
71 GEN_READ_WB_REG_CASES(CSR_CFG_ADDR, ADDR, t, val);
72 GEN_READ_WB_REG_CASES(CSR_CFG_MASK, MASK, t, val);
73 GEN_READ_WB_REG_CASES(CSR_CFG_CTRL, CTRL, t, val);
74 GEN_READ_WB_REG_CASES(CSR_CFG_ASID, ASID, t, val);
76 pr_warn("Attempt to read from unknown breakpoint register %d\n", n);
81 NOKPROBE_SYMBOL(read_wb_reg);
83 static void write_wb_reg(int reg, int n, int t, u64 val)
86 GEN_WRITE_WB_REG_CASES(CSR_CFG_ADDR, ADDR, t, val);
87 GEN_WRITE_WB_REG_CASES(CSR_CFG_MASK, MASK, t, val);
88 GEN_WRITE_WB_REG_CASES(CSR_CFG_CTRL, CTRL, t, val);
89 GEN_WRITE_WB_REG_CASES(CSR_CFG_ASID, ASID, t, val);
91 pr_warn("Attempt to write to unknown breakpoint register %d\n", n);
94 NOKPROBE_SYMBOL(write_wb_reg);
96 enum hw_breakpoint_ops {
97 HW_BREAKPOINT_INSTALL,
98 HW_BREAKPOINT_UNINSTALL,
102 * hw_breakpoint_slot_setup - Find and setup a perf slot according to operations
104 * @slots: pointer to array of slots
105 * @max_slots: max number of slots
106 * @bp: perf_event to setup
107 * @ops: operation to be carried out on the slot
110 * slot index on success
111 * -ENOSPC if no slot is available/matches
112 * -EINVAL on wrong operations parameter
115 static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots,
116 struct perf_event *bp, enum hw_breakpoint_ops ops)
119 struct perf_event **slot;
121 for (i = 0; i < max_slots; ++i) {
124 case HW_BREAKPOINT_INSTALL:
130 case HW_BREAKPOINT_UNINSTALL:
137 pr_warn_once("Unhandled hw breakpoint ops %d\n", ops);
145 void ptrace_hw_copy_thread(struct task_struct *tsk)
147 memset(tsk->thread.hbp_break, 0, sizeof(tsk->thread.hbp_break));
148 memset(tsk->thread.hbp_watch, 0, sizeof(tsk->thread.hbp_watch));
152 * Unregister breakpoints from this task and reset the pointers in the thread_struct.
154 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
157 struct thread_struct *t = &tsk->thread;
159 for (i = 0; i < LOONGARCH_MAX_BRP; i++) {
160 if (t->hbp_break[i]) {
161 unregister_hw_breakpoint(t->hbp_break[i]);
162 t->hbp_break[i] = NULL;
166 for (i = 0; i < LOONGARCH_MAX_WRP; i++) {
167 if (t->hbp_watch[i]) {
168 unregister_hw_breakpoint(t->hbp_watch[i]);
169 t->hbp_watch[i] = NULL;
174 static int hw_breakpoint_control(struct perf_event *bp,
175 enum hw_breakpoint_ops ops)
178 int i, max_slots, enable;
179 struct perf_event **slots;
180 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
182 if (info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) {
184 slots = this_cpu_ptr(bp_on_reg);
185 max_slots = boot_cpu_data.watch_ireg_count;
188 slots = this_cpu_ptr(wp_on_reg);
189 max_slots = boot_cpu_data.watch_dreg_count;
192 i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops);
194 if (WARN_ONCE(i < 0, "Can't find any breakpoint slot"))
198 case HW_BREAKPOINT_INSTALL:
199 /* Set the FWPnCFG/MWPnCFG 1~4 register. */
200 write_wb_reg(CSR_CFG_ADDR, i, 0, info->address);
201 write_wb_reg(CSR_CFG_ADDR, i, 1, info->address);
202 write_wb_reg(CSR_CFG_MASK, i, 0, info->mask);
203 write_wb_reg(CSR_CFG_MASK, i, 1, info->mask);
204 write_wb_reg(CSR_CFG_ASID, i, 0, 0);
205 write_wb_reg(CSR_CFG_ASID, i, 1, 0);
206 if (info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) {
207 write_wb_reg(CSR_CFG_CTRL, i, 0, CTRL_PLV_ENABLE);
209 ctrl = encode_ctrl_reg(info->ctrl);
210 write_wb_reg(CSR_CFG_CTRL, i, 1, ctrl | CTRL_PLV_ENABLE |
211 1 << MWPnCFG3_LoadEn | 1 << MWPnCFG3_StoreEn);
213 enable = csr_read64(LOONGARCH_CSR_CRMD);
214 csr_write64(CSR_CRMD_WE | enable, LOONGARCH_CSR_CRMD);
216 case HW_BREAKPOINT_UNINSTALL:
217 /* Reset the FWPnCFG/MWPnCFG 1~4 register. */
218 write_wb_reg(CSR_CFG_ADDR, i, 0, 0);
219 write_wb_reg(CSR_CFG_ADDR, i, 1, 0);
220 write_wb_reg(CSR_CFG_MASK, i, 0, 0);
221 write_wb_reg(CSR_CFG_MASK, i, 1, 0);
222 write_wb_reg(CSR_CFG_CTRL, i, 0, 0);
223 write_wb_reg(CSR_CFG_CTRL, i, 1, 0);
224 write_wb_reg(CSR_CFG_ASID, i, 0, 0);
225 write_wb_reg(CSR_CFG_ASID, i, 1, 0);
233 * Install a perf counter breakpoint.
235 int arch_install_hw_breakpoint(struct perf_event *bp)
237 return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL);
240 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
242 hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL);
245 static int get_hbp_len(u8 hbp_len)
247 unsigned int len_in_bytes = 0;
250 case LOONGARCH_BREAKPOINT_LEN_1:
253 case LOONGARCH_BREAKPOINT_LEN_2:
256 case LOONGARCH_BREAKPOINT_LEN_4:
259 case LOONGARCH_BREAKPOINT_LEN_8:
268 * Check whether bp virtual address is in kernel space.
270 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
276 len = get_hbp_len(hw->ctrl.len);
278 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
282 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
283 * Hopefully this will disappear when ptrace can bypass the conversion
284 * to generic breakpoint descriptions.
286 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
287 int *gen_len, int *gen_type, int *offset)
291 case LOONGARCH_BREAKPOINT_EXECUTE:
292 *gen_type = HW_BREAKPOINT_X;
294 case LOONGARCH_BREAKPOINT_LOAD:
295 *gen_type = HW_BREAKPOINT_R;
297 case LOONGARCH_BREAKPOINT_STORE:
298 *gen_type = HW_BREAKPOINT_W;
300 case LOONGARCH_BREAKPOINT_LOAD | LOONGARCH_BREAKPOINT_STORE:
301 *gen_type = HW_BREAKPOINT_RW;
310 *offset = __ffs(ctrl.len);
314 case LOONGARCH_BREAKPOINT_LEN_1:
315 *gen_len = HW_BREAKPOINT_LEN_1;
317 case LOONGARCH_BREAKPOINT_LEN_2:
318 *gen_len = HW_BREAKPOINT_LEN_2;
320 case LOONGARCH_BREAKPOINT_LEN_4:
321 *gen_len = HW_BREAKPOINT_LEN_4;
323 case LOONGARCH_BREAKPOINT_LEN_8:
324 *gen_len = HW_BREAKPOINT_LEN_8;
334 * Construct an arch_hw_breakpoint from a perf_event.
336 static int arch_build_bp_info(struct perf_event *bp,
337 const struct perf_event_attr *attr,
338 struct arch_hw_breakpoint *hw)
341 switch (attr->bp_type) {
342 case HW_BREAKPOINT_X:
343 hw->ctrl.type = LOONGARCH_BREAKPOINT_EXECUTE;
345 case HW_BREAKPOINT_R:
346 hw->ctrl.type = LOONGARCH_BREAKPOINT_LOAD;
348 case HW_BREAKPOINT_W:
349 hw->ctrl.type = LOONGARCH_BREAKPOINT_STORE;
351 case HW_BREAKPOINT_RW:
352 hw->ctrl.type = LOONGARCH_BREAKPOINT_LOAD | LOONGARCH_BREAKPOINT_STORE;
359 switch (attr->bp_len) {
360 case HW_BREAKPOINT_LEN_1:
361 hw->ctrl.len = LOONGARCH_BREAKPOINT_LEN_1;
363 case HW_BREAKPOINT_LEN_2:
364 hw->ctrl.len = LOONGARCH_BREAKPOINT_LEN_2;
366 case HW_BREAKPOINT_LEN_4:
367 hw->ctrl.len = LOONGARCH_BREAKPOINT_LEN_4;
369 case HW_BREAKPOINT_LEN_8:
370 hw->ctrl.len = LOONGARCH_BREAKPOINT_LEN_8;
377 hw->address = attr->bp_addr;
383 * Validate the arch-specific HW Breakpoint register settings.
385 int hw_breakpoint_arch_parse(struct perf_event *bp,
386 const struct perf_event_attr *attr,
387 struct arch_hw_breakpoint *hw)
390 u64 alignment_mask, offset;
392 /* Build the arch_hw_breakpoint. */
393 ret = arch_build_bp_info(bp, attr, hw);
397 if (hw->ctrl.type != LOONGARCH_BREAKPOINT_EXECUTE)
398 alignment_mask = 0x7;
399 offset = hw->address & alignment_mask;
401 hw->address &= ~alignment_mask;
402 hw->ctrl.len <<= offset;
407 static void update_bp_registers(struct pt_regs *regs, int enable, int type)
411 struct perf_event **slots;
412 struct arch_hw_breakpoint *info;
416 slots = this_cpu_ptr(bp_on_reg);
417 max_slots = boot_cpu_data.watch_ireg_count;
420 slots = this_cpu_ptr(wp_on_reg);
421 max_slots = boot_cpu_data.watch_dreg_count;
427 for (i = 0; i < max_slots; ++i) {
431 info = counter_arch_bp(slots[i]);
433 if ((info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) && (type == 0)) {
434 write_wb_reg(CSR_CFG_CTRL, i, 0, CTRL_PLV_ENABLE);
435 write_wb_reg(CSR_CFG_CTRL, i, 0, CTRL_PLV_ENABLE);
437 ctrl = read_wb_reg(CSR_CFG_CTRL, i, 1);
438 if (info->ctrl.type == LOONGARCH_BREAKPOINT_LOAD)
439 ctrl |= 0x1 << MWPnCFG3_LoadEn;
440 if (info->ctrl.type == LOONGARCH_BREAKPOINT_STORE)
441 ctrl |= 0x1 << MWPnCFG3_StoreEn;
442 write_wb_reg(CSR_CFG_CTRL, i, 1, ctrl);
444 regs->csr_prmd |= CSR_PRMD_PWE;
446 if ((info->ctrl.type == LOONGARCH_BREAKPOINT_EXECUTE) && (type == 0)) {
447 write_wb_reg(CSR_CFG_CTRL, i, 0, 0);
449 ctrl = read_wb_reg(CSR_CFG_CTRL, i, 1);
450 if (info->ctrl.type == LOONGARCH_BREAKPOINT_LOAD)
451 ctrl &= ~0x1 << MWPnCFG3_LoadEn;
452 if (info->ctrl.type == LOONGARCH_BREAKPOINT_STORE)
453 ctrl &= ~0x1 << MWPnCFG3_StoreEn;
454 write_wb_reg(CSR_CFG_CTRL, i, 1, ctrl);
456 regs->csr_prmd &= ~CSR_PRMD_PWE;
460 NOKPROBE_SYMBOL(update_bp_registers);
463 * Debug exception handlers.
465 void breakpoint_handler(struct pt_regs *regs)
468 struct perf_event *bp, **slots;
470 slots = this_cpu_ptr(bp_on_reg);
472 for (i = 0; i < boot_cpu_data.watch_ireg_count; ++i) {
476 perf_bp_event(bp, regs);
478 update_bp_registers(regs, 0, 0);
480 NOKPROBE_SYMBOL(breakpoint_handler);
482 void watchpoint_handler(struct pt_regs *regs)
485 struct perf_event *wp, **slots;
487 slots = this_cpu_ptr(wp_on_reg);
489 for (i = 0; i < boot_cpu_data.watch_dreg_count; ++i) {
493 perf_bp_event(wp, regs);
495 update_bp_registers(regs, 0, 1);
497 NOKPROBE_SYMBOL(watchpoint_handler);
499 static int __init arch_hw_breakpoint_init(void)
503 boot_cpu_data.watch_ireg_count = get_num_brps();
504 boot_cpu_data.watch_dreg_count = get_num_wrps();
506 pr_info("Found %d breakpoint and %d watchpoint registers.\n",
507 boot_cpu_data.watch_ireg_count, boot_cpu_data.watch_dreg_count);
509 for (cpu = 1; cpu < NR_CPUS; cpu++) {
510 cpu_data[cpu].watch_ireg_count = boot_cpu_data.watch_ireg_count;
511 cpu_data[cpu].watch_dreg_count = boot_cpu_data.watch_dreg_count;
516 arch_initcall(arch_hw_breakpoint_init);
518 void hw_breakpoint_thread_switch(struct task_struct *next)
521 struct pt_regs *regs = task_pt_regs(next);
523 if (test_tsk_thread_flag(next, TIF_SINGLESTEP)) {
524 addr = read_wb_reg(CSR_CFG_ADDR, 0, 0);
525 mask = read_wb_reg(CSR_CFG_MASK, 0, 0);
526 if (!((regs->csr_era ^ addr) & ~mask))
527 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS);
528 regs->csr_prmd |= CSR_PRMD_PWE;
530 /* Update breakpoints */
531 update_bp_registers(regs, 1, 0);
532 /* Update watchpoints */
533 update_bp_registers(regs, 1, 1);
537 void hw_breakpoint_pmu_read(struct perf_event *bp)
542 * Dummy function to register with die_notifier.
544 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
545 unsigned long val, void *data)