arch/loongarch/include/asm/inst.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
   4  */
   5 #ifndef _ASM_INST_H
   6 #define _ASM_INST_H
   7
   8 #include <linux/types.h>
   9 #include <asm/asm.h>
  10
  11 #define INSN_NOP                0x03400000
  12 #define INSN_BREAK              0x002a0000
  13
  14 #define ADDR_IMMMASK_LU52ID     0xFFF0000000000000
  15 #define ADDR_IMMMASK_LU32ID     0x000FFFFF00000000
  16 #define ADDR_IMMMASK_LU12IW     0x00000000FFFFF000
  17 #define ADDR_IMMMASK_ADDU16ID   0x00000000FFFF0000
  18
  19 #define ADDR_IMMSHIFT_LU52ID    52
  20 #define ADDR_IMMSHIFT_LU32ID    32
  21 #define ADDR_IMMSHIFT_LU12IW    12
  22 #define ADDR_IMMSHIFT_ADDU16ID  16
  23
  24 #define ADDR_IMM(addr, INSN)    ((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN)
  25
  26 enum reg0i26_op {
  27         b_op            = 0x14,
  28         bl_op           = 0x15,
  29 };
  30
  31 enum reg1i20_op {
  32         lu12iw_op       = 0x0a,
  33         lu32id_op       = 0x0b,
  34         pcaddi_op       = 0x0c,
  35         pcaddu12i_op    = 0x0e,
  36         pcaddu18i_op    = 0x0f,
  37 };
  38
  39 enum reg1i21_op {
  40         beqz_op         = 0x10,
  41         bnez_op         = 0x11,
  42         bceqz_op        = 0x12, /* bits[9:8] = 0x00 */
  43         bcnez_op        = 0x12, /* bits[9:8] = 0x01 */
  44 };
  45
  46 enum reg2_op {
  47         revb2h_op       = 0x0c,
  48         revb4h_op       = 0x0d,
  49         revb2w_op       = 0x0e,
  50         revbd_op        = 0x0f,
  51         revh2w_op       = 0x10,
  52         revhd_op        = 0x11,
  53 };
  54
  55 enum reg2i5_op {
  56         slliw_op        = 0x81,
  57         srliw_op        = 0x89,
  58         sraiw_op        = 0x91,
  59 };
  60
  61 enum reg2i6_op {
  62         sllid_op        = 0x41,
  63         srlid_op        = 0x45,
  64         sraid_op        = 0x49,
  65 };
  66
  67 enum reg2i12_op {
  68         addiw_op        = 0x0a,
  69         addid_op        = 0x0b,
  70         lu52id_op       = 0x0c,
  71         andi_op         = 0x0d,
  72         ori_op          = 0x0e,
  73         xori_op         = 0x0f,
  74         ldb_op          = 0xa0,
  75         ldh_op          = 0xa1,
  76         ldw_op          = 0xa2,
  77         ldd_op          = 0xa3,
  78         stb_op          = 0xa4,
  79         sth_op          = 0xa5,
  80         stw_op          = 0xa6,
  81         std_op          = 0xa7,
  82         ldbu_op         = 0xa8,
  83         ldhu_op         = 0xa9,
  84         ldwu_op         = 0xaa,
  85         flds_op         = 0xac,
  86         fsts_op         = 0xad,
  87         fldd_op         = 0xae,
  88         fstd_op         = 0xaf,
  89 };
  90
  91 enum reg2i14_op {
  92         llw_op          = 0x20,
  93         scw_op          = 0x21,
  94         lld_op          = 0x22,
  95         scd_op          = 0x23,
  96         ldptrw_op       = 0x24,
  97         stptrw_op       = 0x25,
  98         ldptrd_op       = 0x26,
  99         stptrd_op       = 0x27,
 100 };
 101
 102 enum reg2i16_op {
 103         jirl_op         = 0x13,
 104         beq_op          = 0x16,
 105         bne_op          = 0x17,
 106         blt_op          = 0x18,
 107         bge_op          = 0x19,
 108         bltu_op         = 0x1a,
 109         bgeu_op         = 0x1b,
 110 };
 111
 112 enum reg2bstrd_op {
 113         bstrinsd_op     = 0x2,
 114         bstrpickd_op    = 0x3,
 115 };
 116
 117 enum reg3_op {
 118         addw_op         = 0x20,
 119         addd_op         = 0x21,
 120         subw_op         = 0x22,
 121         subd_op         = 0x23,
 122         nor_op          = 0x28,
 123         and_op          = 0x29,
 124         or_op           = 0x2a,
 125         xor_op          = 0x2b,
 126         orn_op          = 0x2c,
 127         andn_op         = 0x2d,
 128         sllw_op         = 0x2e,
 129         srlw_op         = 0x2f,
 130         sraw_op         = 0x30,
 131         slld_op         = 0x31,
 132         srld_op         = 0x32,
 133         srad_op         = 0x33,
 134         mulw_op         = 0x38,
 135         mulhw_op        = 0x39,
 136         mulhwu_op       = 0x3a,
 137         muld_op         = 0x3b,
 138         mulhd_op        = 0x3c,
 139         mulhdu_op       = 0x3d,
 140         divw_op         = 0x40,
 141         modw_op         = 0x41,
 142         divwu_op        = 0x42,
 143         modwu_op        = 0x43,
 144         divd_op         = 0x44,
 145         modd_op         = 0x45,
 146         divdu_op        = 0x46,
 147         moddu_op        = 0x47,
 148         ldxb_op         = 0x7000,
 149         ldxh_op         = 0x7008,
 150         ldxw_op         = 0x7010,
 151         ldxd_op         = 0x7018,
 152         stxb_op         = 0x7020,
 153         stxh_op         = 0x7028,
 154         stxw_op         = 0x7030,
 155         stxd_op         = 0x7038,
 156         ldxbu_op        = 0x7040,
 157         ldxhu_op        = 0x7048,
 158         ldxwu_op        = 0x7050,
 159         fldxs_op        = 0x7060,
 160         fldxd_op        = 0x7068,
 161         fstxs_op        = 0x7070,
 162         fstxd_op        = 0x7078,
 163         amswapw_op      = 0x70c0,
 164         amswapd_op      = 0x70c1,
 165         amaddw_op       = 0x70c2,
 166         amaddd_op       = 0x70c3,
 167         amandw_op       = 0x70c4,
 168         amandd_op       = 0x70c5,
 169         amorw_op        = 0x70c6,
 170         amord_op        = 0x70c7,
 171         amxorw_op       = 0x70c8,
 172         amxord_op       = 0x70c9,
 173 };
 174
 175 enum reg3sa2_op {
 176         alslw_op        = 0x02,
 177         alslwu_op       = 0x03,
 178         alsld_op        = 0x16,
 179 };
 180
 181 struct reg0i26_format {
 182         unsigned int immediate_h : 10;
 183         unsigned int immediate_l : 16;
 184         unsigned int opcode : 6;
 185 };
 186
 187 struct reg1i20_format {
 188         unsigned int rd : 5;
 189         unsigned int immediate : 20;
 190         unsigned int opcode : 7;
 191 };
 192
 193 struct reg1i21_format {
 194         unsigned int immediate_h  : 5;
 195         unsigned int rj : 5;
 196         unsigned int immediate_l : 16;
 197         unsigned int opcode : 6;
 198 };
 199
 200 struct reg2_format {
 201         unsigned int rd : 5;
 202         unsigned int rj : 5;
 203         unsigned int opcode : 22;
 204 };
 205
 206 struct reg2i5_format {
 207         unsigned int rd : 5;
 208         unsigned int rj : 5;
 209         unsigned int immediate : 5;
 210         unsigned int opcode : 17;
 211 };
 212
 213 struct reg2i6_format {
 214         unsigned int rd : 5;
 215         unsigned int rj : 5;
 216         unsigned int immediate : 6;
 217         unsigned int opcode : 16;
 218 };
 219
 220 struct reg2i12_format {
 221         unsigned int rd : 5;
 222         unsigned int rj : 5;
 223         unsigned int immediate : 12;
 224         unsigned int opcode : 10;
 225 };
 226
 227 struct reg2i14_format {
 228         unsigned int rd : 5;
 229         unsigned int rj : 5;
 230         unsigned int immediate : 14;
 231         unsigned int opcode : 8;
 232 };
 233
 234 struct reg2i16_format {
 235         unsigned int rd : 5;
 236         unsigned int rj : 5;
 237         unsigned int immediate : 16;
 238         unsigned int opcode : 6;
 239 };
 240
 241 struct reg2bstrd_format {
 242         unsigned int rd : 5;
 243         unsigned int rj : 5;
 244         unsigned int lsbd : 6;
 245         unsigned int msbd : 6;
 246         unsigned int opcode : 10;
 247 };
 248
 249 struct reg3_format {
 250         unsigned int rd : 5;
 251         unsigned int rj : 5;
 252         unsigned int rk : 5;
 253         unsigned int opcode : 17;
 254 };
 255
 256 struct reg3sa2_format {
 257         unsigned int rd : 5;
 258         unsigned int rj : 5;
 259         unsigned int rk : 5;
 260         unsigned int immediate : 2;
 261         unsigned int opcode : 15;
 262 };
 263
 264 union loongarch_instruction {
 265         unsigned int word;
 266         struct reg0i26_format   reg0i26_format;
 267         struct reg1i20_format   reg1i20_format;
 268         struct reg1i21_format   reg1i21_format;
 269         struct reg2_format      reg2_format;
 270         struct reg2i5_format    reg2i5_format;
 271         struct reg2i6_format    reg2i6_format;
 272         struct reg2i12_format   reg2i12_format;
 273         struct reg2i14_format   reg2i14_format;
 274         struct reg2i16_format   reg2i16_format;
 275         struct reg2bstrd_format reg2bstrd_format;
 276         struct reg3_format      reg3_format;
 277         struct reg3sa2_format   reg3sa2_format;
 278 };
 279
 280 #define LOONGARCH_INSN_SIZE     sizeof(union loongarch_instruction)
 281
 282 enum loongarch_gpr {
 283         LOONGARCH_GPR_ZERO = 0,
 284         LOONGARCH_GPR_RA = 1,
 285         LOONGARCH_GPR_TP = 2,
 286         LOONGARCH_GPR_SP = 3,
 287         LOONGARCH_GPR_A0 = 4,   /* Reused as V0 for return value */
 288         LOONGARCH_GPR_A1,       /* Reused as V1 for return value */
 289         LOONGARCH_GPR_A2,
 290         LOONGARCH_GPR_A3,
 291         LOONGARCH_GPR_A4,
 292         LOONGARCH_GPR_A5,
 293         LOONGARCH_GPR_A6,
 294         LOONGARCH_GPR_A7,
 295         LOONGARCH_GPR_T0 = 12,
 296         LOONGARCH_GPR_T1,
 297         LOONGARCH_GPR_T2,
 298         LOONGARCH_GPR_T3,
 299         LOONGARCH_GPR_T4,
 300         LOONGARCH_GPR_T5,
 301         LOONGARCH_GPR_T6,
 302         LOONGARCH_GPR_T7,
 303         LOONGARCH_GPR_T8,
 304         LOONGARCH_GPR_FP = 22,
 305         LOONGARCH_GPR_S0 = 23,
 306         LOONGARCH_GPR_S1,
 307         LOONGARCH_GPR_S2,
 308         LOONGARCH_GPR_S3,
 309         LOONGARCH_GPR_S4,
 310         LOONGARCH_GPR_S5,
 311         LOONGARCH_GPR_S6,
 312         LOONGARCH_GPR_S7,
 313         LOONGARCH_GPR_S8,
 314         LOONGARCH_GPR_MAX
 315 };
 316
 317 #define is_imm12_negative(val)  is_imm_negative(val, 12)
 318
 319 static inline bool is_imm_negative(unsigned long val, unsigned int bit)
 320 {
 321         return val & (1UL << (bit - 1));
 322 }
 323
 324 static inline bool is_pc_ins(union loongarch_instruction *ip)
 325 {
 326         return ip->reg1i20_format.opcode >= pcaddi_op &&
 327                         ip->reg1i20_format.opcode <= pcaddu18i_op;
 328 }
 329
 330 static inline bool is_branch_ins(union loongarch_instruction *ip)
 331 {
 332         return ip->reg1i21_format.opcode >= beqz_op &&
 333                 ip->reg1i21_format.opcode <= bgeu_op;
 334 }
 335
 336 static inline bool is_ra_save_ins(union loongarch_instruction *ip)
 337 {
 338         /* st.d $ra, $sp, offset */
 339         return ip->reg2i12_format.opcode == std_op &&
 340                 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
 341                 ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&
 342                 !is_imm12_negative(ip->reg2i12_format.immediate);
 343 }
 344
 345 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip)
 346 {
 347         /* addi.d $sp, $sp, -imm */
 348         return ip->reg2i12_format.opcode == addid_op &&
 349                 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
 350                 ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&
 351                 is_imm12_negative(ip->reg2i12_format.immediate);
 352 }
 353
 354 int larch_insn_read(void *addr, u32 *insnp);
 355 int larch_insn_write(void *addr, u32 insn);
 356 int larch_insn_patch_text(void *addr, u32 insn);
 357
 358 u32 larch_insn_gen_nop(void);
 359 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);
 360 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest);
 361
 362 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);
 363 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
 364
 365 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
 366 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
 367 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
 368 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned long pc, unsigned long dest);
 369
 370 static inline bool signed_imm_check(long val, unsigned int bit)
 371 {
 372         return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1));
 373 }
 374
 375 static inline bool unsigned_imm_check(unsigned long val, unsigned int bit)
 376 {
 377         return val < (1UL << bit);
 378 }
 379
 380 static inline unsigned long sign_extend(unsigned long val, unsigned int idx)
 381 {
 382         if (!is_imm_negative(val, idx + 1))
 383                 return ((1UL << idx) - 1) & val;
 384         else
 385                 return ~((1UL << idx) - 1) | val;
 386 }
 387
 388 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP)                               \
 389 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 390                                int offset)                              \
 391 {                                                                       \
 392         unsigned int immediate_l, immediate_h;                          \
 393                                                                         \
 394         immediate_l = offset & 0xffff;                                  \
 395         offset >>= 16;                                                  \
 396         immediate_h = offset & 0x3ff;                                   \
 397                                                                         \
 398         insn->reg0i26_format.opcode = OP;                               \
 399         insn->reg0i26_format.immediate_l = immediate_l;                 \
 400         insn->reg0i26_format.immediate_h = immediate_h;                 \
 401 }
 402
 403 DEF_EMIT_REG0I26_FORMAT(b, b_op)
 404
 405 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP)                               \
 406 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 407                                enum loongarch_gpr rd, int imm)          \
 408 {                                                                       \
 409         insn->reg1i20_format.opcode = OP;                               \
 410         insn->reg1i20_format.immediate = imm;                           \
 411         insn->reg1i20_format.rd = rd;                                   \
 412 }
 413
 414 DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op)
 415 DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op)
 416 DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op)
 417
 418 #define DEF_EMIT_REG2_FORMAT(NAME, OP)                                  \
 419 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 420                                enum loongarch_gpr rd,                   \
 421                                enum loongarch_gpr rj)                   \
 422 {                                                                       \
 423         insn->reg2_format.opcode = OP;                                  \
 424         insn->reg2_format.rd = rd;                                      \
 425         insn->reg2_format.rj = rj;                                      \
 426 }
 427
 428 DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op)
 429 DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op)
 430 DEF_EMIT_REG2_FORMAT(revbd, revbd_op)
 431
 432 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP)                                \
 433 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 434                                enum loongarch_gpr rd,                   \
 435                                enum loongarch_gpr rj,                   \
 436                                int imm)                                 \
 437 {                                                                       \
 438         insn->reg2i5_format.opcode = OP;                                \
 439         insn->reg2i5_format.immediate = imm;                            \
 440         insn->reg2i5_format.rd = rd;                                    \
 441         insn->reg2i5_format.rj = rj;                                    \
 442 }
 443
 444 DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op)
 445 DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op)
 446 DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op)
 447
 448 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP)                                \
 449 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 450                                enum loongarch_gpr rd,                   \
 451                                enum loongarch_gpr rj,                   \
 452                                int imm)                                 \
 453 {                                                                       \
 454         insn->reg2i6_format.opcode = OP;                                \
 455         insn->reg2i6_format.immediate = imm;                            \
 456         insn->reg2i6_format.rd = rd;                                    \
 457         insn->reg2i6_format.rj = rj;                                    \
 458 }
 459
 460 DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op)
 461 DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op)
 462 DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op)
 463
 464 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP)                               \
 465 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 466                                enum loongarch_gpr rd,                   \
 467                                enum loongarch_gpr rj,                   \
 468                                int imm)                                 \
 469 {                                                                       \
 470         insn->reg2i12_format.opcode = OP;                               \
 471         insn->reg2i12_format.immediate = imm;                           \
 472         insn->reg2i12_format.rd = rd;                                   \
 473         insn->reg2i12_format.rj = rj;                                   \
 474 }
 475
 476 DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op)
 477 DEF_EMIT_REG2I12_FORMAT(addid, addid_op)
 478 DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op)
 479 DEF_EMIT_REG2I12_FORMAT(andi, andi_op)
 480 DEF_EMIT_REG2I12_FORMAT(ori, ori_op)
 481 DEF_EMIT_REG2I12_FORMAT(xori, xori_op)
 482 DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op)
 483 DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op)
 484 DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op)
 485 DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op)
 486 DEF_EMIT_REG2I12_FORMAT(stb, stb_op)
 487 DEF_EMIT_REG2I12_FORMAT(sth, sth_op)
 488 DEF_EMIT_REG2I12_FORMAT(stw, stw_op)
 489 DEF_EMIT_REG2I12_FORMAT(std, std_op)
 490
 491 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP)                               \
 492 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 493                                enum loongarch_gpr rd,                   \
 494                                enum loongarch_gpr rj,                   \
 495                                int imm)                                 \
 496 {                                                                       \
 497         insn->reg2i14_format.opcode = OP;                               \
 498         insn->reg2i14_format.immediate = imm;                           \
 499         insn->reg2i14_format.rd = rd;                                   \
 500         insn->reg2i14_format.rj = rj;                                   \
 501 }
 502
 503 DEF_EMIT_REG2I14_FORMAT(llw, llw_op)
 504 DEF_EMIT_REG2I14_FORMAT(scw, scw_op)
 505 DEF_EMIT_REG2I14_FORMAT(lld, lld_op)
 506 DEF_EMIT_REG2I14_FORMAT(scd, scd_op)
 507 DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op)
 508 DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op)
 509 DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op)
 510 DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op)
 511
 512 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP)                               \
 513 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 514                                enum loongarch_gpr rj,                   \
 515                                enum loongarch_gpr rd,                   \
 516                                int offset)                              \
 517 {                                                                       \
 518         insn->reg2i16_format.opcode = OP;                               \
 519         insn->reg2i16_format.immediate = offset;                        \
 520         insn->reg2i16_format.rj = rj;                                   \
 521         insn->reg2i16_format.rd = rd;                                   \
 522 }
 523
 524 DEF_EMIT_REG2I16_FORMAT(beq, beq_op)
 525 DEF_EMIT_REG2I16_FORMAT(bne, bne_op)
 526 DEF_EMIT_REG2I16_FORMAT(blt, blt_op)
 527 DEF_EMIT_REG2I16_FORMAT(bge, bge_op)
 528 DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op)
 529 DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op)
 530 DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op)
 531
 532 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP)                             \
 533 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 534                                enum loongarch_gpr rd,                   \
 535                                enum loongarch_gpr rj,                   \
 536                                int msbd,                                \
 537                                int lsbd)                                \
 538 {                                                                       \
 539         insn->reg2bstrd_format.opcode = OP;                             \
 540         insn->reg2bstrd_format.msbd = msbd;                             \
 541         insn->reg2bstrd_format.lsbd = lsbd;                             \
 542         insn->reg2bstrd_format.rj = rj;                                 \
 543         insn->reg2bstrd_format.rd = rd;                                 \
 544 }
 545
 546 DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op)
 547
 548 #define DEF_EMIT_REG3_FORMAT(NAME, OP)                                  \
 549 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 550                                enum loongarch_gpr rd,                   \
 551                                enum loongarch_gpr rj,                   \
 552                                enum loongarch_gpr rk)                   \
 553 {                                                                       \
 554         insn->reg3_format.opcode = OP;                                  \
 555         insn->reg3_format.rd = rd;                                      \
 556         insn->reg3_format.rj = rj;                                      \
 557         insn->reg3_format.rk = rk;                                      \
 558 }
 559
 560 DEF_EMIT_REG3_FORMAT(addd, addd_op)
 561 DEF_EMIT_REG3_FORMAT(subd, subd_op)
 562 DEF_EMIT_REG3_FORMAT(muld, muld_op)
 563 DEF_EMIT_REG3_FORMAT(divdu, divdu_op)
 564 DEF_EMIT_REG3_FORMAT(moddu, moddu_op)
 565 DEF_EMIT_REG3_FORMAT(and, and_op)
 566 DEF_EMIT_REG3_FORMAT(or, or_op)
 567 DEF_EMIT_REG3_FORMAT(xor, xor_op)
 568 DEF_EMIT_REG3_FORMAT(sllw, sllw_op)
 569 DEF_EMIT_REG3_FORMAT(slld, slld_op)
 570 DEF_EMIT_REG3_FORMAT(srlw, srlw_op)
 571 DEF_EMIT_REG3_FORMAT(srld, srld_op)
 572 DEF_EMIT_REG3_FORMAT(sraw, sraw_op)
 573 DEF_EMIT_REG3_FORMAT(srad, srad_op)
 574 DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op)
 575 DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op)
 576 DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op)
 577 DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op)
 578 DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
 579 DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
 580 DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
 581 DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
 582 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
 583 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
 584 DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
 585 DEF_EMIT_REG3_FORMAT(amandd, amandd_op)
 586 DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
 587 DEF_EMIT_REG3_FORMAT(amord, amord_op)
 588 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
 589 DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
 590 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
 591 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
 592
 593 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP)                               \
 594 static inline void emit_##NAME(union loongarch_instruction *insn,       \
 595                                enum loongarch_gpr rd,                   \
 596                                enum loongarch_gpr rj,                   \
 597                                enum loongarch_gpr rk,                   \
 598                                int imm)                                 \
 599 {                                                                       \
 600         insn->reg3sa2_format.opcode = OP;                               \
 601         insn->reg3sa2_format.immediate = imm;                           \
 602         insn->reg3sa2_format.rd = rd;                                   \
 603         insn->reg3sa2_format.rj = rj;                                   \
 604         insn->reg3sa2_format.rk = rk;                                   \
 605 }
 606
 607 DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op)
 608
 609 struct pt_regs;
 610
 611 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc);
 612 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign);
 613 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n);
 614
 615 #endif /* _ASM_INST_H */