1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
8 #include <linux/bitops.h>
9 #include <linux/types.h>
11 #include <asm/ptrace.h>
13 #define INSN_NOP 0x03400000
14 #define INSN_BREAK 0x002a0000
16 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
17 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
18 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000
19 #define ADDR_IMMMASK_ORI 0x0000000000000FFF
20 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
22 #define ADDR_IMMSHIFT_LU52ID 52
23 #define ADDR_IMMSBIDX_LU52ID 11
24 #define ADDR_IMMSHIFT_LU32ID 32
25 #define ADDR_IMMSBIDX_LU32ID 19
26 #define ADDR_IMMSHIFT_LU12IW 12
27 #define ADDR_IMMSBIDX_LU12IW 19
28 #define ADDR_IMMSHIFT_ORI 0
29 #define ADDR_IMMSBIDX_ORI 63
30 #define ADDR_IMMSHIFT_ADDU16ID 16
31 #define ADDR_IMMSBIDX_ADDU16ID 15
33 #define ADDR_IMM(addr, INSN) \
34 (sign_extend64(((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN), ADDR_IMMSBIDX_##INSN))
57 bceqz_op = 0x12, /* bits[9:8] = 0x00 */
58 bcnez_op = 0x12, /* bits[9:8] = 0x01 */
68 iocsrrdb_op = 0x19200,
69 iocsrrdh_op = 0x19201,
70 iocsrrdw_op = 0x19202,
71 iocsrrdd_op = 0x19203,
72 iocsrwrb_op = 0x19204,
73 iocsrwrh_op = 0x19205,
74 iocsrwrw_op = 0x19206,
75 iocsrwrd_op = 0x19207,
206 amswapdbw_op = 0x70d2,
207 amswapdbd_op = 0x70d3,
208 amadddbw_op = 0x70d4,
209 amadddbd_op = 0x70d5,
210 amanddbw_op = 0x70d6,
211 amanddbd_op = 0x70d7,
214 amxordbw_op = 0x70da,
215 amxordbd_op = 0x70db,
216 ammaxdbw_op = 0x70dc,
217 ammaxdbd_op = 0x70dd,
218 ammindbw_op = 0x70de,
219 ammindbd_op = 0x70df,
220 ammaxdbwu_op = 0x70e0,
221 ammaxdbdu_op = 0x70e1,
222 ammindbwu_op = 0x70e2,
223 ammindbdu_op = 0x70e3,
256 struct reg0i15_format {
257 unsigned int immediate : 15;
258 unsigned int opcode : 17;
261 struct reg0i26_format {
262 unsigned int immediate_h : 10;
263 unsigned int immediate_l : 16;
264 unsigned int opcode : 6;
267 struct reg1i20_format {
269 unsigned int immediate : 20;
270 unsigned int opcode : 7;
273 struct reg1i21_format {
274 unsigned int immediate_h : 5;
276 unsigned int immediate_l : 16;
277 unsigned int opcode : 6;
283 unsigned int opcode : 22;
286 struct reg2i5_format {
289 unsigned int immediate : 5;
290 unsigned int opcode : 17;
293 struct reg2i6_format {
296 unsigned int immediate : 6;
297 unsigned int opcode : 16;
300 struct reg2i12_format {
303 unsigned int immediate : 12;
304 unsigned int opcode : 10;
307 struct reg2i14_format {
310 unsigned int immediate : 14;
311 unsigned int opcode : 8;
314 struct reg2i16_format {
317 unsigned int immediate : 16;
318 unsigned int opcode : 6;
321 struct reg2bstrd_format {
324 unsigned int lsbd : 6;
325 unsigned int msbd : 6;
326 unsigned int opcode : 10;
329 struct reg2csr_format {
332 unsigned int csr : 14;
333 unsigned int opcode : 8;
340 unsigned int opcode : 17;
343 struct reg3sa2_format {
347 unsigned int immediate : 2;
348 unsigned int opcode : 15;
351 union loongarch_instruction {
353 struct reg0i15_format reg0i15_format;
354 struct reg0i26_format reg0i26_format;
355 struct reg1i20_format reg1i20_format;
356 struct reg1i21_format reg1i21_format;
357 struct reg2_format reg2_format;
358 struct reg2i5_format reg2i5_format;
359 struct reg2i6_format reg2i6_format;
360 struct reg2i12_format reg2i12_format;
361 struct reg2i14_format reg2i14_format;
362 struct reg2i16_format reg2i16_format;
363 struct reg2bstrd_format reg2bstrd_format;
364 struct reg2csr_format reg2csr_format;
365 struct reg3_format reg3_format;
366 struct reg3sa2_format reg3sa2_format;
369 #define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
372 LOONGARCH_GPR_ZERO = 0,
373 LOONGARCH_GPR_RA = 1,
374 LOONGARCH_GPR_TP = 2,
375 LOONGARCH_GPR_SP = 3,
376 LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
377 LOONGARCH_GPR_A1, /* Reused as V1 for return value */
384 LOONGARCH_GPR_T0 = 12,
393 LOONGARCH_GPR_FP = 22,
394 LOONGARCH_GPR_S0 = 23,
406 #define is_imm12_negative(val) is_imm_negative(val, 12)
408 static inline bool is_imm_negative(unsigned long val, unsigned int bit)
410 return val & (1UL << (bit - 1));
413 static inline bool is_break_ins(union loongarch_instruction *ip)
415 return ip->reg0i15_format.opcode == break_op;
418 static inline bool is_pc_ins(union loongarch_instruction *ip)
420 return ip->reg1i20_format.opcode >= pcaddi_op &&
421 ip->reg1i20_format.opcode <= pcaddu18i_op;
424 static inline bool is_branch_ins(union loongarch_instruction *ip)
426 return ip->reg1i21_format.opcode >= beqz_op &&
427 ip->reg1i21_format.opcode <= bgeu_op;
430 static inline bool is_ra_save_ins(union loongarch_instruction *ip)
432 /* st.d $ra, $sp, offset */
433 return ip->reg2i12_format.opcode == std_op &&
434 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
435 ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&
436 !is_imm12_negative(ip->reg2i12_format.immediate);
439 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip)
441 /* addi.d $sp, $sp, -imm */
442 return ip->reg2i12_format.opcode == addid_op &&
443 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
444 ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&
445 is_imm12_negative(ip->reg2i12_format.immediate);
448 static inline bool is_self_loop_ins(union loongarch_instruction *ip, struct pt_regs *regs)
450 switch (ip->reg0i26_format.opcode) {
453 if (ip->reg0i26_format.immediate_l == 0
454 && ip->reg0i26_format.immediate_h == 0)
458 switch (ip->reg1i21_format.opcode) {
462 if (ip->reg1i21_format.immediate_l == 0
463 && ip->reg1i21_format.immediate_h == 0)
467 switch (ip->reg2i16_format.opcode) {
474 if (ip->reg2i16_format.immediate == 0)
478 if (regs->regs[ip->reg2i16_format.rj] +
479 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip)
486 void simu_pc(struct pt_regs *regs, union loongarch_instruction insn);
487 void simu_branch(struct pt_regs *regs, union loongarch_instruction insn);
489 bool insns_not_supported(union loongarch_instruction insn);
490 bool insns_need_simulation(union loongarch_instruction insn);
491 void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs);
493 int larch_insn_read(void *addr, u32 *insnp);
494 int larch_insn_write(void *addr, u32 insn);
495 int larch_insn_patch_text(void *addr, u32 insn);
497 u32 larch_insn_gen_nop(void);
498 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);
499 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest);
501 u32 larch_insn_gen_break(int imm);
503 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);
504 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
506 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
507 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
508 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
509 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
511 static inline bool signed_imm_check(long val, unsigned int bit)
513 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1));
516 static inline bool unsigned_imm_check(unsigned long val, unsigned int bit)
518 return val < (1UL << bit);
521 #define DEF_EMIT_REG0I15_FORMAT(NAME, OP) \
522 static inline void emit_##NAME(union loongarch_instruction *insn, \
525 insn->reg0i15_format.opcode = OP; \
526 insn->reg0i15_format.immediate = imm; \
529 DEF_EMIT_REG0I15_FORMAT(break, break_op)
531 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \
532 static inline void emit_##NAME(union loongarch_instruction *insn, \
535 unsigned int immediate_l, immediate_h; \
537 immediate_l = offset & 0xffff; \
539 immediate_h = offset & 0x3ff; \
541 insn->reg0i26_format.opcode = OP; \
542 insn->reg0i26_format.immediate_l = immediate_l; \
543 insn->reg0i26_format.immediate_h = immediate_h; \
546 DEF_EMIT_REG0I26_FORMAT(b, b_op)
547 DEF_EMIT_REG0I26_FORMAT(bl, bl_op)
549 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \
550 static inline void emit_##NAME(union loongarch_instruction *insn, \
551 enum loongarch_gpr rd, int imm) \
553 insn->reg1i20_format.opcode = OP; \
554 insn->reg1i20_format.immediate = imm; \
555 insn->reg1i20_format.rd = rd; \
558 DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op)
559 DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op)
560 DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op)
562 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \
563 static inline void emit_##NAME(union loongarch_instruction *insn, \
564 enum loongarch_gpr rd, \
565 enum loongarch_gpr rj) \
567 insn->reg2_format.opcode = OP; \
568 insn->reg2_format.rd = rd; \
569 insn->reg2_format.rj = rj; \
572 DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op)
573 DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op)
574 DEF_EMIT_REG2_FORMAT(revbd, revbd_op)
576 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \
577 static inline void emit_##NAME(union loongarch_instruction *insn, \
578 enum loongarch_gpr rd, \
579 enum loongarch_gpr rj, \
582 insn->reg2i5_format.opcode = OP; \
583 insn->reg2i5_format.immediate = imm; \
584 insn->reg2i5_format.rd = rd; \
585 insn->reg2i5_format.rj = rj; \
588 DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op)
589 DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op)
590 DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op)
592 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \
593 static inline void emit_##NAME(union loongarch_instruction *insn, \
594 enum loongarch_gpr rd, \
595 enum loongarch_gpr rj, \
598 insn->reg2i6_format.opcode = OP; \
599 insn->reg2i6_format.immediate = imm; \
600 insn->reg2i6_format.rd = rd; \
601 insn->reg2i6_format.rj = rj; \
604 DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op)
605 DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op)
606 DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op)
608 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \
609 static inline void emit_##NAME(union loongarch_instruction *insn, \
610 enum loongarch_gpr rd, \
611 enum loongarch_gpr rj, \
614 insn->reg2i12_format.opcode = OP; \
615 insn->reg2i12_format.immediate = imm; \
616 insn->reg2i12_format.rd = rd; \
617 insn->reg2i12_format.rj = rj; \
620 DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op)
621 DEF_EMIT_REG2I12_FORMAT(addid, addid_op)
622 DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op)
623 DEF_EMIT_REG2I12_FORMAT(andi, andi_op)
624 DEF_EMIT_REG2I12_FORMAT(ori, ori_op)
625 DEF_EMIT_REG2I12_FORMAT(xori, xori_op)
626 DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op)
627 DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op)
628 DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op)
629 DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op)
630 DEF_EMIT_REG2I12_FORMAT(stb, stb_op)
631 DEF_EMIT_REG2I12_FORMAT(sth, sth_op)
632 DEF_EMIT_REG2I12_FORMAT(stw, stw_op)
633 DEF_EMIT_REG2I12_FORMAT(std, std_op)
635 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \
636 static inline void emit_##NAME(union loongarch_instruction *insn, \
637 enum loongarch_gpr rd, \
638 enum loongarch_gpr rj, \
641 insn->reg2i14_format.opcode = OP; \
642 insn->reg2i14_format.immediate = imm; \
643 insn->reg2i14_format.rd = rd; \
644 insn->reg2i14_format.rj = rj; \
647 DEF_EMIT_REG2I14_FORMAT(llw, llw_op)
648 DEF_EMIT_REG2I14_FORMAT(scw, scw_op)
649 DEF_EMIT_REG2I14_FORMAT(lld, lld_op)
650 DEF_EMIT_REG2I14_FORMAT(scd, scd_op)
651 DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op)
652 DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op)
653 DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op)
654 DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op)
656 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \
657 static inline void emit_##NAME(union loongarch_instruction *insn, \
658 enum loongarch_gpr rj, \
659 enum loongarch_gpr rd, \
662 insn->reg2i16_format.opcode = OP; \
663 insn->reg2i16_format.immediate = offset; \
664 insn->reg2i16_format.rj = rj; \
665 insn->reg2i16_format.rd = rd; \
668 DEF_EMIT_REG2I16_FORMAT(beq, beq_op)
669 DEF_EMIT_REG2I16_FORMAT(bne, bne_op)
670 DEF_EMIT_REG2I16_FORMAT(blt, blt_op)
671 DEF_EMIT_REG2I16_FORMAT(bge, bge_op)
672 DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op)
673 DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op)
674 DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op)
676 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \
677 static inline void emit_##NAME(union loongarch_instruction *insn, \
678 enum loongarch_gpr rd, \
679 enum loongarch_gpr rj, \
683 insn->reg2bstrd_format.opcode = OP; \
684 insn->reg2bstrd_format.msbd = msbd; \
685 insn->reg2bstrd_format.lsbd = lsbd; \
686 insn->reg2bstrd_format.rj = rj; \
687 insn->reg2bstrd_format.rd = rd; \
690 DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op)
692 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \
693 static inline void emit_##NAME(union loongarch_instruction *insn, \
694 enum loongarch_gpr rd, \
695 enum loongarch_gpr rj, \
696 enum loongarch_gpr rk) \
698 insn->reg3_format.opcode = OP; \
699 insn->reg3_format.rd = rd; \
700 insn->reg3_format.rj = rj; \
701 insn->reg3_format.rk = rk; \
704 DEF_EMIT_REG3_FORMAT(addd, addd_op)
705 DEF_EMIT_REG3_FORMAT(subd, subd_op)
706 DEF_EMIT_REG3_FORMAT(muld, muld_op)
707 DEF_EMIT_REG3_FORMAT(divdu, divdu_op)
708 DEF_EMIT_REG3_FORMAT(moddu, moddu_op)
709 DEF_EMIT_REG3_FORMAT(and, and_op)
710 DEF_EMIT_REG3_FORMAT(or, or_op)
711 DEF_EMIT_REG3_FORMAT(xor, xor_op)
712 DEF_EMIT_REG3_FORMAT(sllw, sllw_op)
713 DEF_EMIT_REG3_FORMAT(slld, slld_op)
714 DEF_EMIT_REG3_FORMAT(srlw, srlw_op)
715 DEF_EMIT_REG3_FORMAT(srld, srld_op)
716 DEF_EMIT_REG3_FORMAT(sraw, sraw_op)
717 DEF_EMIT_REG3_FORMAT(srad, srad_op)
718 DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op)
719 DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op)
720 DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op)
721 DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op)
722 DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
723 DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
724 DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
725 DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
726 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
727 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
728 DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
729 DEF_EMIT_REG3_FORMAT(amandd, amandd_op)
730 DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
731 DEF_EMIT_REG3_FORMAT(amord, amord_op)
732 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
733 DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
734 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
735 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
737 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \
738 static inline void emit_##NAME(union loongarch_instruction *insn, \
739 enum loongarch_gpr rd, \
740 enum loongarch_gpr rj, \
741 enum loongarch_gpr rk, \
744 insn->reg3sa2_format.opcode = OP; \
745 insn->reg3sa2_format.immediate = imm; \
746 insn->reg3sa2_format.rd = rd; \
747 insn->reg3sa2_format.rj = rj; \
748 insn->reg3sa2_format.rk = rk; \
751 DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op)
755 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc);
756 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign);
757 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n);
759 #endif /* _ASM_INST_H */