1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #ifndef __ASM_CSKY_ENTRY_H
5 #define __ASM_CSKY_ENTRY_H
8 #include <abi/regdef.h>
24 .macro SAVE_ALL epc_inc
56 #ifdef CONFIG_CPU_HAS_HILO
79 #ifdef CONFIG_CPU_HAS_HILO
104 .macro SAVE_REGS_FTRACE
126 #ifdef CONFIG_CPU_HAS_HILO
137 .macro RESTORE_REGS_FTRACE
140 #ifdef CONFIG_CPU_HAS_HILO
161 .macro SAVE_SWITCH_STACK
172 #ifdef CONFIG_CPU_HAS_HILO
183 .macro RESTORE_SWITCH_STACK
184 #ifdef CONFIG_CPU_HAS_HILO
205 /* MMU registers operators. */
235 /* Init psr and enable ee */
236 lrw r6, DEFAULT_PSR_VALUE
240 /* Invalid I/Dcache BTB BHT */
246 /* Invalid all TLB */
248 mtcr r6, cr<8, 15> /* Set MCIR */
250 /* Check MMU on/off */
255 /* MMU off: setup mapping tlb entry */
257 mtcr r6, cr<6, 15> /* Set MPR with 4K page size */
259 grs r6, 1f /* Get current pa by PC */
260 bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */
262 mtcr r6, cr<4, 15> /* Set MEH */
267 mtcr r8, cr<2, 15> /* Set MEL0 */
270 mtcr r8, cr<3, 15> /* Set MEL1 */
273 mtcr r8, cr<8, 15> /* Set MCIR to write TLB */
278 * MMU on: use origin MSA value from bootloader
280 * cr<30/31, 15> MSA register format:
281 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
282 * BA Reserved SH WA B SO SEC C D V
284 mfcr r6, cr<30, 15> /* Get MSA0 */
289 mtcr r6, cr<30, 15> /* Set MSA0 */
292 mtcr r6, cr<31, 15> /* Clr MSA1 */
299 jmpi 3f /* jump to va */
302 #endif /* __ASM_CSKY_ENTRY_H */