1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #ifndef __ASM_CSKY_ENTRY_H
5 #define __ASM_CSKY_ENTRY_H
8 #include <abi/regdef.h>
22 .macro SAVE_ALL epc_inc
48 #ifdef CONFIG_CPU_HAS_HILO
70 #ifdef CONFIG_CPU_HAS_HILO
92 .macro SAVE_SWITCH_STACK
103 #ifdef CONFIG_CPU_HAS_HILO
114 .macro RESTORE_SWITCH_STACK
115 #ifdef CONFIG_CPU_HAS_HILO
136 /* MMU registers operators. */
166 /* Init psr and enable ee */
167 lrw r6, DEFAULT_PSR_VALUE
171 /* Invalid I/Dcache BTB BHT */
177 /* Invalid all TLB */
179 mtcr r6, cr<8, 15> /* Set MCIR */
181 /* Check MMU on/off */
186 /* MMU off: setup mapping tlb entry */
188 mtcr r6, cr<6, 15> /* Set MPR with 4K page size */
190 grs r6, 1f /* Get current pa by PC */
191 bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */
193 mtcr r6, cr<4, 15> /* Set MEH */
198 mtcr r8, cr<2, 15> /* Set MEL0 */
201 mtcr r8, cr<3, 15> /* Set MEL1 */
204 mtcr r8, cr<8, 15> /* Set MCIR to write TLB */
209 * MMU on: use origin MSA value from bootloader
211 * cr<30/31, 15> MSA register format:
212 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
213 * BA Reserved SH WA B SO SEC C D V
215 mfcr r6, cr<30, 15> /* Get MSA0 */
220 mtcr r6, cr<30, 15> /* Set MSA0 */
226 mtcr r6, cr<31, 15> /* Set MSA1 */
233 jmpi 3f /* jump to va */
237 .macro ANDI_R3 rx, imm
239 andi \rx, (\imm >> 3)
241 #endif /* __ASM_CSKY_ENTRY_H */