arch/blackfin/mach-bf609/boards/ezkit.c

   1 /*
   2  * Copyright 2004-2009 Analog Devices Inc.
   3  *                2005 National ICT Australia (NICTA)
   4  *                      Aidan Williams <aidan@nicta.com.au>
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/mtd/mtd.h>
  12 #include <linux/mtd/partitions.h>
  13 #include <linux/mtd/physmap.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/spi/flash.h>
  16 #include <linux/irq.h>
  17 #include <linux/i2c.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/usb/musb.h>
  20 #include <linux/pinctrl/machine.h>
  21 #include <linux/pinctrl/pinconf-generic.h>
  22 #include <linux/platform_data/pinctrl-adi2.h>
  23 #include <linux/spi/adi_spi3.h>
  24 #include <asm/dma.h>
  25 #include <asm/gpio.h>
  26 #include <asm/nand.h>
  27 #include <asm/dpmc.h>
  28 #include <asm/portmux.h>
  29 #include <asm/bfin_sdh.h>
  30 #include <linux/input.h>
  31 #include <linux/spi/ad7877.h>
  32
  33 /*
  34  * Name the Board for the /proc/cpuinfo
  35  */
  36 const char bfin_board_name[] = "ADI BF609-EZKIT";
  37
  38 /*
  39  *  Driver needs to know address, irq and flag pin.
  40  */
  41
  42 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
  43 #include <linux/usb/isp1760.h>
  44 static struct resource bfin_isp1760_resources[] = {
  45         [0] = {
  46                 .start  = 0x2C0C0000,
  47                 .end    = 0x2C0C0000 + 0xfffff,
  48                 .flags  = IORESOURCE_MEM,
  49         },
  50         [1] = {
  51                 .start  = IRQ_PG7,
  52                 .end    = IRQ_PG7,
  53                 .flags  = IORESOURCE_IRQ,
  54         },
  55 };
  56
  57 static struct isp1760_platform_data isp1760_priv = {
  58         .is_isp1761 = 0,
  59         .bus_width_16 = 1,
  60         .port1_otg = 0,
  61         .analog_oc = 0,
  62         .dack_polarity_high = 0,
  63         .dreq_polarity_high = 0,
  64 };
  65
  66 static struct platform_device bfin_isp1760_device = {
  67         .name           = "isp1760",
  68         .id             = 0,
  69         .dev = {
  70                 .platform_data = &isp1760_priv,
  71         },
  72         .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
  73         .resource       = bfin_isp1760_resources,
  74 };
  75 #endif
  76
  77 #if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
  78 #include <linux/platform_data/bfin_rotary.h>
  79
  80 static struct bfin_rotary_platform_data bfin_rotary_data = {
  81         /*.rotary_up_key     = KEY_UP,*/
  82         /*.rotary_down_key   = KEY_DOWN,*/
  83         .rotary_rel_code   = REL_WHEEL,
  84         .rotary_button_key = KEY_ENTER,
  85         .debounce          = 10,        /* 0..17 */
  86         .mode              = ROT_QUAD_ENC | ROT_DEBE,
  87 };
  88
  89 static struct resource bfin_rotary_resources[] = {
  90         {
  91                 .start = CNT_CONFIG,
  92                 .end   = CNT_CONFIG + 0xff,
  93                 .flags = IORESOURCE_MEM,
  94         },
  95         {
  96                 .start = IRQ_CNT,
  97                 .end = IRQ_CNT,
  98                 .flags = IORESOURCE_IRQ,
  99         },
 100 };
 101
 102 static struct platform_device bfin_rotary_device = {
 103         .name           = "bfin-rotary",
 104         .id             = -1,
 105         .num_resources  = ARRAY_SIZE(bfin_rotary_resources),
 106         .resource       = bfin_rotary_resources,
 107         .dev            = {
 108                 .platform_data = &bfin_rotary_data,
 109         },
 110 };
 111 #endif
 112
 113 #if IS_ENABLED(CONFIG_STMMAC_ETH)
 114 #include <linux/stmmac.h>
 115 #include <linux/phy.h>
 116
 117 static struct stmmac_mdio_bus_data phy_private_data = {
 118         .phy_mask = 1,
 119 };
 120
 121 static struct stmmac_dma_cfg eth_dma_cfg = {
 122         .pbl    = 2,
 123 };
 124
 125 int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
 126 {
 127         bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
 128         return 0;
 129 }
 130
 131 static struct plat_stmmacenet_data eth_private_data = {
 132         .has_gmac = 1,
 133         .bus_id   = 0,
 134         .enh_desc = 1,
 135         .phy_addr = 1,
 136         .mdio_bus_data = &phy_private_data,
 137         .dma_cfg  = &eth_dma_cfg,
 138         .force_thresh_dma_mode = 1,
 139         .interface = PHY_INTERFACE_MODE_RMII,
 140         .init = stmmac_ptp_clk_init,
 141 };
 142
 143 static struct platform_device bfin_eth_device = {
 144         .name           = "stmmaceth",
 145         .id             = 0,
 146         .num_resources  = 2,
 147         .resource       = (struct resource[]) {
 148                 {
 149                         .start  = EMAC0_MACCFG,
 150                         .end    = EMAC0_MACCFG + 0x1274,
 151                         .flags  = IORESOURCE_MEM,
 152                 },
 153                 {
 154                         .name   = "macirq",
 155                         .start  = IRQ_EMAC0_STAT,
 156                         .end    = IRQ_EMAC0_STAT,
 157                         .flags  = IORESOURCE_IRQ,
 158                 },
 159         },
 160         .dev = {
 161                 .power.can_wakeup = 1,
 162                 .platform_data = &eth_private_data,
 163         }
 164 };
 165 #endif
 166
 167 #if IS_ENABLED(CONFIG_INPUT_ADXL34X)
 168 #include <linux/input/adxl34x.h>
 169 static const struct adxl34x_platform_data adxl34x_info = {
 170         .x_axis_offset = 0,
 171         .y_axis_offset = 0,
 172         .z_axis_offset = 0,
 173         .tap_threshold = 0x31,
 174         .tap_duration = 0x10,
 175         .tap_latency = 0x60,
 176         .tap_window = 0xF0,
 177         .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
 178         .act_axis_control = 0xFF,
 179         .activity_threshold = 5,
 180         .inactivity_threshold = 3,
 181         .inactivity_time = 4,
 182         .free_fall_threshold = 0x7,
 183         .free_fall_time = 0x20,
 184         .data_rate = 0x8,
 185         .data_range = ADXL_FULL_RES,
 186
 187         .ev_type = EV_ABS,
 188         .ev_code_x = ABS_X,             /* EV_REL */
 189         .ev_code_y = ABS_Y,             /* EV_REL */
 190         .ev_code_z = ABS_Z,             /* EV_REL */
 191
 192         .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
 193
 194 /*      .ev_code_ff = KEY_F,*/          /* EV_KEY */
 195 /*      .ev_code_act_inactivity = KEY_A,*/      /* EV_KEY */
 196         .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
 197         .fifo_mode = ADXL_FIFO_STREAM,
 198         .orientation_enable = ADXL_EN_ORIENTATION_3D,
 199         .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
 200         .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
 201         /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
 202         .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
 203 };
 204 #endif
 205
 206 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 207 static struct platform_device rtc_device = {
 208         .name = "rtc-bfin",
 209         .id   = -1,
 210 };
 211 #endif
 212
 213 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
 214 #ifdef CONFIG_SERIAL_BFIN_UART0
 215 static struct resource bfin_uart0_resources[] = {
 216         {
 217                 .start = UART0_REVID,
 218                 .end = UART0_RXDIV+4,
 219                 .flags = IORESOURCE_MEM,
 220         },
 221 #ifdef CONFIG_EARLY_PRINTK
 222         {
 223                 .start = PORTD_FER,
 224                 .end = PORTD_FER+2,
 225                 .flags = IORESOURCE_REG,
 226         },
 227         {
 228                 .start = PORTD_MUX,
 229                 .end = PORTD_MUX+3,
 230                 .flags = IORESOURCE_REG,
 231         },
 232 #endif
 233         {
 234                 .start = IRQ_UART0_TX,
 235                 .end = IRQ_UART0_TX,
 236                 .flags = IORESOURCE_IRQ,
 237         },
 238         {
 239                 .start = IRQ_UART0_RX,
 240                 .end = IRQ_UART0_RX,
 241                 .flags = IORESOURCE_IRQ,
 242         },
 243         {
 244                 .start = IRQ_UART0_STAT,
 245                 .end = IRQ_UART0_STAT,
 246                 .flags = IORESOURCE_IRQ,
 247         },
 248         {
 249                 .start = CH_UART0_TX,
 250                 .end = CH_UART0_TX,
 251                 .flags = IORESOURCE_DMA,
 252         },
 253         {
 254                 .start = CH_UART0_RX,
 255                 .end = CH_UART0_RX,
 256                 .flags = IORESOURCE_DMA,
 257         },
 258 #ifdef CONFIG_BFIN_UART0_CTSRTS
 259         {       /* CTS pin -- 0 means not supported */
 260                 .start = GPIO_PD10,
 261                 .end = GPIO_PD10,
 262                 .flags = IORESOURCE_IO,
 263         },
 264         {       /* RTS pin -- 0 means not supported */
 265                 .start = GPIO_PD9,
 266                 .end = GPIO_PD9,
 267                 .flags = IORESOURCE_IO,
 268         },
 269 #endif
 270 };
 271
 272 static unsigned short bfin_uart0_peripherals[] = {
 273         P_UART0_TX, P_UART0_RX,
 274 #ifdef CONFIG_BFIN_UART0_CTSRTS
 275         P_UART0_RTS, P_UART0_CTS,
 276 #endif
 277         0
 278 };
 279
 280 static struct platform_device bfin_uart0_device = {
 281         .name = "bfin-uart",
 282         .id = 0,
 283         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 284         .resource = bfin_uart0_resources,
 285         .dev = {
 286                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
 287         },
 288 };
 289 #endif
 290 #ifdef CONFIG_SERIAL_BFIN_UART1
 291 static struct resource bfin_uart1_resources[] = {
 292         {
 293                 .start = UART1_REVID,
 294                 .end = UART1_RXDIV+4,
 295                 .flags = IORESOURCE_MEM,
 296         },
 297 #ifdef CONFIG_EARLY_PRINTK
 298         {
 299                 .start = PORTG_FER_SET,
 300                 .end = PORTG_FER_SET+2,
 301                 .flags = IORESOURCE_REG,
 302         },
 303 #endif
 304         {
 305                 .start = IRQ_UART1_TX,
 306                 .end = IRQ_UART1_TX,
 307                 .flags = IORESOURCE_IRQ,
 308         },
 309         {
 310                 .start = IRQ_UART1_RX,
 311                 .end = IRQ_UART1_RX,
 312                 .flags = IORESOURCE_IRQ,
 313         },
 314         {
 315                 .start = IRQ_UART1_STAT,
 316                 .end = IRQ_UART1_STAT,
 317                 .flags = IORESOURCE_IRQ,
 318         },
 319         {
 320                 .start = CH_UART1_TX,
 321                 .end = CH_UART1_TX,
 322                 .flags = IORESOURCE_DMA,
 323         },
 324         {
 325                 .start = CH_UART1_RX,
 326                 .end = CH_UART1_RX,
 327                 .flags = IORESOURCE_DMA,
 328         },
 329 #ifdef CONFIG_BFIN_UART1_CTSRTS
 330         {       /* CTS pin -- 0 means not supported */
 331                 .start = GPIO_PG13,
 332                 .end = GPIO_PG13,
 333                 .flags = IORESOURCE_IO,
 334         },
 335         {       /* RTS pin -- 0 means not supported */
 336                 .start = GPIO_PG10,
 337                 .end = GPIO_PG10,
 338                 .flags = IORESOURCE_IO,
 339         },
 340 #endif
 341 };
 342
 343 static unsigned short bfin_uart1_peripherals[] = {
 344         P_UART1_TX, P_UART1_RX,
 345 #ifdef CONFIG_BFIN_UART1_CTSRTS
 346         P_UART1_RTS, P_UART1_CTS,
 347 #endif
 348         0
 349 };
 350
 351 static struct platform_device bfin_uart1_device = {
 352         .name = "bfin-uart",
 353         .id = 1,
 354         .num_resources = ARRAY_SIZE(bfin_uart1_resources),
 355         .resource = bfin_uart1_resources,
 356         .dev = {
 357                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
 358         },
 359 };
 360 #endif
 361 #endif
 362
 363 #if IS_ENABLED(CONFIG_BFIN_SIR)
 364 #ifdef CONFIG_BFIN_SIR0
 365 static struct resource bfin_sir0_resources[] = {
 366         {
 367                 .start = 0xFFC00400,
 368                 .end = 0xFFC004FF,
 369                 .flags = IORESOURCE_MEM,
 370         },
 371         {
 372                 .start = IRQ_UART0_TX,
 373                 .end = IRQ_UART0_TX+1,
 374                 .flags = IORESOURCE_IRQ,
 375         },
 376         {
 377                 .start = CH_UART0_TX,
 378                 .end = CH_UART0_TX+1,
 379                 .flags = IORESOURCE_DMA,
 380         },
 381 };
 382 static struct platform_device bfin_sir0_device = {
 383         .name = "bfin_sir",
 384         .id = 0,
 385         .num_resources = ARRAY_SIZE(bfin_sir0_resources),
 386         .resource = bfin_sir0_resources,
 387 };
 388 #endif
 389 #ifdef CONFIG_BFIN_SIR1
 390 static struct resource bfin_sir1_resources[] = {
 391         {
 392                 .start = 0xFFC02000,
 393                 .end = 0xFFC020FF,
 394                 .flags = IORESOURCE_MEM,
 395         },
 396         {
 397                 .start = IRQ_UART1_TX,
 398                 .end = IRQ_UART1_TX+1,
 399                 .flags = IORESOURCE_IRQ,
 400         },
 401         {
 402                 .start = CH_UART1_TX,
 403                 .end = CH_UART1_TX+1,
 404                 .flags = IORESOURCE_DMA,
 405         },
 406 };
 407 static struct platform_device bfin_sir1_device = {
 408         .name = "bfin_sir",
 409         .id = 1,
 410         .num_resources = ARRAY_SIZE(bfin_sir1_resources),
 411         .resource = bfin_sir1_resources,
 412 };
 413 #endif
 414 #endif
 415
 416 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 417 static struct resource musb_resources[] = {
 418         [0] = {
 419                 .start  = 0xFFCC1000,
 420                 .end    = 0xFFCC1398,
 421                 .flags  = IORESOURCE_MEM,
 422         },
 423         [1] = { /* general IRQ */
 424                 .start  = IRQ_USB_STAT,
 425                 .end    = IRQ_USB_STAT,
 426                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 427                 .name   = "mc"
 428         },
 429         [2] = { /* DMA IRQ */
 430                 .start  = IRQ_USB_DMA,
 431                 .end    = IRQ_USB_DMA,
 432                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 433                 .name   = "dma"
 434         },
 435 };
 436
 437 static struct musb_hdrc_config musb_config = {
 438         .multipoint     = 1,
 439         .dyn_fifo       = 0,
 440         .dma            = 1,
 441         .num_eps        = 16,
 442         .dma_channels   = 8,
 443         .clkin          = 48,           /* musb CLKIN in MHZ */
 444 };
 445
 446 static struct musb_hdrc_platform_data musb_plat = {
 447 #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
 448         .mode           = MUSB_OTG,
 449 #elif defined(CONFIG_USB_MUSB_HDRC)
 450         .mode           = MUSB_HOST,
 451 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
 452         .mode           = MUSB_PERIPHERAL,
 453 #endif
 454         .config         = &musb_config,
 455 };
 456
 457 static u64 musb_dmamask = ~(u32)0;
 458
 459 static struct platform_device musb_device = {
 460         .name           = "musb-blackfin",
 461         .id             = 0,
 462         .dev = {
 463                 .dma_mask               = &musb_dmamask,
 464                 .coherent_dma_mask      = 0xffffffff,
 465                 .platform_data          = &musb_plat,
 466         },
 467         .num_resources  = ARRAY_SIZE(musb_resources),
 468         .resource       = musb_resources,
 469 };
 470 #endif
 471
 472 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
 473 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 474 static struct resource bfin_sport0_uart_resources[] = {
 475         {
 476                 .start = SPORT0_TCR1,
 477                 .end = SPORT0_MRCS3+4,
 478                 .flags = IORESOURCE_MEM,
 479         },
 480         {
 481                 .start = IRQ_SPORT0_RX,
 482                 .end = IRQ_SPORT0_RX+1,
 483                 .flags = IORESOURCE_IRQ,
 484         },
 485         {
 486                 .start = IRQ_SPORT0_ERROR,
 487                 .end = IRQ_SPORT0_ERROR,
 488                 .flags = IORESOURCE_IRQ,
 489         },
 490 };
 491
 492 static unsigned short bfin_sport0_peripherals[] = {
 493         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
 494         P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 495 };
 496
 497 static struct platform_device bfin_sport0_uart_device = {
 498         .name = "bfin-sport-uart",
 499         .id = 0,
 500         .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
 501         .resource = bfin_sport0_uart_resources,
 502         .dev = {
 503                 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
 504         },
 505 };
 506 #endif
 507 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 508 static struct resource bfin_sport1_uart_resources[] = {
 509         {
 510                 .start = SPORT1_TCR1,
 511                 .end = SPORT1_MRCS3+4,
 512                 .flags = IORESOURCE_MEM,
 513         },
 514         {
 515                 .start = IRQ_SPORT1_RX,
 516                 .end = IRQ_SPORT1_RX+1,
 517                 .flags = IORESOURCE_IRQ,
 518         },
 519         {
 520                 .start = IRQ_SPORT1_ERROR,
 521                 .end = IRQ_SPORT1_ERROR,
 522                 .flags = IORESOURCE_IRQ,
 523         },
 524 };
 525
 526 static unsigned short bfin_sport1_peripherals[] = {
 527         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
 528         P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 529 };
 530
 531 static struct platform_device bfin_sport1_uart_device = {
 532         .name = "bfin-sport-uart",
 533         .id = 1,
 534         .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
 535         .resource = bfin_sport1_uart_resources,
 536         .dev = {
 537                 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
 538         },
 539 };
 540 #endif
 541 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
 542 static struct resource bfin_sport2_uart_resources[] = {
 543         {
 544                 .start = SPORT2_TCR1,
 545                 .end = SPORT2_MRCS3+4,
 546                 .flags = IORESOURCE_MEM,
 547         },
 548         {
 549                 .start = IRQ_SPORT2_RX,
 550                 .end = IRQ_SPORT2_RX+1,
 551                 .flags = IORESOURCE_IRQ,
 552         },
 553         {
 554                 .start = IRQ_SPORT2_ERROR,
 555                 .end = IRQ_SPORT2_ERROR,
 556                 .flags = IORESOURCE_IRQ,
 557         },
 558 };
 559
 560 static unsigned short bfin_sport2_peripherals[] = {
 561         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
 562         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 563 };
 564
 565 static struct platform_device bfin_sport2_uart_device = {
 566         .name = "bfin-sport-uart",
 567         .id = 2,
 568         .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
 569         .resource = bfin_sport2_uart_resources,
 570         .dev = {
 571                 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
 572         },
 573 };
 574 #endif
 575 #endif
 576
 577 #if IS_ENABLED(CONFIG_CAN_BFIN)
 578
 579 static unsigned short bfin_can0_peripherals[] = {
 580         P_CAN0_RX, P_CAN0_TX, 0
 581 };
 582
 583 static struct resource bfin_can0_resources[] = {
 584         {
 585                 .start = 0xFFC00A00,
 586                 .end = 0xFFC00FFF,
 587                 .flags = IORESOURCE_MEM,
 588         },
 589         {
 590                 .start = IRQ_CAN0_RX,
 591                 .end = IRQ_CAN0_RX,
 592                 .flags = IORESOURCE_IRQ,
 593         },
 594         {
 595                 .start = IRQ_CAN0_TX,
 596                 .end = IRQ_CAN0_TX,
 597                 .flags = IORESOURCE_IRQ,
 598         },
 599         {
 600                 .start = IRQ_CAN0_STAT,
 601                 .end = IRQ_CAN0_STAT,
 602                 .flags = IORESOURCE_IRQ,
 603         },
 604 };
 605
 606 static struct platform_device bfin_can0_device = {
 607         .name = "bfin_can",
 608         .id = 0,
 609         .num_resources = ARRAY_SIZE(bfin_can0_resources),
 610         .resource = bfin_can0_resources,
 611         .dev = {
 612                 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
 613         },
 614 };
 615
 616 #endif
 617
 618 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
 619 static struct mtd_partition partition_info[] = {
 620         {
 621                 .name = "bootloader(nand)",
 622                 .offset = 0,
 623                 .size = 0x80000,
 624         }, {
 625                 .name = "linux kernel(nand)",
 626                 .offset = MTDPART_OFS_APPEND,
 627                 .size = 4 * 1024 * 1024,
 628         },
 629         {
 630                 .name = "file system(nand)",
 631                 .offset = MTDPART_OFS_APPEND,
 632                 .size = MTDPART_SIZ_FULL,
 633         },
 634 };
 635
 636 static struct bf5xx_nand_platform bfin_nand_platform = {
 637         .data_width = NFC_NWIDTH_8,
 638         .partitions = partition_info,
 639         .nr_partitions = ARRAY_SIZE(partition_info),
 640         .rd_dly = 3,
 641         .wr_dly = 3,
 642 };
 643
 644 static struct resource bfin_nand_resources[] = {
 645         {
 646                 .start = 0xFFC03B00,
 647                 .end = 0xFFC03B4F,
 648                 .flags = IORESOURCE_MEM,
 649         },
 650         {
 651                 .start = CH_NFC,
 652                 .end = CH_NFC,
 653                 .flags = IORESOURCE_IRQ,
 654         },
 655 };
 656
 657 static struct platform_device bfin_nand_device = {
 658         .name = "bfin-nand",
 659         .id = 0,
 660         .num_resources = ARRAY_SIZE(bfin_nand_resources),
 661         .resource = bfin_nand_resources,
 662         .dev = {
 663                 .platform_data = &bfin_nand_platform,
 664         },
 665 };
 666 #endif
 667
 668 #if IS_ENABLED(CONFIG_SDH_BFIN)
 669
 670 static struct bfin_sd_host bfin_sdh_data = {
 671         .dma_chan = CH_RSI,
 672         .irq_int0 = IRQ_RSI_INT0,
 673         .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
 674 };
 675
 676 static struct platform_device bfin_sdh_device = {
 677         .name = "bfin-sdh",
 678         .id = 0,
 679         .dev = {
 680                 .platform_data = &bfin_sdh_data,
 681         },
 682 };
 683 #endif
 684
 685 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 686 static struct mtd_partition ezkit_partitions[] = {
 687         {
 688                 .name       = "bootloader(nor)",
 689                 .size       = 0x80000,
 690                 .offset     = 0,
 691         }, {
 692                 .name       = "linux kernel(nor)",
 693                 .size       = 0x400000,
 694                 .offset     = MTDPART_OFS_APPEND,
 695         }, {
 696                 .name       = "file system(nor)",
 697                 .size       = 0x1000000 - 0x80000 - 0x400000,
 698                 .offset     = MTDPART_OFS_APPEND,
 699         },
 700 };
 701
 702 int bf609_nor_flash_init(struct platform_device *pdev)
 703 {
 704 #define CONFIG_SMC_GCTL_VAL     0x00000010
 705
 706         bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
 707         bfin_write32(SMC_B0CTL, 0x01002011);
 708         bfin_write32(SMC_B0TIM, 0x08170977);
 709         bfin_write32(SMC_B0ETIM, 0x00092231);
 710         return 0;
 711 }
 712
 713 void bf609_nor_flash_exit(struct platform_device *pdev)
 714 {
 715         bfin_write32(SMC_GCTL, 0);
 716 }
 717
 718 static struct physmap_flash_data ezkit_flash_data = {
 719         .width      = 2,
 720         .parts      = ezkit_partitions,
 721         .init       = bf609_nor_flash_init,
 722         .exit       = bf609_nor_flash_exit,
 723         .nr_parts   = ARRAY_SIZE(ezkit_partitions),
 724 #ifdef CONFIG_ROMKERNEL
 725         .probe_type = "map_rom",
 726 #endif
 727 };
 728
 729 static struct resource ezkit_flash_resource = {
 730         .start = 0xb0000000,
 731         .end   = 0xb0ffffff,
 732         .flags = IORESOURCE_MEM,
 733 };
 734
 735 static struct platform_device ezkit_flash_device = {
 736         .name          = "physmap-flash",
 737         .id            = 0,
 738         .dev = {
 739                 .platform_data = &ezkit_flash_data,
 740         },
 741         .num_resources = 1,
 742         .resource      = &ezkit_flash_resource,
 743 };
 744 #endif
 745
 746 #if IS_ENABLED(CONFIG_MTD_M25P80)
 747 /* SPI flash chip (w25q32) */
 748 static struct mtd_partition bfin_spi_flash_partitions[] = {
 749         {
 750                 .name = "bootloader(spi)",
 751                 .size = 0x00080000,
 752                 .offset = 0,
 753                 .mask_flags = MTD_CAP_ROM
 754         }, {
 755                 .name = "linux kernel(spi)",
 756                 .size = 0x00180000,
 757                 .offset = MTDPART_OFS_APPEND,
 758         }, {
 759                 .name = "file system(spi)",
 760                 .size = MTDPART_SIZ_FULL,
 761                 .offset = MTDPART_OFS_APPEND,
 762         }
 763 };
 764
 765 static struct flash_platform_data bfin_spi_flash_data = {
 766         .name = "m25p80",
 767         .parts = bfin_spi_flash_partitions,
 768         .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
 769         .type = "w25q32",
 770 };
 771
 772 static struct adi_spi3_chip spi_flash_chip_info = {
 773         .enable_dma = true,         /* use dma transfer with this chip*/
 774 };
 775 #endif
 776
 777 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
 778 static struct adi_spi3_chip spidev_chip_info = {
 779         .enable_dma = true,
 780 };
 781 #endif
 782
 783 #if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
 784 static struct platform_device bfin_pcm = {
 785         .name = "bfin-i2s-pcm-audio",
 786         .id = -1,
 787 };
 788 #endif
 789
 790 #if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
 791 #include <asm/bfin_sport3.h>
 792 static struct resource bfin_snd_resources[] = {
 793         {
 794                 .start = SPORT0_CTL_A,
 795                 .end = SPORT0_CTL_A,
 796                 .flags = IORESOURCE_MEM,
 797         },
 798         {
 799                 .start = SPORT0_CTL_B,
 800                 .end = SPORT0_CTL_B,
 801                 .flags = IORESOURCE_MEM,
 802         },
 803         {
 804                 .start = CH_SPORT0_TX,
 805                 .end = CH_SPORT0_TX,
 806                 .flags = IORESOURCE_DMA,
 807         },
 808         {
 809                 .start = CH_SPORT0_RX,
 810                 .end = CH_SPORT0_RX,
 811                 .flags = IORESOURCE_DMA,
 812         },
 813         {
 814                 .start = IRQ_SPORT0_TX_STAT,
 815                 .end = IRQ_SPORT0_TX_STAT,
 816                 .flags = IORESOURCE_IRQ,
 817         },
 818         {
 819                 .start = IRQ_SPORT0_RX_STAT,
 820                 .end = IRQ_SPORT0_RX_STAT,
 821                 .flags = IORESOURCE_IRQ,
 822         },
 823 };
 824
 825 static const unsigned short bfin_snd_pin[] = {
 826         P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
 827         P_SPORT0_BFS, P_SPORT0_BD0, 0,
 828 };
 829
 830 static struct bfin_snd_platform_data bfin_snd_data = {
 831         .pin_req = bfin_snd_pin,
 832 };
 833
 834 static struct platform_device bfin_i2s = {
 835         .name = "bfin-i2s",
 836         .num_resources = ARRAY_SIZE(bfin_snd_resources),
 837         .resource = bfin_snd_resources,
 838         .dev = {
 839                 .platform_data = &bfin_snd_data,
 840         },
 841 };
 842 #endif
 843
 844 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
 845 static const char * const ad1836_link[] = {
 846         "bfin-i2s.0",
 847         "spi0.76",
 848 };
 849 static struct platform_device bfin_ad1836_machine = {
 850         .name = "bfin-snd-ad1836",
 851         .id = -1,
 852         .dev = {
 853                 .platform_data = (void *)ad1836_link,
 854         },
 855 };
 856 #endif
 857
 858 #if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
 859 static struct platform_device adau1761_device = {
 860         .name = "bfin-eval-adau1x61",
 861 };
 862 #endif
 863
 864 #if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
 865 #include <sound/adau17x1.h>
 866 static struct adau1761_platform_data adau1761_info = {
 867         .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
 868         .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
 869 };
 870 #endif
 871
 872 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
 873 #include <linux/videodev2.h>
 874 #include <media/blackfin/bfin_capture.h>
 875 #include <media/blackfin/ppi.h>
 876
 877 static const unsigned short ppi_req[] = {
 878         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
 879         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
 880         P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
 881         P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
 882 #if !IS_ENABLED(CONFIG_VIDEO_VS6624)
 883         P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
 884         P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
 885 #endif
 886         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
 887         0,
 888 };
 889
 890 static const struct ppi_info ppi_info = {
 891         .type = PPI_TYPE_EPPI3,
 892         .dma_ch = CH_EPPI0_CH0,
 893         .irq_err = IRQ_EPPI0_STAT,
 894         .base = (void __iomem *)EPPI0_STAT,
 895         .pin_req = ppi_req,
 896 };
 897
 898 #if IS_ENABLED(CONFIG_VIDEO_VS6624)
 899 static struct v4l2_input vs6624_inputs[] = {
 900         {
 901                 .index = 0,
 902                 .name = "Camera",
 903                 .type = V4L2_INPUT_TYPE_CAMERA,
 904                 .std = V4L2_STD_UNKNOWN,
 905         },
 906 };
 907
 908 static struct bcap_route vs6624_routes[] = {
 909         {
 910                 .input = 0,
 911                 .output = 0,
 912         },
 913 };
 914
 915 static const unsigned vs6624_ce_pin = GPIO_PE4;
 916
 917 static struct bfin_capture_config bfin_capture_data = {
 918         .card_name = "BF609",
 919         .inputs = vs6624_inputs,
 920         .num_inputs = ARRAY_SIZE(vs6624_inputs),
 921         .routes = vs6624_routes,
 922         .i2c_adapter_id = 0,
 923         .board_info = {
 924                 .type = "vs6624",
 925                 .addr = 0x10,
 926                 .platform_data = (void *)&vs6624_ce_pin,
 927         },
 928         .ppi_info = &ppi_info,
 929         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
 930                         | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
 931         .blank_pixels = 4,
 932 };
 933 #endif
 934
 935 #if IS_ENABLED(CONFIG_VIDEO_ADV7842)
 936 #include <media/adv7842.h>
 937
 938 static struct v4l2_input adv7842_inputs[] = {
 939         {
 940                 .index = 0,
 941                 .name = "Composite",
 942                 .type = V4L2_INPUT_TYPE_CAMERA,
 943                 .std = V4L2_STD_ALL,
 944                 .capabilities = V4L2_IN_CAP_STD,
 945         },
 946         {
 947                 .index = 1,
 948                 .name = "S-Video",
 949                 .type = V4L2_INPUT_TYPE_CAMERA,
 950                 .std = V4L2_STD_ALL,
 951                 .capabilities = V4L2_IN_CAP_STD,
 952         },
 953         {
 954                 .index = 2,
 955                 .name = "Component",
 956                 .type = V4L2_INPUT_TYPE_CAMERA,
 957                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 958         },
 959         {
 960                 .index = 3,
 961                 .name = "VGA",
 962                 .type = V4L2_INPUT_TYPE_CAMERA,
 963                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 964         },
 965         {
 966                 .index = 4,
 967                 .name = "HDMI",
 968                 .type = V4L2_INPUT_TYPE_CAMERA,
 969                 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
 970         },
 971 };
 972
 973 static struct bcap_route adv7842_routes[] = {
 974         {
 975                 .input = 3,
 976                 .output = 0,
 977                 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
 978                                 | EPPI_CTL_ACTIVE656),
 979         },
 980         {
 981                 .input = 4,
 982                 .output = 0,
 983         },
 984         {
 985                 .input = 2,
 986                 .output = 0,
 987         },
 988         {
 989                 .input = 1,
 990                 .output = 0,
 991         },
 992         {
 993                 .input = 0,
 994                 .output = 1,
 995                 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
 996                                 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
 997                                 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
 998         },
 999 };
1000
1001 static struct adv7842_output_format adv7842_opf[] = {
1002         {
1003                 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
1004                 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
1005                 .op_656_range = 1,
1006                 .blank_data = 1,
1007                 .insert_av_codes = 1,
1008         },
1009         {
1010                 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
1011                 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
1012                 .op_656_range = 1,
1013                 .blank_data = 1,
1014         },
1015 };
1016
1017 static struct adv7842_platform_data adv7842_data = {
1018         .opf = adv7842_opf,
1019         .num_opf = ARRAY_SIZE(adv7842_opf),
1020         .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
1021         .prim_mode = ADV7842_PRIM_MODE_SDP,
1022         .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
1023         .hdmi_free_run_enable = 1,
1024         .sdp_free_run_auto = 1,
1025         .llc_dll_phase = 0x10,
1026         .i2c_sdp_io = 0x40,
1027         .i2c_sdp = 0x41,
1028         .i2c_cp = 0x42,
1029         .i2c_vdp = 0x43,
1030         .i2c_afe = 0x44,
1031         .i2c_hdmi = 0x45,
1032         .i2c_repeater = 0x46,
1033         .i2c_edid = 0x47,
1034         .i2c_infoframe = 0x48,
1035         .i2c_cec = 0x49,
1036         .i2c_avlink = 0x4a,
1037         .i2c_ex = 0x26,
1038 };
1039
1040 static struct bfin_capture_config bfin_capture_data = {
1041         .card_name = "BF609",
1042         .inputs = adv7842_inputs,
1043         .num_inputs = ARRAY_SIZE(adv7842_inputs),
1044         .routes = adv7842_routes,
1045         .i2c_adapter_id = 0,
1046         .board_info = {
1047                 .type = "adv7842",
1048                 .addr = 0x20,
1049                 .platform_data = (void *)&adv7842_data,
1050         },
1051         .ppi_info = &ppi_info,
1052         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1053                         | EPPI_CTL_ACTIVE656),
1054 };
1055 #endif
1056
1057 static struct platform_device bfin_capture_device = {
1058         .name = "bfin_capture",
1059         .dev = {
1060                 .platform_data = &bfin_capture_data,
1061         },
1062 };
1063 #endif
1064
1065 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
1066 #include <linux/videodev2.h>
1067 #include <media/blackfin/bfin_display.h>
1068 #include <media/blackfin/ppi.h>
1069
1070 static const unsigned short ppi_req_disp[] = {
1071         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1072         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1073         P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1074         P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1075         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1076         0,
1077 };
1078
1079 static const struct ppi_info ppi_info = {
1080         .type = PPI_TYPE_EPPI3,
1081         .dma_ch = CH_EPPI0_CH0,
1082         .irq_err = IRQ_EPPI0_STAT,
1083         .base = (void __iomem *)EPPI0_STAT,
1084         .pin_req = ppi_req_disp,
1085 };
1086
1087 #if IS_ENABLED(CONFIG_VIDEO_ADV7511)
1088 #include <media/adv7511.h>
1089
1090 static struct v4l2_output adv7511_outputs[] = {
1091         {
1092                 .index = 0,
1093                 .name = "HDMI",
1094                 .type = V4L2_INPUT_TYPE_CAMERA,
1095                 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
1096         },
1097 };
1098
1099 static struct disp_route adv7511_routes[] = {
1100         {
1101                 .output = 0,
1102         },
1103 };
1104
1105 static struct adv7511_platform_data adv7511_data = {
1106         .edid_addr = 0x7e,
1107         .i2c_ex = 0x25,
1108 };
1109
1110 static struct bfin_display_config bfin_display_data = {
1111         .card_name = "BF609",
1112         .outputs = adv7511_outputs,
1113         .num_outputs = ARRAY_SIZE(adv7511_outputs),
1114         .routes = adv7511_routes,
1115         .i2c_adapter_id = 0,
1116         .board_info = {
1117                 .type = "adv7511",
1118                 .addr = 0x39,
1119                 .platform_data = (void *)&adv7511_data,
1120         },
1121         .ppi_info = &ppi_info,
1122         .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1123                         | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1124                         | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1125                         | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1126 };
1127 #endif
1128
1129 #if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1130 #include <media/adv7343.h>
1131
1132 static struct v4l2_output adv7343_outputs[] = {
1133         {
1134                 .index = 0,
1135                 .name = "Composite",
1136                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1137                 .std = V4L2_STD_ALL,
1138                 .capabilities = V4L2_OUT_CAP_STD,
1139         },
1140         {
1141                 .index = 1,
1142                 .name = "S-Video",
1143                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1144                 .std = V4L2_STD_ALL,
1145                 .capabilities = V4L2_OUT_CAP_STD,
1146         },
1147         {
1148                 .index = 2,
1149                 .name = "Component",
1150                 .type = V4L2_OUTPUT_TYPE_ANALOG,
1151                 .std = V4L2_STD_ALL,
1152                 .capabilities = V4L2_OUT_CAP_STD,
1153         },
1154
1155 };
1156
1157 static struct disp_route adv7343_routes[] = {
1158         {
1159                 .output = ADV7343_COMPOSITE_ID,
1160         },
1161         {
1162                 .output = ADV7343_SVIDEO_ID,
1163         },
1164         {
1165                 .output = ADV7343_COMPONENT_ID,
1166         },
1167 };
1168
1169 static struct adv7343_platform_data adv7343_data = {
1170         .mode_config = {
1171                 .sleep_mode = false,
1172                 .pll_control = false,
1173                 .dac_1 = true,
1174                 .dac_2 = true,
1175                 .dac_3 = true,
1176                 .dac_4 = true,
1177                 .dac_5 = true,
1178                 .dac_6 = true,
1179         },
1180         .sd_config = {
1181                 .sd_dac_out1 = false,
1182                 .sd_dac_out2 = false,
1183         },
1184 };
1185
1186 static struct bfin_display_config bfin_display_data = {
1187         .card_name = "BF609",
1188         .outputs = adv7343_outputs,
1189         .num_outputs = ARRAY_SIZE(adv7343_outputs),
1190         .routes = adv7343_routes,
1191         .i2c_adapter_id = 0,
1192         .board_info = {
1193                 .type = "adv7343",
1194                 .addr = 0x2b,
1195                 .platform_data = (void *)&adv7343_data,
1196         },
1197         .ppi_info = &ppi_info_disp,
1198         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1199                         | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1200                         | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1201 };
1202 #endif
1203
1204 static struct platform_device bfin_display_device = {
1205         .name = "bfin_display",
1206         .dev = {
1207                 .platform_data = &bfin_display_data,
1208         },
1209 };
1210 #endif
1211
1212 #if defined(CONFIG_BFIN_CRC)
1213 #define BFIN_CRC_NAME "bfin-crc"
1214
1215 static struct resource bfin_crc0_resources[] = {
1216         {
1217                 .start = REG_CRC0_CTL,
1218                 .end = REG_CRC0_REVID+4,
1219                 .flags = IORESOURCE_MEM,
1220         },
1221         {
1222                 .start = IRQ_CRC0_DCNTEXP,
1223                 .end = IRQ_CRC0_DCNTEXP,
1224                 .flags = IORESOURCE_IRQ,
1225         },
1226         {
1227                 .start = CH_MEM_STREAM0_SRC_CRC0,
1228                 .end = CH_MEM_STREAM0_SRC_CRC0,
1229                 .flags = IORESOURCE_DMA,
1230         },
1231         {
1232                 .start = CH_MEM_STREAM0_DEST_CRC0,
1233                 .end = CH_MEM_STREAM0_DEST_CRC0,
1234                 .flags = IORESOURCE_DMA,
1235         },
1236 };
1237
1238 static struct platform_device bfin_crc0_device = {
1239         .name = BFIN_CRC_NAME,
1240         .id = 0,
1241         .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1242         .resource = bfin_crc0_resources,
1243 };
1244
1245 static struct resource bfin_crc1_resources[] = {
1246         {
1247                 .start = REG_CRC1_CTL,
1248                 .end = REG_CRC1_REVID+4,
1249                 .flags = IORESOURCE_MEM,
1250         },
1251         {
1252                 .start = IRQ_CRC1_DCNTEXP,
1253                 .end = IRQ_CRC1_DCNTEXP,
1254                 .flags = IORESOURCE_IRQ,
1255         },
1256         {
1257                 .start = CH_MEM_STREAM1_SRC_CRC1,
1258                 .end = CH_MEM_STREAM1_SRC_CRC1,
1259                 .flags = IORESOURCE_DMA,
1260         },
1261         {
1262                 .start = CH_MEM_STREAM1_DEST_CRC1,
1263                 .end = CH_MEM_STREAM1_DEST_CRC1,
1264                 .flags = IORESOURCE_DMA,
1265         },
1266 };
1267
1268 static struct platform_device bfin_crc1_device = {
1269         .name = BFIN_CRC_NAME,
1270         .id = 1,
1271         .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1272         .resource = bfin_crc1_resources,
1273 };
1274 #endif
1275
1276 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1277 #define BFIN_CRYPTO_CRC_NAME            "bfin-hmac-crc"
1278 #define BFIN_CRYPTO_CRC_POLY_DATA       0x5c5c5c5c
1279
1280 static struct resource bfin_crypto_crc_resources[] = {
1281         {
1282                 .start = REG_CRC0_CTL,
1283                 .end = REG_CRC0_REVID+4,
1284                 .flags = IORESOURCE_MEM,
1285         },
1286         {
1287                 .start = IRQ_CRC0_DCNTEXP,
1288                 .end = IRQ_CRC0_DCNTEXP,
1289                 .flags = IORESOURCE_IRQ,
1290         },
1291         {
1292                 .start = CH_MEM_STREAM0_SRC_CRC0,
1293                 .end = CH_MEM_STREAM0_SRC_CRC0,
1294                 .flags = IORESOURCE_DMA,
1295         },
1296 };
1297
1298 static struct platform_device bfin_crypto_crc_device = {
1299         .name = BFIN_CRYPTO_CRC_NAME,
1300         .id = 0,
1301         .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1302         .resource = bfin_crypto_crc_resources,
1303         .dev = {
1304                 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1305         },
1306 };
1307 #endif
1308
1309 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1310 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1311         .model                  = 7877,
1312         .vref_delay_usecs       = 50,   /* internal, no capacitor */
1313         .x_plate_ohms           = 419,
1314         .y_plate_ohms           = 486,
1315         .pressure_max           = 1000,
1316         .pressure_min           = 0,
1317         .stopacq_polarity       = 1,
1318         .first_conversion_delay = 3,
1319         .acquisition_time       = 1,
1320         .averaging              = 1,
1321         .pen_down_acc_interval  = 1,
1322 };
1323 #endif
1324
1325 #ifdef CONFIG_PINCTRL_ADI2
1326
1327 # define ADI_PINT_DEVNAME "adi-gpio-pint"
1328 # define ADI_GPIO_DEVNAME "adi-gpio"
1329 # define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1330
1331 static struct platform_device bfin_pinctrl_device = {
1332         .name = ADI_PINCTRL_DEVNAME,
1333         .id = 0,
1334 };
1335
1336 static struct resource bfin_pint0_resources[] = {
1337         {
1338                 .start = PINT0_MASK_SET,
1339                 .end = PINT0_LATCH + 3,
1340                 .flags = IORESOURCE_MEM,
1341         },
1342         {
1343                 .start = IRQ_PINT0,
1344                 .end = IRQ_PINT0,
1345                 .flags = IORESOURCE_IRQ,
1346         },
1347 };
1348
1349 static struct platform_device bfin_pint0_device = {
1350         .name = ADI_PINT_DEVNAME,
1351         .id = 0,
1352         .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1353         .resource = bfin_pint0_resources,
1354 };
1355
1356 static struct resource bfin_pint1_resources[] = {
1357         {
1358                 .start = PINT1_MASK_SET,
1359                 .end = PINT1_LATCH + 3,
1360                 .flags = IORESOURCE_MEM,
1361         },
1362         {
1363                 .start = IRQ_PINT1,
1364                 .end = IRQ_PINT1,
1365                 .flags = IORESOURCE_IRQ,
1366         },
1367 };
1368
1369 static struct platform_device bfin_pint1_device = {
1370         .name = ADI_PINT_DEVNAME,
1371         .id = 1,
1372         .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1373         .resource = bfin_pint1_resources,
1374 };
1375
1376 static struct resource bfin_pint2_resources[] = {
1377         {
1378                 .start = PINT2_MASK_SET,
1379                 .end = PINT2_LATCH + 3,
1380                 .flags = IORESOURCE_MEM,
1381         },
1382         {
1383                 .start = IRQ_PINT2,
1384                 .end = IRQ_PINT2,
1385                 .flags = IORESOURCE_IRQ,
1386         },
1387 };
1388
1389 static struct platform_device bfin_pint2_device = {
1390         .name = ADI_PINT_DEVNAME,
1391         .id = 2,
1392         .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1393         .resource = bfin_pint2_resources,
1394 };
1395
1396 static struct resource bfin_pint3_resources[] = {
1397         {
1398                 .start = PINT3_MASK_SET,
1399                 .end = PINT3_LATCH + 3,
1400                 .flags = IORESOURCE_MEM,
1401         },
1402         {
1403                 .start = IRQ_PINT3,
1404                 .end = IRQ_PINT3,
1405                 .flags = IORESOURCE_IRQ,
1406         },
1407 };
1408
1409 static struct platform_device bfin_pint3_device = {
1410         .name = ADI_PINT_DEVNAME,
1411         .id = 3,
1412         .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1413         .resource = bfin_pint3_resources,
1414 };
1415
1416 static struct resource bfin_pint4_resources[] = {
1417         {
1418                 .start = PINT4_MASK_SET,
1419                 .end = PINT4_LATCH + 3,
1420                 .flags = IORESOURCE_MEM,
1421         },
1422         {
1423                 .start = IRQ_PINT4,
1424                 .end = IRQ_PINT4,
1425                 .flags = IORESOURCE_IRQ,
1426         },
1427 };
1428
1429 static struct platform_device bfin_pint4_device = {
1430         .name = ADI_PINT_DEVNAME,
1431         .id = 4,
1432         .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1433         .resource = bfin_pint4_resources,
1434 };
1435
1436 static struct resource bfin_pint5_resources[] = {
1437         {
1438                 .start = PINT5_MASK_SET,
1439                 .end = PINT5_LATCH + 3,
1440                 .flags = IORESOURCE_MEM,
1441         },
1442         {
1443                 .start = IRQ_PINT5,
1444                 .end = IRQ_PINT5,
1445                 .flags = IORESOURCE_IRQ,
1446         },
1447 };
1448
1449 static struct platform_device bfin_pint5_device = {
1450         .name = ADI_PINT_DEVNAME,
1451         .id = 5,
1452         .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1453         .resource = bfin_pint5_resources,
1454 };
1455
1456 static struct resource bfin_gpa_resources[] = {
1457         {
1458                 .start = PORTA_FER,
1459                 .end = PORTA_MUX + 3,
1460                 .flags = IORESOURCE_MEM,
1461         },
1462         {       /* optional */
1463                 .start = IRQ_PA0,
1464                 .end = IRQ_PA0,
1465                 .flags = IORESOURCE_IRQ,
1466         },
1467 };
1468
1469 static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1470         .port_pin_base  = GPIO_PA0,
1471         .port_width     = GPIO_BANKSIZE,
1472         .pint_id        = 0,            /* PINT0 */
1473         .pint_assign    = true,         /* PINT upper 16 bit */
1474         .pint_map       = 0,            /* mapping mask in PINT */
1475 };
1476
1477 static struct platform_device bfin_gpa_device = {
1478         .name = ADI_GPIO_DEVNAME,
1479         .id = 0,
1480         .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1481         .resource = bfin_gpa_resources,
1482         .dev = {
1483                 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1484         },
1485 };
1486
1487 static struct resource bfin_gpb_resources[] = {
1488         {
1489                 .start = PORTB_FER,
1490                 .end = PORTB_MUX + 3,
1491                 .flags = IORESOURCE_MEM,
1492         },
1493         {
1494                 .start = IRQ_PB0,
1495                 .end = IRQ_PB0,
1496                 .flags = IORESOURCE_IRQ,
1497         },
1498 };
1499
1500 static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1501         .port_pin_base  = GPIO_PB0,
1502         .port_width     = GPIO_BANKSIZE,
1503         .pint_id        = 0,
1504         .pint_assign    = false,
1505         .pint_map       = 1,
1506 };
1507
1508 static struct platform_device bfin_gpb_device = {
1509         .name = ADI_GPIO_DEVNAME,
1510         .id = 1,
1511         .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1512         .resource = bfin_gpb_resources,
1513         .dev = {
1514                 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1515         },
1516 };
1517
1518 static struct resource bfin_gpc_resources[] = {
1519         {
1520                 .start = PORTC_FER,
1521                 .end = PORTC_MUX + 3,
1522                 .flags = IORESOURCE_MEM,
1523         },
1524         {
1525                 .start = IRQ_PC0,
1526                 .end = IRQ_PC0,
1527                 .flags = IORESOURCE_IRQ,
1528         },
1529 };
1530
1531 static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1532         .port_pin_base  = GPIO_PC0,
1533         .port_width     = GPIO_BANKSIZE,
1534         .pint_id        = 1,
1535         .pint_assign    = false,
1536         .pint_map       = 1,
1537 };
1538
1539 static struct platform_device bfin_gpc_device = {
1540         .name = ADI_GPIO_DEVNAME,
1541         .id = 2,
1542         .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1543         .resource = bfin_gpc_resources,
1544         .dev = {
1545                 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1546         },
1547 };
1548
1549 static struct resource bfin_gpd_resources[] = {
1550         {
1551                 .start = PORTD_FER,
1552                 .end = PORTD_MUX + 3,
1553                 .flags = IORESOURCE_MEM,
1554         },
1555         {
1556                 .start = IRQ_PD0,
1557                 .end = IRQ_PD0,
1558                 .flags = IORESOURCE_IRQ,
1559         },
1560 };
1561
1562 static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1563         .port_pin_base  = GPIO_PD0,
1564         .port_width     = GPIO_BANKSIZE,
1565         .pint_id        = 2,
1566         .pint_assign    = false,
1567         .pint_map       = 1,
1568 };
1569
1570 static struct platform_device bfin_gpd_device = {
1571         .name = ADI_GPIO_DEVNAME,
1572         .id = 3,
1573         .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1574         .resource = bfin_gpd_resources,
1575         .dev = {
1576                 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1577         },
1578 };
1579
1580 static struct resource bfin_gpe_resources[] = {
1581         {
1582                 .start = PORTE_FER,
1583                 .end = PORTE_MUX + 3,
1584                 .flags = IORESOURCE_MEM,
1585         },
1586         {
1587                 .start = IRQ_PE0,
1588                 .end = IRQ_PE0,
1589                 .flags = IORESOURCE_IRQ,
1590         },
1591 };
1592
1593 static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1594         .port_pin_base  = GPIO_PE0,
1595         .port_width     = GPIO_BANKSIZE,
1596         .pint_id        = 3,
1597         .pint_assign    = false,
1598         .pint_map       = 1,
1599 };
1600
1601 static struct platform_device bfin_gpe_device = {
1602         .name = ADI_GPIO_DEVNAME,
1603         .id = 4,
1604         .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1605         .resource = bfin_gpe_resources,
1606         .dev = {
1607                 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1608         },
1609 };
1610
1611 static struct resource bfin_gpf_resources[] = {
1612         {
1613                 .start = PORTF_FER,
1614                 .end = PORTF_MUX + 3,
1615                 .flags = IORESOURCE_MEM,
1616         },
1617         {
1618                 .start = IRQ_PF0,
1619                 .end = IRQ_PF0,
1620                 .flags = IORESOURCE_IRQ,
1621         },
1622 };
1623
1624 static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1625         .port_pin_base  = GPIO_PF0,
1626         .port_width     = GPIO_BANKSIZE,
1627         .pint_id        = 4,
1628         .pint_assign    = false,
1629         .pint_map       = 1,
1630 };
1631
1632 static struct platform_device bfin_gpf_device = {
1633         .name = ADI_GPIO_DEVNAME,
1634         .id = 5,
1635         .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1636         .resource = bfin_gpf_resources,
1637         .dev = {
1638                 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1639         },
1640 };
1641
1642 static struct resource bfin_gpg_resources[] = {
1643         {
1644                 .start = PORTG_FER,
1645                 .end = PORTG_MUX + 3,
1646                 .flags = IORESOURCE_MEM,
1647         },
1648         {
1649                 .start = IRQ_PG0,
1650                 .end = IRQ_PG0,
1651                 .flags = IORESOURCE_IRQ,
1652         },
1653 };
1654
1655 static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1656         .port_pin_base  = GPIO_PG0,
1657         .port_width     = GPIO_BANKSIZE,
1658         .pint_id        = 5,
1659         .pint_assign    = false,
1660         .pint_map       = 1,
1661 };
1662
1663 static struct platform_device bfin_gpg_device = {
1664         .name = ADI_GPIO_DEVNAME,
1665         .id = 6,
1666         .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1667         .resource = bfin_gpg_resources,
1668         .dev = {
1669                 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1670         },
1671 };
1672
1673 #endif
1674
1675 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
1676 #include <linux/input.h>
1677 #include <linux/gpio_keys.h>
1678
1679 static struct gpio_keys_button bfin_gpio_keys_table[] = {
1680         {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1681         {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1682 };
1683
1684 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1685         .buttons        = bfin_gpio_keys_table,
1686         .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
1687 };
1688
1689 static struct platform_device bfin_device_gpiokeys = {
1690         .name      = "gpio-keys",
1691         .dev = {
1692                 .platform_data = &bfin_gpio_keys_data,
1693         },
1694 };
1695 #endif
1696
1697 static struct spi_board_info bfin_spi_board_info[] __initdata = {
1698 #if IS_ENABLED(CONFIG_MTD_M25P80)
1699         {
1700                 /* the modalias must be the same as spi device driver name */
1701                 .modalias = "m25p80", /* Name of spi_driver for this device */
1702                 .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
1703                 .bus_num = 0, /* Framework bus number */
1704                 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1705                 .platform_data = &bfin_spi_flash_data,
1706                 .controller_data = &spi_flash_chip_info,
1707                 .mode = SPI_MODE_3,
1708         },
1709 #endif
1710 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1711         {
1712                 .modalias               = "ad7877",
1713                 .platform_data          = &bfin_ad7877_ts_info,
1714                 .irq                    = IRQ_PD9,
1715                 .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
1716                 .bus_num                = 0,
1717                 .chip_select            = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
1718         },
1719 #endif
1720 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
1721         {
1722                 .modalias = "spidev",
1723                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
1724                 .bus_num = 0,
1725                 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1726                 .controller_data = &spidev_chip_info,
1727         },
1728 #endif
1729 #if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
1730         {
1731                 .modalias               = "adxl34x",
1732                 .platform_data          = &adxl34x_info,
1733                 .irq                    = IRQ_PC5,
1734                 .max_speed_hz           = 5000000,     /* max spi clock (SCK) speed in HZ */
1735                 .bus_num                = 1,
1736                 .chip_select            = 2,
1737                 .mode = SPI_MODE_3,
1738         },
1739 #endif
1740 };
1741 #if IS_ENABLED(CONFIG_SPI_ADI_V3)
1742 /* SPI (0) */
1743 static struct resource bfin_spi0_resource[] = {
1744         {
1745                 .start = SPI0_REGBASE,
1746                 .end   = SPI0_REGBASE + 0xFF,
1747                 .flags = IORESOURCE_MEM,
1748         },
1749         {
1750                 .start = CH_SPI0_TX,
1751                 .end   = CH_SPI0_TX,
1752                 .flags = IORESOURCE_DMA,
1753         },
1754         {
1755                 .start = CH_SPI0_RX,
1756                 .end   = CH_SPI0_RX,
1757                 .flags = IORESOURCE_DMA,
1758         },
1759 };
1760
1761 /* SPI (1) */
1762 static struct resource bfin_spi1_resource[] = {
1763         {
1764                 .start = SPI1_REGBASE,
1765                 .end   = SPI1_REGBASE + 0xFF,
1766                 .flags = IORESOURCE_MEM,
1767         },
1768         {
1769                 .start = CH_SPI1_TX,
1770                 .end   = CH_SPI1_TX,
1771                 .flags = IORESOURCE_DMA,
1772         },
1773         {
1774                 .start = CH_SPI1_RX,
1775                 .end   = CH_SPI1_RX,
1776                 .flags = IORESOURCE_DMA,
1777         },
1778
1779 };
1780
1781 /* SPI controller data */
1782 static struct adi_spi3_master bf60x_spi_master_info0 = {
1783         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1784         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1785 };
1786
1787 static struct platform_device bf60x_spi_master0 = {
1788         .name = "adi-spi3",
1789         .id = 0, /* Bus number */
1790         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1791         .resource = bfin_spi0_resource,
1792         .dev = {
1793                 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1794         },
1795 };
1796
1797 static struct adi_spi3_master bf60x_spi_master_info1 = {
1798         .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1799         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1800 };
1801
1802 static struct platform_device bf60x_spi_master1 = {
1803         .name = "adi-spi3",
1804         .id = 1, /* Bus number */
1805         .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1806         .resource = bfin_spi1_resource,
1807         .dev = {
1808                 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1809         },
1810 };
1811 #endif  /* spi master and devices */
1812
1813 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
1814 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1815
1816 static struct resource bfin_twi0_resource[] = {
1817         [0] = {
1818                 .start = TWI0_CLKDIV,
1819                 .end   = TWI0_CLKDIV + 0xFF,
1820                 .flags = IORESOURCE_MEM,
1821         },
1822         [1] = {
1823                 .start = IRQ_TWI0,
1824                 .end   = IRQ_TWI0,
1825                 .flags = IORESOURCE_IRQ,
1826         },
1827 };
1828
1829 static struct platform_device i2c_bfin_twi0_device = {
1830         .name = "i2c-bfin-twi",
1831         .id = 0,
1832         .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1833         .resource = bfin_twi0_resource,
1834         .dev = {
1835                 .platform_data = &bfin_twi0_pins,
1836         },
1837 };
1838
1839 static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1840
1841 static struct resource bfin_twi1_resource[] = {
1842         [0] = {
1843                 .start = TWI1_CLKDIV,
1844                 .end   = TWI1_CLKDIV + 0xFF,
1845                 .flags = IORESOURCE_MEM,
1846         },
1847         [1] = {
1848                 .start = IRQ_TWI1,
1849                 .end   = IRQ_TWI1,
1850                 .flags = IORESOURCE_IRQ,
1851         },
1852 };
1853
1854 static struct platform_device i2c_bfin_twi1_device = {
1855         .name = "i2c-bfin-twi",
1856         .id = 1,
1857         .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1858         .resource = bfin_twi1_resource,
1859         .dev = {
1860                 .platform_data = &bfin_twi1_pins,
1861         },
1862 };
1863 #endif
1864
1865 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1866 #if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
1867         {
1868                 I2C_BOARD_INFO("adxl34x", 0x53),
1869                 .irq = IRQ_PC5,
1870                 .platform_data = (void *)&adxl34x_info,
1871         },
1872 #endif
1873 #if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
1874         {
1875                 I2C_BOARD_INFO("adau1761", 0x38),
1876                 .platform_data = (void *)&adau1761_info
1877         },
1878 #endif
1879 #if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
1880         {
1881                 I2C_BOARD_INFO("ssm2602", 0x1b),
1882         },
1883 #endif
1884 };
1885
1886 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1887 };
1888
1889 static const unsigned int cclk_vlev_datasheet[] =
1890 {
1891 /*
1892  * Internal VLEV BF54XSBBC1533
1893  ****temporarily using these values until data sheet is updated
1894  */
1895         VRPAIR(VLEV_085, 150000000),
1896         VRPAIR(VLEV_090, 250000000),
1897         VRPAIR(VLEV_110, 276000000),
1898         VRPAIR(VLEV_115, 301000000),
1899         VRPAIR(VLEV_120, 525000000),
1900         VRPAIR(VLEV_125, 550000000),
1901         VRPAIR(VLEV_130, 600000000),
1902 };
1903
1904 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1905         .tuple_tab = cclk_vlev_datasheet,
1906         .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1907         .vr_settling_time = 25 /* us */,
1908 };
1909
1910 static struct platform_device bfin_dpmc = {
1911         .name = "bfin dpmc",
1912         .dev = {
1913                 .platform_data = &bfin_dmpc_vreg_data,
1914         },
1915 };
1916
1917 static struct platform_device *ezkit_devices[] __initdata = {
1918
1919         &bfin_dpmc,
1920 #if defined(CONFIG_PINCTRL_ADI2)
1921         &bfin_pinctrl_device,
1922         &bfin_pint0_device,
1923         &bfin_pint1_device,
1924         &bfin_pint2_device,
1925         &bfin_pint3_device,
1926         &bfin_pint4_device,
1927         &bfin_pint5_device,
1928         &bfin_gpa_device,
1929         &bfin_gpb_device,
1930         &bfin_gpc_device,
1931         &bfin_gpd_device,
1932         &bfin_gpe_device,
1933         &bfin_gpf_device,
1934         &bfin_gpg_device,
1935 #endif
1936
1937 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
1938         &rtc_device,
1939 #endif
1940
1941 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
1942 #ifdef CONFIG_SERIAL_BFIN_UART0
1943         &bfin_uart0_device,
1944 #endif
1945 #ifdef CONFIG_SERIAL_BFIN_UART1
1946         &bfin_uart1_device,
1947 #endif
1948 #endif
1949
1950 #if IS_ENABLED(CONFIG_BFIN_SIR)
1951 #ifdef CONFIG_BFIN_SIR0
1952         &bfin_sir0_device,
1953 #endif
1954 #ifdef CONFIG_BFIN_SIR1
1955         &bfin_sir1_device,
1956 #endif
1957 #endif
1958
1959 #if IS_ENABLED(CONFIG_STMMAC_ETH)
1960         &bfin_eth_device,
1961 #endif
1962
1963 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
1964         &musb_device,
1965 #endif
1966
1967 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
1968         &bfin_isp1760_device,
1969 #endif
1970
1971 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
1972 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1973         &bfin_sport0_uart_device,
1974 #endif
1975 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1976         &bfin_sport1_uart_device,
1977 #endif
1978 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1979         &bfin_sport2_uart_device,
1980 #endif
1981 #endif
1982
1983 #if IS_ENABLED(CONFIG_CAN_BFIN)
1984         &bfin_can0_device,
1985 #endif
1986
1987 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
1988         &bfin_nand_device,
1989 #endif
1990
1991 #if IS_ENABLED(CONFIG_SDH_BFIN)
1992         &bfin_sdh_device,
1993 #endif
1994
1995 #if IS_ENABLED(CONFIG_SPI_ADI_V3)
1996         &bf60x_spi_master0,
1997         &bf60x_spi_master1,
1998 #endif
1999
2000 #if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
2001         &bfin_rotary_device,
2002 #endif
2003
2004 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
2005         &i2c_bfin_twi0_device,
2006 #if !defined(CONFIG_BF542)
2007         &i2c_bfin_twi1_device,
2008 #endif
2009 #endif
2010
2011 #if defined(CONFIG_BFIN_CRC)
2012         &bfin_crc0_device,
2013         &bfin_crc1_device,
2014 #endif
2015 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
2016         &bfin_crypto_crc_device,
2017 #endif
2018
2019 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
2020         &bfin_device_gpiokeys,
2021 #endif
2022
2023 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
2024         &ezkit_flash_device,
2025 #endif
2026 #if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
2027         &bfin_pcm,
2028 #endif
2029 #if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
2030         &bfin_i2s,
2031 #endif
2032 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
2033         &bfin_ad1836_machine,
2034 #endif
2035 #if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
2036         &adau1761_device,
2037 #endif
2038 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
2039         &bfin_capture_device,
2040 #endif
2041 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
2042         &bfin_display_device,
2043 #endif
2044
2045 };
2046
2047 /* Pin control settings */
2048 static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2049         /* per-device maps */
2050         PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0",  "pinctrl-adi2.0", NULL, "uart0"),
2051         PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1",  "pinctrl-adi2.0", NULL, "uart1"),
2052         PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0",  "pinctrl-adi2.0", NULL, "uart0"),
2053         PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1",  "pinctrl-adi2.0", NULL, "uart1"),
2054         PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0",  "pinctrl-adi2.0", NULL, "rsi0"),
2055         PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0",  "pinctrl-adi2.0", NULL, "eth0"),
2056         PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0",  "pinctrl-adi2.0", NULL, "spi0"),
2057         PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1",  "pinctrl-adi2.0", NULL, "spi1"),
2058         PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0",  "pinctrl-adi2.0", NULL, "twi0"),
2059         PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1",  "pinctrl-adi2.0", NULL, "twi1"),
2060         PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary",  "pinctrl-adi2.0", NULL, "rotary"),
2061         PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0",  "pinctrl-adi2.0", NULL, "can0"),
2062         PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0",  "pinctrl-adi2.0", NULL, "smc0"),
2063         PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2064         PIN_MAP_MUX_GROUP("bfin_display.0", "8bit",  "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"),
2065         PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2066         PIN_MAP_MUX_GROUP("bfin_display.0", "16bit",  "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
2067         PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit",  "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"),
2068         PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0",  "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
2069         PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit",  "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
2070         PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit",  "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
2071         PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0",  "pinctrl-adi2.0", NULL, "sport0"),
2072         PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0",  "pinctrl-adi2.0", NULL, "sport0"),
2073         PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1",  "pinctrl-adi2.0", NULL, "sport1"),
2074         PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1",  "pinctrl-adi2.0", NULL, "sport1"),
2075         PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2",  "pinctrl-adi2.0", NULL, "sport2"),
2076         PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2",  "pinctrl-adi2.0", NULL, "sport2"),
2077 };
2078
2079 static int __init ezkit_init(void)
2080 {
2081         printk(KERN_INFO "%s(): registering device resources\n", __func__);
2082
2083         /* Initialize pinmuxing */
2084         pinctrl_register_mappings(bfin_pinmux_map,
2085                                 ARRAY_SIZE(bfin_pinmux_map));
2086
2087         i2c_register_board_info(0, bfin_i2c_board_info0,
2088                                 ARRAY_SIZE(bfin_i2c_board_info0));
2089         i2c_register_board_info(1, bfin_i2c_board_info1,
2090                                 ARRAY_SIZE(bfin_i2c_board_info1));
2091
2092         platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
2093
2094         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2095
2096         return 0;
2097 }
2098
2099 arch_initcall(ezkit_init);
2100
2101 static struct platform_device *ezkit_early_devices[] __initdata = {
2102 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2103 #ifdef CONFIG_SERIAL_BFIN_UART0
2104         &bfin_uart0_device,
2105 #endif
2106 #ifdef CONFIG_SERIAL_BFIN_UART1
2107         &bfin_uart1_device,
2108 #endif
2109 #endif
2110 };
2111
2112 void __init native_machine_early_platform_add_devices(void)
2113 {
2114         printk(KERN_INFO "register early platform devices\n");
2115         early_platform_add_devices(ezkit_early_devices,
2116                 ARRAY_SIZE(ezkit_early_devices));
2117 }