1 # SPDX-License-Identifier: GPL-2.0
8 config RWSEM_GENERIC_SPINLOCK
11 config RWSEM_XCHGADD_ALGORITHM
17 select HAVE_ARCH_TRACEHOOK
18 select HAVE_DYNAMIC_FTRACE
19 select HAVE_FTRACE_MCOUNT_RECORD
20 select HAVE_FUNCTION_GRAPH_TRACER
21 select HAVE_FUNCTION_TRACER
23 select HAVE_KERNEL_GZIP if RAMKERNEL
24 select HAVE_KERNEL_BZIP2 if RAMKERNEL
25 select HAVE_KERNEL_LZMA if RAMKERNEL
26 select HAVE_KERNEL_LZO if RAMKERNEL
28 select HAVE_PERF_EVENTS
29 select ARCH_HAVE_CUSTOM_GPIO_H
32 select HAVE_UNDERSCORE_SYMBOL_PREFIX
34 select ARCH_WANT_IPC_PARSE_VERSION
35 select GENERIC_ATOMIC64
36 select GENERIC_IRQ_PROBE
37 select GENERIC_IRQ_SHOW
38 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
39 select GENERIC_SMP_IDLE_THREAD
40 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
41 select HAVE_MOD_ARCH_SPECIFIC
42 select MODULES_USE_ELF_RELA
43 select HAVE_DEBUG_STACKOVERFLOW
45 select ARCH_NO_COHERENT_DMA_MMAP
57 config FORCE_MAX_ZONEORDER
61 config GENERIC_CALIBRATE_DELAY
64 config LOCKDEP_SUPPORT
67 config STACKTRACE_SUPPORT
70 config TRACE_IRQFLAGS_SUPPORT
75 source "kernel/Kconfig.preempt"
77 source "kernel/Kconfig.freezer"
79 menu "Blackfin Processor Options"
81 comment "Processor and Board Settings"
90 BF512 Processor Support.
95 BF514 Processor Support.
100 BF516 Processor Support.
105 BF518 Processor Support.
110 BF522 Processor Support.
115 BF523 Processor Support.
120 BF524 Processor Support.
125 BF525 Processor Support.
130 BF526 Processor Support.
135 BF527 Processor Support.
140 BF531 Processor Support.
145 BF532 Processor Support.
150 BF533 Processor Support.
155 BF534 Processor Support.
160 BF536 Processor Support.
165 BF537 Processor Support.
170 BF538 Processor Support.
175 BF539 Processor Support.
180 BF542 Processor Support.
185 BF542 Processor Support.
190 BF544 Processor Support.
195 BF544 Processor Support.
200 BF547 Processor Support.
205 BF547 Processor Support.
210 BF548 Processor Support.
215 BF548 Processor Support.
220 BF549 Processor Support.
225 BF549 Processor Support.
230 BF561 Processor Support.
236 BF609 Processor Support.
242 select TICKSOURCE_CORETMR
243 bool "Symmetric multi-processing support"
245 This enables support for systems with more than one CPU,
246 like the dual core BF561. If you have a system with only one
247 CPU, say N. If you have a system with more than one CPU, say Y.
249 If you don't know what to do here, say N.
257 bool "Support for hot-pluggable CPUs"
263 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
264 default 2 if (BF537 || BF536 || BF534)
265 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
266 default 4 if (BF538 || BF539)
270 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
271 default 3 if (BF537 || BF536 || BF534 || BF54xM)
272 default 5 if (BF561 || BF538 || BF539)
273 default 6 if (BF533 || BF532 || BF531)
277 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
278 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
279 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
283 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
287 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
291 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
295 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
299 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
303 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
307 depends on (BF533 || BF532 || BF531)
319 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
324 depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
328 depends on BF54x || BF60x
330 config MEM_MT48LC64M4A2FB_7E
332 depends on (BFIN533_STAMP)
335 config MEM_MT48LC16M16A2TG_75
337 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
338 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
339 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
340 || BFIN527_BLUETECHNIX_CM)
343 config MEM_MT48LC32M8A2_75
345 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
348 config MEM_MT48LC8M32B2B5_7
350 depends on (BFIN561_BLUETECHNIX_CM)
353 config MEM_MT48LC32M16A2TG_75
355 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
358 config MEM_MT48H32M16LFCJ_75
360 depends on (BFIN526_EZBRD)
363 config MEM_MT47H64M16
365 depends on (BFIN609_EZKIT)
368 source "arch/blackfin/mach-bf518/Kconfig"
369 source "arch/blackfin/mach-bf527/Kconfig"
370 source "arch/blackfin/mach-bf533/Kconfig"
371 source "arch/blackfin/mach-bf561/Kconfig"
372 source "arch/blackfin/mach-bf537/Kconfig"
373 source "arch/blackfin/mach-bf538/Kconfig"
374 source "arch/blackfin/mach-bf548/Kconfig"
375 source "arch/blackfin/mach-bf609/Kconfig"
377 menu "Board customizations"
380 bool "Default bootloader kernel arguments"
383 string "Initial kernel command string"
384 depends on CMDLINE_BOOL
385 default "console=ttyBF0,57600"
387 If you don't have a boot loader capable of passing a command line string
388 to the kernel, you may specify one here. As a minimum, you should specify
389 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
392 hex "Kernel load address for booting"
394 range 0x1000 0x20000000
396 This option allows you to set the load address of the kernel.
397 This can be useful if you are on a board which has a small amount
398 of memory or you wish to reserve some memory at the beginning of
401 Note that you need to keep this value above 4k (0x1000) as this
402 memory region is used to capture NULL pointer references as well
403 as some core kernel functions.
405 config PHY_RAM_BASE_ADDRESS
406 hex "Physical RAM Base"
409 set BF609 FPGA physical SRAM base address
412 hex "Kernel ROM Base"
415 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
416 range 0x20000000 0x30000000 if (BF54x || BF561)
417 range 0xB0000000 0xC0000000 if (BF60x)
419 Make sure your ROM base does not include any file-header
420 information that is prepended to the kernel.
422 For example, the bootable U-Boot format (created with
423 mkimage) has a 64 byte header (0x40). So while the image
424 you write to flash might start at say 0x20080000, you have
425 to add 0x40 to get the kernel's ROM base as it will come
428 comment "Clock/PLL Setup"
431 int "Frequency of the crystal on the board in Hz"
432 default "10000000" if BFIN532_IP0X
433 default "11059200" if BFIN533_STAMP
434 default "24576000" if PNAV10
435 default "25000000" # most people use this
436 default "27000000" if BFIN533_EZKIT
437 default "30000000" if BFIN561_EZKIT
438 default "24000000" if BFIN527_AD7160EVAL
440 The frequency of CLKIN crystal oscillator on the board in Hz.
441 Warning: This value should match the crystal on the board. Otherwise,
442 peripherals won't work properly.
444 config BFIN_KERNEL_CLOCK
445 bool "Re-program Clocks while Kernel boots?"
448 This option decides if kernel clocks are re-programed from the
449 bootloader settings. If the clocks are not set, the SDRAM settings
450 are also not changed, and the Bootloader does 100% of the hardware
455 depends on BFIN_KERNEL_CLOCK && (!BF60x)
460 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
463 If this is set the clock will be divided by 2, before it goes to the PLL.
467 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
469 default "22" if BFIN533_EZKIT
470 default "45" if BFIN533_STAMP
471 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
472 default "22" if BFIN533_BLUETECHNIX_CM
473 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
474 default "20" if (BFIN561_EZKIT || BF609)
475 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
476 default "25" if BFIN527_AD7160EVAL
478 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
479 PLL Frequency = (Crystal Frequency) * (this setting)
482 prompt "Core Clock Divider"
483 depends on BFIN_KERNEL_CLOCK
486 This sets the frequency of the core. It can be 1, 2, 4 or 8
487 Core Frequency = (PLL frequency) / (this setting)
503 int "System Clock Divider"
504 depends on BFIN_KERNEL_CLOCK
508 This sets the frequency of the system clock (including SDRAM or DDR) on
509 !BF60x else it set the clock for system buses and provides the
510 source from which SCLK0 and SCLK1 are derived.
511 This can be between 1 and 15
512 System Clock = (PLL frequency) / (this setting)
515 int "System Clock0 Divider"
516 depends on BFIN_KERNEL_CLOCK && BF60x
520 This sets the frequency of the system clock0 for PVP and all other
521 peripherals not clocked by SCLK1.
522 This can be between 1 and 15
523 System Clock0 = (System Clock) / (this setting)
526 int "System Clock1 Divider"
527 depends on BFIN_KERNEL_CLOCK && BF60x
531 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
532 This can be between 1 and 15
533 System Clock1 = (System Clock) / (this setting)
536 int "DDR Clock Divider"
537 depends on BFIN_KERNEL_CLOCK && BF60x
541 This sets the frequency of the DDR memory.
542 This can be between 1 and 15
543 DDR Clock = (PLL frequency) / (this setting)
546 prompt "DDR SDRAM Chip Type"
547 depends on BFIN_KERNEL_CLOCK
549 default MEM_MT46V32M16_5B
551 config MEM_MT46V32M16_6T
554 config MEM_MT46V32M16_5B
559 prompt "DDR/SDRAM Timing"
560 depends on BFIN_KERNEL_CLOCK && !BF60x
561 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
563 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
564 The calculated SDRAM timing parameters may not be 100%
565 accurate - This option is therefore marked experimental.
567 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
568 bool "Calculate Timings"
570 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
571 bool "Provide accurate Timings based on target SCLK"
573 Please consult the Blackfin Hardware Reference Manuals as well
574 as the memory device datasheet.
575 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
578 menu "Memory Init Control"
579 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
596 config MEM_EBIU_DDRQUE
613 # Max & Min Speeds for various Chips
617 default 400000000 if BF512
618 default 400000000 if BF514
619 default 400000000 if BF516
620 default 400000000 if BF518
621 default 400000000 if BF522
622 default 600000000 if BF523
623 default 400000000 if BF524
624 default 600000000 if BF525
625 default 400000000 if BF526
626 default 600000000 if BF527
627 default 400000000 if BF531
628 default 400000000 if BF532
629 default 750000000 if BF533
630 default 500000000 if BF534
631 default 400000000 if BF536
632 default 600000000 if BF537
633 default 533333333 if BF538
634 default 533333333 if BF539
635 default 600000000 if BF542
636 default 533333333 if BF544
637 default 600000000 if BF547
638 default 600000000 if BF548
639 default 533333333 if BF549
640 default 600000000 if BF561
641 default 800000000 if BF609
649 default 200000000 if BF609
656 comment "Kernel Timer/Scheduler"
658 source kernel/Kconfig.hz
660 config SET_GENERIC_CLOCKEVENTS
661 bool "Generic clock events"
663 select GENERIC_CLOCKEVENTS
665 menu "Clock event device"
666 depends on GENERIC_CLOCKEVENTS
667 config TICKSOURCE_GPTMR0
672 config TICKSOURCE_CORETMR
678 depends on GENERIC_CLOCKEVENTS
679 config CYCLES_CLOCKSOURCE
682 depends on !BFIN_SCRATCH_REG_CYCLES
685 If you say Y here, you will enable support for using the 'cycles'
686 registers as a clock source. Doing so means you will be unable to
687 safely write to the 'cycles' register during runtime. You will
688 still be able to read it (such as for performance monitoring), but
689 writing the registers will most likely crash the kernel.
691 config GPTMR0_CLOCKSOURCE
694 depends on !TICKSOURCE_GPTMR0
700 prompt "Blackfin Exception Scratch Register"
701 default BFIN_SCRATCH_REG_RETN
703 Select the resource to reserve for the Exception handler:
704 - RETN: Non-Maskable Interrupt (NMI)
705 - RETE: Exception Return (JTAG/ICE)
706 - CYCLES: Performance counter
708 If you are unsure, please select "RETN".
710 config BFIN_SCRATCH_REG_RETN
713 Use the RETN register in the Blackfin exception handler
714 as a stack scratch register. This means you cannot
715 safely use NMI on the Blackfin while running Linux, but
716 you can debug the system with a JTAG ICE and use the
717 CYCLES performance registers.
719 If you are unsure, please select "RETN".
721 config BFIN_SCRATCH_REG_RETE
724 Use the RETE register in the Blackfin exception handler
725 as a stack scratch register. This means you cannot
726 safely use a JTAG ICE while debugging a Blackfin board,
727 but you can safely use the CYCLES performance registers
730 If you are unsure, please select "RETN".
732 config BFIN_SCRATCH_REG_CYCLES
735 Use the CYCLES register in the Blackfin exception handler
736 as a stack scratch register. This means you cannot
737 safely use the CYCLES performance registers on a Blackfin
738 board at anytime, but you can debug the system with a JTAG
741 If you are unsure, please select "RETN".
748 menu "Blackfin Kernel Optimizations"
750 comment "Memory Optimizations"
753 bool "Locate interrupt entry code in L1 Memory"
757 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
758 into L1 instruction memory. (less latency)
760 config EXCPT_IRQ_SYSC_L1
761 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
765 If enabled, the entire ASM lowlevel exception and interrupt entry code
766 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
770 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
774 If enabled, the frequently called do_irq dispatcher function is linked
775 into L1 instruction memory. (less latency)
777 config CORE_TIMER_IRQ_L1
778 bool "Locate frequently called timer_interrupt() function in L1 Memory"
782 If enabled, the frequently called timer_interrupt() function is linked
783 into L1 instruction memory. (less latency)
786 bool "Locate frequently idle function in L1 Memory"
790 If enabled, the frequently called idle function is linked
791 into L1 instruction memory. (less latency)
794 bool "Locate kernel schedule function in L1 Memory"
798 If enabled, the frequently called kernel schedule is linked
799 into L1 instruction memory. (less latency)
801 config ARITHMETIC_OPS_L1
802 bool "Locate kernel owned arithmetic functions in L1 Memory"
806 If enabled, arithmetic functions are linked
807 into L1 instruction memory. (less latency)
810 bool "Locate access_ok function in L1 Memory"
814 If enabled, the access_ok function is linked
815 into L1 instruction memory. (less latency)
818 bool "Locate memset function in L1 Memory"
822 If enabled, the memset function is linked
823 into L1 instruction memory. (less latency)
826 bool "Locate memcpy function in L1 Memory"
830 If enabled, the memcpy function is linked
831 into L1 instruction memory. (less latency)
834 bool "locate strcmp function in L1 Memory"
838 If enabled, the strcmp function is linked
839 into L1 instruction memory (less latency).
842 bool "locate strncmp function in L1 Memory"
846 If enabled, the strncmp function is linked
847 into L1 instruction memory (less latency).
850 bool "locate strcpy function in L1 Memory"
854 If enabled, the strcpy function is linked
855 into L1 instruction memory (less latency).
858 bool "locate strncpy function in L1 Memory"
862 If enabled, the strncpy function is linked
863 into L1 instruction memory (less latency).
865 config SYS_BFIN_SPINLOCK_L1
866 bool "Locate sys_bfin_spinlock function in L1 Memory"
870 If enabled, sys_bfin_spinlock function is linked
871 into L1 instruction memory. (less latency)
873 config CACHELINE_ALIGNED_L1
874 bool "Locate cacheline_aligned data to L1 Data Memory"
877 depends on !SMP && !BF531 && !CRC32
879 If enabled, cacheline_aligned data is linked
880 into L1 data memory. (less latency)
882 config SYSCALL_TAB_L1
883 bool "Locate Syscall Table L1 Data Memory"
885 depends on !SMP && !BF531
887 If enabled, the Syscall LUT is linked
888 into L1 data memory. (less latency)
890 config CPLB_SWITCH_TAB_L1
891 bool "Locate CPLB Switch Tables L1 Data Memory"
893 depends on !SMP && !BF531
895 If enabled, the CPLB Switch Tables are linked
896 into L1 data memory. (less latency)
898 config ICACHE_FLUSH_L1
899 bool "Locate icache flush funcs in L1 Inst Memory"
902 If enabled, the Blackfin icache flushing functions are linked
903 into L1 instruction memory.
905 Note that this might be required to address anomalies, but
906 these functions are pretty small, so it shouldn't be too bad.
907 If you are using a processor affected by an anomaly, the build
908 system will double check for you and prevent it.
910 config DCACHE_FLUSH_L1
911 bool "Locate dcache flush funcs in L1 Inst Memory"
915 If enabled, the Blackfin dcache flushing functions are linked
916 into L1 instruction memory.
919 bool "Support locating application stack in L1 Scratch Memory"
923 If enabled the application stack can be located in L1
924 scratch memory (less latency).
926 Currently only works with FLAT binaries.
928 config EXCEPTION_L1_SCRATCH
929 bool "Locate exception stack in L1 Scratch Memory"
931 depends on !SMP && !APP_STACK_L1
933 Whenever an exception occurs, use the L1 Scratch memory for
934 stack storage. You cannot place the stacks of FLAT binaries
935 in L1 when using this option.
937 If you don't use L1 Scratch, then you should say Y here.
939 comment "Speed Optimizations"
940 config BFIN_INS_LOWOVERHEAD
941 bool "ins[bwl] low overhead, higher interrupt latency"
945 Reads on the Blackfin are speculative. In Blackfin terms, this means
946 they can be interrupted at any time (even after they have been issued
947 on to the external bus), and re-issued after the interrupt occurs.
948 For memory - this is not a big deal, since memory does not change if
951 If a FIFO is sitting on the end of the read, it will see two reads,
952 when the core only sees one since the FIFO receives both the read
953 which is cancelled (and not delivered to the core) and the one which
954 is re-issued (which is delivered to the core).
956 To solve this, interrupts are turned off before reads occur to
957 I/O space. This option controls which the overhead/latency of
958 controlling interrupts during this time
959 "n" turns interrupts off every read
960 (higher overhead, but lower interrupt latency)
961 "y" turns interrupts off every loop
962 (low overhead, but longer interrupt latency)
964 default behavior is to leave this set to on (type "Y"). If you are experiencing
965 interrupt latency issues, it is safe and OK to turn this off.
970 prompt "Kernel executes from"
972 Choose the memory type that the kernel will be running in.
977 The kernel will be resident in RAM when running.
982 The kernel will be resident in FLASH/ROM when running.
986 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
995 tristate "Enable Blackfin General Purpose Timers API"
998 Enable support for the General Purpose Timers API. If you
1001 To compile this driver as a module, choose M here: the module
1002 will be called gptimers.
1005 prompt "Uncached DMA region"
1006 default DMA_UNCACHED_1M
1007 config DMA_UNCACHED_32M
1008 bool "Enable 32M DMA region"
1009 config DMA_UNCACHED_16M
1010 bool "Enable 16M DMA region"
1011 config DMA_UNCACHED_8M
1012 bool "Enable 8M DMA region"
1013 config DMA_UNCACHED_4M
1014 bool "Enable 4M DMA region"
1015 config DMA_UNCACHED_2M
1016 bool "Enable 2M DMA region"
1017 config DMA_UNCACHED_1M
1018 bool "Enable 1M DMA region"
1019 config DMA_UNCACHED_512K
1020 bool "Enable 512K DMA region"
1021 config DMA_UNCACHED_256K
1022 bool "Enable 256K DMA region"
1023 config DMA_UNCACHED_128K
1024 bool "Enable 128K DMA region"
1025 config DMA_UNCACHED_NONE
1026 bool "Disable DMA region"
1030 comment "Cache Support"
1033 bool "Enable ICACHE"
1035 config BFIN_EXTMEM_ICACHEABLE
1036 bool "Enable ICACHE for external memory"
1037 depends on BFIN_ICACHE
1039 config BFIN_L2_ICACHEABLE
1040 bool "Enable ICACHE for L2 SRAM"
1041 depends on BFIN_ICACHE
1042 depends on (BF54x || BF561 || BF60x) && !SMP
1046 bool "Enable DCACHE"
1048 config BFIN_DCACHE_BANKA
1049 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1050 depends on BFIN_DCACHE && !BF531
1052 config BFIN_EXTMEM_DCACHEABLE
1053 bool "Enable DCACHE for external memory"
1054 depends on BFIN_DCACHE
1057 prompt "External memory DCACHE policy"
1058 depends on BFIN_EXTMEM_DCACHEABLE
1059 default BFIN_EXTMEM_WRITEBACK if !SMP
1060 default BFIN_EXTMEM_WRITETHROUGH if SMP
1061 config BFIN_EXTMEM_WRITEBACK
1066 Cached data will be written back to SDRAM only when needed.
1067 This can give a nice increase in performance, but beware of
1068 broken drivers that do not properly invalidate/flush their
1071 Write Through Policy:
1072 Cached data will always be written back to SDRAM when the
1073 cache is updated. This is a completely safe setting, but
1074 performance is worse than Write Back.
1076 If you are unsure of the options and you want to be safe,
1077 then go with Write Through.
1079 config BFIN_EXTMEM_WRITETHROUGH
1080 bool "Write through"
1083 Cached data will be written back to SDRAM only when needed.
1084 This can give a nice increase in performance, but beware of
1085 broken drivers that do not properly invalidate/flush their
1088 Write Through Policy:
1089 Cached data will always be written back to SDRAM when the
1090 cache is updated. This is a completely safe setting, but
1091 performance is worse than Write Back.
1093 If you are unsure of the options and you want to be safe,
1094 then go with Write Through.
1098 config BFIN_L2_DCACHEABLE
1099 bool "Enable DCACHE for L2 SRAM"
1100 depends on BFIN_DCACHE
1101 depends on (BF54x || BF561 || BF60x) && !SMP
1104 prompt "L2 SRAM DCACHE policy"
1105 depends on BFIN_L2_DCACHEABLE
1106 default BFIN_L2_WRITEBACK
1107 config BFIN_L2_WRITEBACK
1110 config BFIN_L2_WRITETHROUGH
1111 bool "Write through"
1115 comment "Memory Protection Unit"
1117 bool "Enable the memory protection unit"
1120 Use the processor's MPU to protect applications from accessing
1121 memory they do not own. This comes at a performance penalty
1122 and is recommended only for debugging.
1124 comment "Asynchronous Memory Configuration"
1126 menu "EBIU_AMGCTL Global Control"
1129 bool "Enable CLKOUT"
1133 bool "DMA has priority over core for ext. accesses"
1138 bool "Bank 0 16 bit packing enable"
1143 bool "Bank 1 16 bit packing enable"
1148 bool "Bank 2 16 bit packing enable"
1153 bool "Bank 3 16 bit packing enable"
1157 prompt "Enable Asynchronous Memory Banks"
1161 bool "Disable All Banks"
1164 bool "Enable Bank 0"
1166 config C_AMBEN_B0_B1
1167 bool "Enable Bank 0 & 1"
1169 config C_AMBEN_B0_B1_B2
1170 bool "Enable Bank 0 & 1 & 2"
1173 bool "Enable All Banks"
1177 menu "EBIU_AMBCTL Control"
1180 hex "Bank 0 (AMBCTL0.L)"
1183 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1184 used to control the Asynchronous Memory Bank 0 settings.
1187 hex "Bank 1 (AMBCTL0.H)"
1189 default 0x5558 if BF54x
1191 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1192 used to control the Asynchronous Memory Bank 1 settings.
1195 hex "Bank 2 (AMBCTL1.L)"
1198 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1199 used to control the Asynchronous Memory Bank 2 settings.
1202 hex "Bank 3 (AMBCTL1.H)"
1205 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1206 used to control the Asynchronous Memory Bank 3 settings.
1210 config EBIU_MBSCTLVAL
1211 hex "EBIU Bank Select Control Register"
1216 hex "Flash Memory Mode Control Register"
1221 hex "Flash Memory Bank Control Register"
1226 #############################################################################
1227 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1233 Support for PCI bus.
1235 source "drivers/pci/Kconfig"
1237 source "drivers/pcmcia/Kconfig"
1241 menu "Executable file formats"
1243 source "fs/Kconfig.binfmt"
1247 menu "Power management options"
1249 source "kernel/power/Kconfig"
1251 config ARCH_SUSPEND_POSSIBLE
1255 prompt "Standby Power Saving Mode"
1256 depends on PM && !BF60x
1257 default PM_BFIN_SLEEP_DEEPER
1258 config PM_BFIN_SLEEP_DEEPER
1261 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1262 power dissipation by disabling the clock to the processor core (CCLK).
1263 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1264 to 0.85 V to provide the greatest power savings, while preserving the
1266 The PLL and system clock (SCLK) continue to operate at a very low
1267 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1268 the SDRAM is put into Self Refresh Mode. Typically an external event
1269 such as GPIO interrupt or RTC activity wakes up the processor.
1270 Various Peripherals such as UART, SPORT, PPI may not function as
1271 normal during Sleep Deeper, due to the reduced SCLK frequency.
1272 When in the sleep mode, system DMA access to L1 memory is not supported.
1274 If unsure, select "Sleep Deeper".
1276 config PM_BFIN_SLEEP
1279 Sleep Mode (High Power Savings) - The sleep mode reduces power
1280 dissipation by disabling the clock to the processor core (CCLK).
1281 The PLL and system clock (SCLK), however, continue to operate in
1282 this mode. Typically an external event or RTC activity will wake
1283 up the processor. When in the sleep mode, system DMA access to L1
1284 memory is not supported.
1286 If unsure, select "Sleep Deeper".
1289 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1292 config PM_BFIN_WAKE_PH6
1293 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1294 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1297 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1299 config PM_BFIN_WAKE_GP
1300 bool "Allow Wake-Up from GPIOs"
1301 depends on PM && BF54x
1304 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1305 (all processors, except ADSP-BF549). This option sets
1306 the general-purpose wake-up enable (GPWE) control bit to enable
1307 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1308 On ADSP-BF549 this option enables the same functionality on the
1309 /MRXON pin also PH7.
1311 config PM_BFIN_WAKE_PA15
1312 bool "Allow Wake-Up from PA15"
1313 depends on PM && BF60x
1318 config PM_BFIN_WAKE_PA15_POL
1319 int "Wake-up priority"
1320 depends on PM_BFIN_WAKE_PA15
1323 Wake-Up priority 0(low) 1(high)
1325 config PM_BFIN_WAKE_PB15
1326 bool "Allow Wake-Up from PB15"
1327 depends on PM && BF60x
1332 config PM_BFIN_WAKE_PB15_POL
1333 int "Wake-up priority"
1334 depends on PM_BFIN_WAKE_PB15
1337 Wake-Up priority 0(low) 1(high)
1339 config PM_BFIN_WAKE_PC15
1340 bool "Allow Wake-Up from PC15"
1341 depends on PM && BF60x
1346 config PM_BFIN_WAKE_PC15_POL
1347 int "Wake-up priority"
1348 depends on PM_BFIN_WAKE_PC15
1351 Wake-Up priority 0(low) 1(high)
1353 config PM_BFIN_WAKE_PD06
1354 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1355 depends on PM && BF60x
1358 Enable PD06(ETH0_PHYINT) Wake-up
1360 config PM_BFIN_WAKE_PD06_POL
1361 int "Wake-up priority"
1362 depends on PM_BFIN_WAKE_PD06
1365 Wake-Up priority 0(low) 1(high)
1367 config PM_BFIN_WAKE_PE12
1368 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1369 depends on PM && BF60x
1372 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1374 config PM_BFIN_WAKE_PE12_POL
1375 int "Wake-up priority"
1376 depends on PM_BFIN_WAKE_PE12
1379 Wake-Up priority 0(low) 1(high)
1381 config PM_BFIN_WAKE_PG04
1382 bool "Allow Wake-Up from PG04(CAN0_RX)"
1383 depends on PM && BF60x
1386 Enable PG04(CAN0_RX) Wake-up
1388 config PM_BFIN_WAKE_PG04_POL
1389 int "Wake-up priority"
1390 depends on PM_BFIN_WAKE_PG04
1393 Wake-Up priority 0(low) 1(high)
1395 config PM_BFIN_WAKE_PG13
1396 bool "Allow Wake-Up from PG13"
1397 depends on PM && BF60x
1402 config PM_BFIN_WAKE_PG13_POL
1403 int "Wake-up priority"
1404 depends on PM_BFIN_WAKE_PG13
1407 Wake-Up priority 0(low) 1(high)
1409 config PM_BFIN_WAKE_USB
1410 bool "Allow Wake-Up from (USB)"
1411 depends on PM && BF60x
1414 Enable (USB) Wake-up
1416 config PM_BFIN_WAKE_USB_POL
1417 int "Wake-up priority"
1418 depends on PM_BFIN_WAKE_USB
1421 Wake-Up priority 0(low) 1(high)
1425 menu "CPU Frequency scaling"
1427 source "drivers/cpufreq/Kconfig"
1429 config BFIN_CPU_FREQ
1435 bool "CPU Voltage scaling"
1439 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1440 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1441 manuals. There is a theoretical risk that during VDDINT transitions
1446 source "net/Kconfig"
1448 source "drivers/Kconfig"
1450 source "drivers/firmware/Kconfig"
1454 source "arch/blackfin/Kconfig.debug"
1456 source "security/Kconfig"
1458 source "crypto/Kconfig"
1460 source "lib/Kconfig"