1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/mm/proc.S
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
10 #include <linux/init.h>
11 #include <linux/linkage.h>
12 #include <linux/pgtable.h>
13 #include <asm/assembler.h>
14 #include <asm/asm-offsets.h>
15 #include <asm/asm_pointer_auth.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/cpufeature.h>
19 #include <asm/alternative.h>
21 #include <asm/sysreg.h>
23 #ifdef CONFIG_ARM64_64K_PAGES
24 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
25 #elif defined(CONFIG_ARM64_16K_PAGES)
26 #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
27 #else /* CONFIG_ARM64_4K_PAGES */
28 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
31 #ifdef CONFIG_RANDOMIZE_BASE
32 #define TCR_KASLR_FLAGS TCR_NFD1
34 #define TCR_KASLR_FLAGS 0
37 #define TCR_SMP_FLAGS TCR_SHARED
39 /* PTWs cacheable, inner/outer WBWA */
40 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
42 #ifdef CONFIG_KASAN_SW_TAGS
43 #define TCR_KASAN_FLAGS TCR_TBI1 | TCR_TBID1
45 #define TCR_KASAN_FLAGS 0
49 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
50 * changed during __cpu_setup to Normal Tagged if the system supports MTE.
52 #define MAIR_EL1_SET \
53 (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \
54 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \
55 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \
56 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \
57 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \
58 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \
59 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
63 * cpu_do_suspend - save CPU registers context
65 * x0: virtual address of context pointer
67 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
69 SYM_FUNC_START(cpu_do_suspend)
72 mrs x4, contextidr_el1
80 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
90 stp x10, x11, [x0, #64]
91 stp x12, x13, [x0, #80]
93 * Save x18 as it may be used as a platform register, e.g. by shadow
98 SYM_FUNC_END(cpu_do_suspend)
101 * cpu_do_resume - restore CPU register context
103 * x0: Address of context pointer
105 .pushsection ".idmap.text", "awx"
106 SYM_FUNC_START(cpu_do_resume)
108 ldp x4, x5, [x0, #16]
109 ldp x6, x8, [x0, #32]
110 ldp x9, x10, [x0, #48]
111 ldp x11, x12, [x0, #64]
112 ldp x13, x14, [x0, #80]
114 * Restore x18, as it may be used as a platform register, and clear
115 * the buffer to minimize the risk of exposure when used for shadow
122 msr contextidr_el1, x4
125 /* Don't change t0sz here, mask those bits when restoring */
127 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
133 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
134 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
135 * exception. Mask them until local_daif_restore() in cpu_suspend()
142 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
149 * Restore oslsr_el1 by writing oslar_el1
152 ubfx x11, x11, #1, #1
154 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
155 reset_amuserenr_el0 x0 // Disable AMU access from EL0
157 alternative_if ARM64_HAS_RAS_EXTN
158 msr_s SYS_DISR_EL1, xzr
159 alternative_else_nop_endif
161 ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
164 SYM_FUNC_END(cpu_do_resume)
168 .pushsection ".idmap.text", "awx"
170 .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
171 adrp \tmp1, reserved_pg_dir
172 phys_to_ttbr \tmp2, \tmp1
173 offset_ttbr1 \tmp2, \tmp1
182 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
184 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
185 * called by anything else. It can only be executed from a TTBR0 mapping.
187 SYM_FUNC_START(idmap_cpu_replace_ttbr1)
188 save_and_disable_daif flags=x2
190 __idmap_cpu_set_reserved_ttbr1 x1, x3
199 SYM_FUNC_END(idmap_cpu_replace_ttbr1)
202 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
203 .pushsection ".idmap.text", "awx"
205 .macro __idmap_kpti_get_pgtable_ent, type
206 dc cvac, cur_\()\type\()p // Ensure any existing dirty
207 dmb sy // lines are written back before
208 ldr \type, [cur_\()\type\()p] // loading the entry
209 tbz \type, #0, skip_\()\type // Skip invalid and
210 tbnz \type, #11, skip_\()\type // non-global entries
213 .macro __idmap_kpti_put_pgtable_ent_ng, type
214 orr \type, \type, #PTE_NG // Same bit for blocks and pages
215 str \type, [cur_\()\type\()p] // Update the entry and ensure
216 dmb sy // that it is visible to all
217 dc civac, cur_\()\type\()p // CPUs.
221 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
223 * Called exactly once from stop_machine context by each CPU found during boot.
227 SYM_FUNC_START(idmap_kpti_install_ng_mappings)
246 mrs swapper_ttb, ttbr1_el1
247 restore_ttbr1 swapper_ttb
248 adr flag_ptr, __idmap_kpti_flag
250 cbnz cpu, __idmap_kpti_secondary
252 /* We're the boot CPU. Wait for the others to catch up */
255 ldaxr w17, [flag_ptr]
256 eor w17, w17, num_cpus
259 /* We need to walk swapper, so turn off the MMU. */
260 pre_disable_mmu_workaround
262 bic x17, x17, #SCTLR_ELx_M
266 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
268 mov cur_pgdp, swapper_pa
269 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
270 do_pgd: __idmap_kpti_get_pgtable_ent pgd
271 tbnz pgd, #1, walk_puds
273 __idmap_kpti_put_pgtable_ent_ng pgd
275 add cur_pgdp, cur_pgdp, #8
276 cmp cur_pgdp, end_pgdp
279 /* Publish the updated tables and nuke all the TLBs */
285 /* We're done: fire up the MMU again */
287 orr x17, x17, #SCTLR_ELx_M
292 * Invalidate the local I-cache so that any instructions fetched
293 * speculatively from the PoC are discarded, since they may have
294 * been dynamically patched at the PoU.
300 /* Set the flag to zero to indicate that we're all done */
306 .if CONFIG_PGTABLE_LEVELS > 3
307 pte_to_phys cur_pudp, pgd
308 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
309 do_pud: __idmap_kpti_get_pgtable_ent pud
310 tbnz pud, #1, walk_pmds
312 __idmap_kpti_put_pgtable_ent_ng pud
314 add cur_pudp, cur_pudp, 8
315 cmp cur_pudp, end_pudp
318 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
327 .if CONFIG_PGTABLE_LEVELS > 2
328 pte_to_phys cur_pmdp, pud
329 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
330 do_pmd: __idmap_kpti_get_pgtable_ent pmd
331 tbnz pmd, #1, walk_ptes
333 __idmap_kpti_put_pgtable_ent_ng pmd
335 add cur_pmdp, cur_pmdp, #8
336 cmp cur_pmdp, end_pmdp
339 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
348 pte_to_phys cur_ptep, pmd
349 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
350 do_pte: __idmap_kpti_get_pgtable_ent pte
351 __idmap_kpti_put_pgtable_ent_ng pte
353 add cur_ptep, cur_ptep, #8
354 cmp cur_ptep, end_ptep
374 /* Secondary CPUs end up here */
375 __idmap_kpti_secondary:
376 /* Uninstall swapper before surgery begins */
377 __idmap_cpu_set_reserved_ttbr1 x16, x17
379 /* Increment the flag to let the boot CPU we're ready */
380 1: ldxr w16, [flag_ptr]
382 stxr w17, w16, [flag_ptr]
385 /* Wait for the boot CPU to finish messing around with swapper */
391 /* All done, act like nothing happened */
392 offset_ttbr1 swapper_ttb, x16
393 msr ttbr1_el1, swapper_ttb
399 SYM_FUNC_END(idmap_kpti_install_ng_mappings)
406 * Initialise the processor for turning the MMU on.
409 * Return in x0 the value of the SCTLR_EL1 register.
411 .pushsection ".idmap.text", "awx"
412 SYM_FUNC_START(__cpu_setup)
413 tlbi vmalle1 // Invalidate local TLB
417 msr cpacr_el1, x1 // Enable FP/ASIMD
418 mov x1, #1 << 12 // Reset mdscr_el1 and disable
419 msr mdscr_el1, x1 // access to the DCC from EL0
420 isb // Unmask debug exceptions now,
421 enable_dbg // since this is per-cpu
422 reset_pmuserenr_el0 x1 // Disable PMU access from EL0
423 reset_amuserenr_el0 x1 // Disable AMU access from EL0
426 * Memory region attributes
428 mov_q x5, MAIR_EL1_SET
429 #ifdef CONFIG_ARM64_MTE
431 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
432 * (ID_AA64PFR1_EL1[11:8] > 1).
434 mrs x10, ID_AA64PFR1_EL1
435 ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
436 cmp x10, #ID_AA64PFR1_MTE
439 /* Normal Tagged memory type at the corresponding MAIR index */
440 mov x10, #MAIR_ATTR_NORMAL_TAGGED
441 bfi x5, x10, #(8 * MT_NORMAL_TAGGED), #8
443 /* initialize GCR_EL1: all non-zero tags excluded by default */
444 mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)
445 msr_s SYS_GCR_EL1, x10
447 /* clear any pending tag check faults in TFSR*_EL1 */
448 msr_s SYS_TFSR_EL1, xzr
449 msr_s SYS_TFSRE0_EL1, xzr
454 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
455 * both user and kernel.
457 mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
458 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
459 TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
460 tcr_clear_errata_bits x10, x9, x5
462 #ifdef CONFIG_ARM64_VA_BITS_52
463 ldr_l x9, vabits_actual
473 * Set the IPS bits in TCR_EL1.
475 tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
476 #ifdef CONFIG_ARM64_HW_AFDBM
478 * Enable hardware update of the Access Flags bit.
479 * Hardware dirty bit management is enabled later,
482 mrs x9, ID_AA64MMFR1_EL1
485 orr x10, x10, #TCR_HA // hardware Access flag update
487 #endif /* CONFIG_ARM64_HW_AFDBM */
492 mov_q x0, INIT_SCTLR_EL1_MMU_ON
493 ret // return to head.S
494 SYM_FUNC_END(__cpu_setup)