1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
9 #include <linux/errno.h>
10 #include <linux/linkage.h>
11 #include <linux/init.h>
12 #include <asm/assembler.h>
13 #include <asm/cpufeature.h>
14 #include <asm/alternative.h>
15 #include <asm/asm-uaccess.h>
18 * caches_clean_inval_pou_macro(start,end) [fixup]
20 * Ensure that the I and D caches are coherent within specified region.
21 * This is typically used when code has been written to a memory region,
22 * and will be executed.
24 * - start - virtual start address of region
25 * - end - virtual end address of region
26 * - fixup - optional label to branch to on user fault
28 .macro caches_clean_inval_pou_macro, fixup
29 alternative_if ARM64_HAS_CACHE_IDC
32 alternative_else_nop_endif
35 dcache_by_line_op cvau, ish, x2, x3, x4, x5, \fixup
37 alternative_if ARM64_HAS_CACHE_DIC
40 alternative_else_nop_endif
41 invalidate_icache_by_line x0, x1, x2, x3, \fixup
46 * caches_clean_inval_pou(start,end)
48 * Ensure that the I and D caches are coherent within specified region.
49 * This is typically used when code has been written to a memory region,
50 * and will be executed.
52 * - start - virtual start address of region
53 * - end - virtual end address of region
55 SYM_FUNC_START(caches_clean_inval_pou)
56 caches_clean_inval_pou_macro
58 SYM_FUNC_END(caches_clean_inval_pou)
61 * caches_clean_inval_user_pou(start,end)
63 * Ensure that the I and D caches are coherent within specified region.
64 * This is typically used when code has been written to a memory region,
65 * and will be executed.
67 * - start - virtual start address of region
68 * - end - virtual end address of region
70 SYM_FUNC_START(caches_clean_inval_user_pou)
71 uaccess_ttbr0_enable x2, x3, x4
73 caches_clean_inval_pou_macro 2f
76 uaccess_ttbr0_disable x1, x2
81 SYM_FUNC_END(caches_clean_inval_user_pou)
84 * icache_inval_pou(start,end)
86 * Ensure that the I cache is invalid within specified region.
88 * - start - virtual start address of region
89 * - end - virtual end address of region
91 SYM_FUNC_START(icache_inval_pou)
92 alternative_if ARM64_HAS_CACHE_DIC
95 alternative_else_nop_endif
97 invalidate_icache_by_line x0, x1, x2, x3
99 SYM_FUNC_END(icache_inval_pou)
102 * dcache_clean_inval_poc(start, end)
104 * Ensure that any D-cache lines for the interval [start, end)
105 * are cleaned and invalidated to the PoC.
107 * - start - virtual start address of region
108 * - end - virtual end address of region
110 SYM_FUNC_START_PI(dcache_clean_inval_poc)
111 dcache_by_line_op civac, sy, x0, x1, x2, x3
113 SYM_FUNC_END_PI(dcache_clean_inval_poc)
116 * dcache_clean_pou(start, end)
118 * Ensure that any D-cache lines for the interval [start, end)
119 * are cleaned to the PoU.
121 * - start - virtual start address of region
122 * - end - virtual end address of region
124 SYM_FUNC_START(dcache_clean_pou)
125 alternative_if ARM64_HAS_CACHE_IDC
128 alternative_else_nop_endif
129 dcache_by_line_op cvau, ish, x0, x1, x2, x3
131 SYM_FUNC_END(dcache_clean_pou)
134 * dcache_inval_poc(start, end)
136 * Ensure that any D-cache lines for the interval [start, end)
137 * are invalidated. Any partial lines at the ends of the interval are
138 * also cleaned to PoC to prevent data loss.
140 * - start - kernel start address of region
141 * - end - kernel end address of region
143 SYM_FUNC_START_PI(dcache_inval_poc)
144 dcache_line_size x2, x3
146 tst x1, x3 // end cache line aligned?
149 dc civac, x1 // clean & invalidate D / U line
150 1: tst x0, x3 // start cache line aligned?
153 dc civac, x0 // clean & invalidate D / U line
155 2: dc ivac, x0 // invalidate D / U line
161 SYM_FUNC_END_PI(dcache_inval_poc)
164 * dcache_clean_poc(start, end)
166 * Ensure that any D-cache lines for the interval [start, end)
167 * are cleaned to the PoC.
169 * - start - virtual start address of region
170 * - end - virtual end address of region
172 SYM_FUNC_START_PI(dcache_clean_poc)
173 dcache_by_line_op cvac, sy, x0, x1, x2, x3
175 SYM_FUNC_END_PI(dcache_clean_poc)
178 * dcache_clean_pop(start, end)
180 * Ensure that any D-cache lines for the interval [start, end)
181 * are cleaned to the PoP.
183 * - start - virtual start address of region
184 * - end - virtual end address of region
186 SYM_FUNC_START_PI(dcache_clean_pop)
187 alternative_if_not ARM64_HAS_DCPOP
189 alternative_else_nop_endif
190 dcache_by_line_op cvap, sy, x0, x1, x2, x3
192 SYM_FUNC_END_PI(dcache_clean_pop)
195 * __dma_flush_area(start, size)
197 * clean & invalidate D / U line
199 * - start - virtual start address of region
200 * - size - size in question
202 SYM_FUNC_START_PI(__dma_flush_area)
204 dcache_by_line_op civac, sy, x0, x1, x2, x3
206 SYM_FUNC_END_PI(__dma_flush_area)
209 * __dma_map_area(start, size, dir)
210 * - start - kernel virtual start address
211 * - size - size of region
212 * - dir - DMA direction
214 SYM_FUNC_START_PI(__dma_map_area)
216 cmp w2, #DMA_FROM_DEVICE
217 b.eq __pi_dcache_inval_poc
218 b __pi_dcache_clean_poc
219 SYM_FUNC_END_PI(__dma_map_area)
222 * __dma_unmap_area(start, size, dir)
223 * - start - kernel virtual start address
224 * - size - size of region
225 * - dir - DMA direction
227 SYM_FUNC_START_PI(__dma_unmap_area)
229 cmp w2, #DMA_TO_DEVICE
230 b.ne __pi_dcache_inval_poc
232 SYM_FUNC_END_PI(__dma_unmap_area)