1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Huawei Ltd.
4 * Author: Jiang Liu <liuj97@gmail.com>
6 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
8 #include <linux/bitops.h>
10 #include <linux/printk.h>
11 #include <linux/sizes.h>
12 #include <linux/types.h>
14 #include <asm/debug-monitors.h>
15 #include <asm/errno.h>
17 #include <asm/kprobes.h>
19 #define AARCH64_INSN_SF_BIT BIT(31)
20 #define AARCH64_INSN_N_BIT BIT(22)
21 #define AARCH64_INSN_LSL_12 BIT(22)
23 static const int aarch64_insn_encoding_class[] = {
24 AARCH64_INSN_CLS_UNKNOWN,
25 AARCH64_INSN_CLS_UNKNOWN,
27 AARCH64_INSN_CLS_UNKNOWN,
28 AARCH64_INSN_CLS_LDST,
29 AARCH64_INSN_CLS_DP_REG,
30 AARCH64_INSN_CLS_LDST,
31 AARCH64_INSN_CLS_DP_FPSIMD,
32 AARCH64_INSN_CLS_DP_IMM,
33 AARCH64_INSN_CLS_DP_IMM,
34 AARCH64_INSN_CLS_BR_SYS,
35 AARCH64_INSN_CLS_BR_SYS,
36 AARCH64_INSN_CLS_LDST,
37 AARCH64_INSN_CLS_DP_REG,
38 AARCH64_INSN_CLS_LDST,
39 AARCH64_INSN_CLS_DP_FPSIMD,
42 enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
44 return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
47 bool __kprobes aarch64_insn_is_steppable_hint(u32 insn)
49 if (!aarch64_insn_is_hint(insn))
52 switch (insn & 0xFE0) {
53 case AARCH64_INSN_HINT_XPACLRI:
54 case AARCH64_INSN_HINT_PACIA_1716:
55 case AARCH64_INSN_HINT_PACIB_1716:
56 case AARCH64_INSN_HINT_PACIAZ:
57 case AARCH64_INSN_HINT_PACIASP:
58 case AARCH64_INSN_HINT_PACIBZ:
59 case AARCH64_INSN_HINT_PACIBSP:
60 case AARCH64_INSN_HINT_BTI:
61 case AARCH64_INSN_HINT_BTIC:
62 case AARCH64_INSN_HINT_BTIJ:
63 case AARCH64_INSN_HINT_BTIJC:
64 case AARCH64_INSN_HINT_NOP:
71 bool aarch64_insn_is_branch_imm(u32 insn)
73 return (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn) ||
74 aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn) ||
75 aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
76 aarch64_insn_is_bcond(insn));
79 bool __kprobes aarch64_insn_uses_literal(u32 insn)
81 /* ldr/ldrsw (literal), prfm */
83 return aarch64_insn_is_ldr_lit(insn) ||
84 aarch64_insn_is_ldrsw_lit(insn) ||
85 aarch64_insn_is_adr_adrp(insn) ||
86 aarch64_insn_is_prfm_lit(insn);
89 bool __kprobes aarch64_insn_is_branch(u32 insn)
91 /* b, bl, cb*, tb*, ret*, b.cond, br*, blr* */
93 return aarch64_insn_is_b(insn) ||
94 aarch64_insn_is_bl(insn) ||
95 aarch64_insn_is_cbz(insn) ||
96 aarch64_insn_is_cbnz(insn) ||
97 aarch64_insn_is_tbz(insn) ||
98 aarch64_insn_is_tbnz(insn) ||
99 aarch64_insn_is_ret(insn) ||
100 aarch64_insn_is_ret_auth(insn) ||
101 aarch64_insn_is_br(insn) ||
102 aarch64_insn_is_br_auth(insn) ||
103 aarch64_insn_is_blr(insn) ||
104 aarch64_insn_is_blr_auth(insn) ||
105 aarch64_insn_is_bcond(insn);
108 static int __kprobes aarch64_get_imm_shift_mask(enum aarch64_insn_imm_type type,
109 u32 *maskp, int *shiftp)
115 case AARCH64_INSN_IMM_26:
119 case AARCH64_INSN_IMM_19:
123 case AARCH64_INSN_IMM_16:
127 case AARCH64_INSN_IMM_14:
131 case AARCH64_INSN_IMM_12:
135 case AARCH64_INSN_IMM_9:
139 case AARCH64_INSN_IMM_7:
143 case AARCH64_INSN_IMM_6:
144 case AARCH64_INSN_IMM_S:
148 case AARCH64_INSN_IMM_R:
152 case AARCH64_INSN_IMM_N:
166 #define ADR_IMM_HILOSPLIT 2
167 #define ADR_IMM_SIZE SZ_2M
168 #define ADR_IMM_LOMASK ((1 << ADR_IMM_HILOSPLIT) - 1)
169 #define ADR_IMM_HIMASK ((ADR_IMM_SIZE >> ADR_IMM_HILOSPLIT) - 1)
170 #define ADR_IMM_LOSHIFT 29
171 #define ADR_IMM_HISHIFT 5
173 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn)
175 u32 immlo, immhi, mask;
179 case AARCH64_INSN_IMM_ADR:
181 immlo = (insn >> ADR_IMM_LOSHIFT) & ADR_IMM_LOMASK;
182 immhi = (insn >> ADR_IMM_HISHIFT) & ADR_IMM_HIMASK;
183 insn = (immhi << ADR_IMM_HILOSPLIT) | immlo;
184 mask = ADR_IMM_SIZE - 1;
187 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
188 pr_err("aarch64_insn_decode_immediate: unknown immediate encoding %d\n",
194 return (insn >> shift) & mask;
197 u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
200 u32 immlo, immhi, mask;
203 if (insn == AARCH64_BREAK_FAULT)
204 return AARCH64_BREAK_FAULT;
207 case AARCH64_INSN_IMM_ADR:
209 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT;
210 imm >>= ADR_IMM_HILOSPLIT;
211 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT;
213 mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) |
214 (ADR_IMM_HIMASK << ADR_IMM_HISHIFT));
217 if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) {
218 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
220 return AARCH64_BREAK_FAULT;
224 /* Update the immediate field. */
225 insn &= ~(mask << shift);
226 insn |= (imm & mask) << shift;
231 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
237 case AARCH64_INSN_REGTYPE_RT:
238 case AARCH64_INSN_REGTYPE_RD:
241 case AARCH64_INSN_REGTYPE_RN:
244 case AARCH64_INSN_REGTYPE_RT2:
245 case AARCH64_INSN_REGTYPE_RA:
248 case AARCH64_INSN_REGTYPE_RM:
252 pr_err("%s: unknown register type encoding %d\n", __func__,
257 return (insn >> shift) & GENMASK(4, 0);
260 static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
262 enum aarch64_insn_register reg)
266 if (insn == AARCH64_BREAK_FAULT)
267 return AARCH64_BREAK_FAULT;
269 if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) {
270 pr_err("%s: unknown register encoding %d\n", __func__, reg);
271 return AARCH64_BREAK_FAULT;
275 case AARCH64_INSN_REGTYPE_RT:
276 case AARCH64_INSN_REGTYPE_RD:
279 case AARCH64_INSN_REGTYPE_RN:
282 case AARCH64_INSN_REGTYPE_RT2:
283 case AARCH64_INSN_REGTYPE_RA:
286 case AARCH64_INSN_REGTYPE_RM:
287 case AARCH64_INSN_REGTYPE_RS:
291 pr_err("%s: unknown register type encoding %d\n", __func__,
293 return AARCH64_BREAK_FAULT;
296 insn &= ~(GENMASK(4, 0) << shift);
297 insn |= reg << shift;
302 static u32 aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type,
308 case AARCH64_INSN_SIZE_8:
311 case AARCH64_INSN_SIZE_16:
314 case AARCH64_INSN_SIZE_32:
317 case AARCH64_INSN_SIZE_64:
321 pr_err("%s: unknown size encoding %d\n", __func__, type);
322 return AARCH64_BREAK_FAULT;
325 insn &= ~GENMASK(31, 30);
331 static inline long branch_imm_common(unsigned long pc, unsigned long addr,
336 if ((pc & 0x3) || (addr & 0x3)) {
337 pr_err("%s: A64 instructions must be word aligned\n", __func__);
341 offset = ((long)addr - (long)pc);
343 if (offset < -range || offset >= range) {
344 pr_err("%s: offset out of range\n", __func__);
351 u32 __kprobes aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
352 enum aarch64_insn_branch_type type)
358 * B/BL support [-128M, 128M) offset
359 * ARM64 virtual address arrangement guarantees all kernel and module
360 * texts are within +/-128M.
362 offset = branch_imm_common(pc, addr, SZ_128M);
363 if (offset >= SZ_128M)
364 return AARCH64_BREAK_FAULT;
367 case AARCH64_INSN_BRANCH_LINK:
368 insn = aarch64_insn_get_bl_value();
370 case AARCH64_INSN_BRANCH_NOLINK:
371 insn = aarch64_insn_get_b_value();
374 pr_err("%s: unknown branch encoding %d\n", __func__, type);
375 return AARCH64_BREAK_FAULT;
378 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
382 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
383 enum aarch64_insn_register reg,
384 enum aarch64_insn_variant variant,
385 enum aarch64_insn_branch_type type)
390 offset = branch_imm_common(pc, addr, SZ_1M);
392 return AARCH64_BREAK_FAULT;
395 case AARCH64_INSN_BRANCH_COMP_ZERO:
396 insn = aarch64_insn_get_cbz_value();
398 case AARCH64_INSN_BRANCH_COMP_NONZERO:
399 insn = aarch64_insn_get_cbnz_value();
402 pr_err("%s: unknown branch encoding %d\n", __func__, type);
403 return AARCH64_BREAK_FAULT;
407 case AARCH64_INSN_VARIANT_32BIT:
409 case AARCH64_INSN_VARIANT_64BIT:
410 insn |= AARCH64_INSN_SF_BIT;
413 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
414 return AARCH64_BREAK_FAULT;
417 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
419 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
423 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
424 enum aarch64_insn_condition cond)
429 offset = branch_imm_common(pc, addr, SZ_1M);
431 insn = aarch64_insn_get_bcond_value();
433 if (cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL) {
434 pr_err("%s: unknown condition encoding %d\n", __func__, cond);
435 return AARCH64_BREAK_FAULT;
439 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
443 u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)
445 return aarch64_insn_get_hint_value() | op;
448 u32 __kprobes aarch64_insn_gen_nop(void)
450 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
453 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
454 enum aarch64_insn_branch_type type)
459 case AARCH64_INSN_BRANCH_NOLINK:
460 insn = aarch64_insn_get_br_value();
462 case AARCH64_INSN_BRANCH_LINK:
463 insn = aarch64_insn_get_blr_value();
465 case AARCH64_INSN_BRANCH_RETURN:
466 insn = aarch64_insn_get_ret_value();
469 pr_err("%s: unknown branch encoding %d\n", __func__, type);
470 return AARCH64_BREAK_FAULT;
473 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg);
476 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
477 enum aarch64_insn_register base,
478 enum aarch64_insn_register offset,
479 enum aarch64_insn_size_type size,
480 enum aarch64_insn_ldst_type type)
485 case AARCH64_INSN_LDST_LOAD_REG_OFFSET:
486 insn = aarch64_insn_get_ldr_reg_value();
488 case AARCH64_INSN_LDST_STORE_REG_OFFSET:
489 insn = aarch64_insn_get_str_reg_value();
492 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
493 return AARCH64_BREAK_FAULT;
496 insn = aarch64_insn_encode_ldst_size(size, insn);
498 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg);
500 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
503 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
507 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
508 enum aarch64_insn_register reg2,
509 enum aarch64_insn_register base,
511 enum aarch64_insn_variant variant,
512 enum aarch64_insn_ldst_type type)
518 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX:
519 insn = aarch64_insn_get_ldp_pre_value();
521 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX:
522 insn = aarch64_insn_get_stp_pre_value();
524 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX:
525 insn = aarch64_insn_get_ldp_post_value();
527 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX:
528 insn = aarch64_insn_get_stp_post_value();
531 pr_err("%s: unknown load/store encoding %d\n", __func__, type);
532 return AARCH64_BREAK_FAULT;
536 case AARCH64_INSN_VARIANT_32BIT:
537 if ((offset & 0x3) || (offset < -256) || (offset > 252)) {
538 pr_err("%s: offset must be multiples of 4 in the range of [-256, 252] %d\n",
540 return AARCH64_BREAK_FAULT;
544 case AARCH64_INSN_VARIANT_64BIT:
545 if ((offset & 0x7) || (offset < -512) || (offset > 504)) {
546 pr_err("%s: offset must be multiples of 8 in the range of [-512, 504] %d\n",
548 return AARCH64_BREAK_FAULT;
551 insn |= AARCH64_INSN_SF_BIT;
554 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
555 return AARCH64_BREAK_FAULT;
558 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
561 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
564 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
567 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7, insn,
571 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
572 enum aarch64_insn_register base,
573 enum aarch64_insn_register state,
574 enum aarch64_insn_size_type size,
575 enum aarch64_insn_ldst_type type)
580 case AARCH64_INSN_LDST_LOAD_EX:
581 insn = aarch64_insn_get_load_ex_value();
583 case AARCH64_INSN_LDST_STORE_EX:
584 insn = aarch64_insn_get_store_ex_value();
587 pr_err("%s: unknown load/store exclusive encoding %d\n", __func__, type);
588 return AARCH64_BREAK_FAULT;
591 insn = aarch64_insn_encode_ldst_size(size, insn);
593 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
596 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
599 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2, insn,
600 AARCH64_INSN_REG_ZR);
602 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
606 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
607 enum aarch64_insn_register address,
608 enum aarch64_insn_register value,
609 enum aarch64_insn_size_type size)
611 u32 insn = aarch64_insn_get_ldadd_value();
614 case AARCH64_INSN_SIZE_32:
615 case AARCH64_INSN_SIZE_64:
618 pr_err("%s: unimplemented size encoding %d\n", __func__, size);
619 return AARCH64_BREAK_FAULT;
622 insn = aarch64_insn_encode_ldst_size(size, insn);
624 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
627 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
630 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn,
634 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
635 enum aarch64_insn_register value,
636 enum aarch64_insn_size_type size)
639 * STADD is simply encoded as an alias for LDADD with XZR as
640 * the destination register.
642 return aarch64_insn_gen_ldadd(AARCH64_INSN_REG_ZR, address,
646 static u32 aarch64_insn_encode_prfm_imm(enum aarch64_insn_prfm_type type,
647 enum aarch64_insn_prfm_target target,
648 enum aarch64_insn_prfm_policy policy,
651 u32 imm_type = 0, imm_target = 0, imm_policy = 0;
654 case AARCH64_INSN_PRFM_TYPE_PLD:
656 case AARCH64_INSN_PRFM_TYPE_PLI:
659 case AARCH64_INSN_PRFM_TYPE_PST:
663 pr_err("%s: unknown prfm type encoding %d\n", __func__, type);
664 return AARCH64_BREAK_FAULT;
668 case AARCH64_INSN_PRFM_TARGET_L1:
670 case AARCH64_INSN_PRFM_TARGET_L2:
673 case AARCH64_INSN_PRFM_TARGET_L3:
677 pr_err("%s: unknown prfm target encoding %d\n", __func__, target);
678 return AARCH64_BREAK_FAULT;
682 case AARCH64_INSN_PRFM_POLICY_KEEP:
684 case AARCH64_INSN_PRFM_POLICY_STRM:
688 pr_err("%s: unknown prfm policy encoding %d\n", __func__, policy);
689 return AARCH64_BREAK_FAULT;
692 /* In this case, imm5 is encoded into Rt field. */
693 insn &= ~GENMASK(4, 0);
694 insn |= imm_policy | (imm_target << 1) | (imm_type << 3);
699 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
700 enum aarch64_insn_prfm_type type,
701 enum aarch64_insn_prfm_target target,
702 enum aarch64_insn_prfm_policy policy)
704 u32 insn = aarch64_insn_get_prfm_value();
706 insn = aarch64_insn_encode_ldst_size(AARCH64_INSN_SIZE_64, insn);
708 insn = aarch64_insn_encode_prfm_imm(type, target, policy, insn);
710 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
713 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, 0);
716 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
717 enum aarch64_insn_register src,
718 int imm, enum aarch64_insn_variant variant,
719 enum aarch64_insn_adsb_type type)
724 case AARCH64_INSN_ADSB_ADD:
725 insn = aarch64_insn_get_add_imm_value();
727 case AARCH64_INSN_ADSB_SUB:
728 insn = aarch64_insn_get_sub_imm_value();
730 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
731 insn = aarch64_insn_get_adds_imm_value();
733 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
734 insn = aarch64_insn_get_subs_imm_value();
737 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
738 return AARCH64_BREAK_FAULT;
742 case AARCH64_INSN_VARIANT_32BIT:
744 case AARCH64_INSN_VARIANT_64BIT:
745 insn |= AARCH64_INSN_SF_BIT;
748 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
749 return AARCH64_BREAK_FAULT;
752 /* We can't encode more than a 24bit value (12bit + 12bit shift) */
753 if (imm & ~(BIT(24) - 1))
756 /* If we have something in the top 12 bits... */
757 if (imm & ~(SZ_4K - 1)) {
758 /* ... and in the low 12 bits -> error */
759 if (imm & (SZ_4K - 1))
763 insn |= AARCH64_INSN_LSL_12;
766 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
768 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
770 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
773 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
774 return AARCH64_BREAK_FAULT;
777 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
778 enum aarch64_insn_register src,
780 enum aarch64_insn_variant variant,
781 enum aarch64_insn_bitfield_type type)
787 case AARCH64_INSN_BITFIELD_MOVE:
788 insn = aarch64_insn_get_bfm_value();
790 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED:
791 insn = aarch64_insn_get_ubfm_value();
793 case AARCH64_INSN_BITFIELD_MOVE_SIGNED:
794 insn = aarch64_insn_get_sbfm_value();
797 pr_err("%s: unknown bitfield encoding %d\n", __func__, type);
798 return AARCH64_BREAK_FAULT;
802 case AARCH64_INSN_VARIANT_32BIT:
803 mask = GENMASK(4, 0);
805 case AARCH64_INSN_VARIANT_64BIT:
806 insn |= AARCH64_INSN_SF_BIT | AARCH64_INSN_N_BIT;
807 mask = GENMASK(5, 0);
810 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
811 return AARCH64_BREAK_FAULT;
815 pr_err("%s: invalid immr encoding %d\n", __func__, immr);
816 return AARCH64_BREAK_FAULT;
819 pr_err("%s: invalid imms encoding %d\n", __func__, imms);
820 return AARCH64_BREAK_FAULT;
823 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
825 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
827 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
829 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
832 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
834 enum aarch64_insn_variant variant,
835 enum aarch64_insn_movewide_type type)
840 case AARCH64_INSN_MOVEWIDE_ZERO:
841 insn = aarch64_insn_get_movz_value();
843 case AARCH64_INSN_MOVEWIDE_KEEP:
844 insn = aarch64_insn_get_movk_value();
846 case AARCH64_INSN_MOVEWIDE_INVERSE:
847 insn = aarch64_insn_get_movn_value();
850 pr_err("%s: unknown movewide encoding %d\n", __func__, type);
851 return AARCH64_BREAK_FAULT;
854 if (imm & ~(SZ_64K - 1)) {
855 pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
856 return AARCH64_BREAK_FAULT;
860 case AARCH64_INSN_VARIANT_32BIT:
861 if (shift != 0 && shift != 16) {
862 pr_err("%s: invalid shift encoding %d\n", __func__,
864 return AARCH64_BREAK_FAULT;
867 case AARCH64_INSN_VARIANT_64BIT:
868 insn |= AARCH64_INSN_SF_BIT;
869 if (shift != 0 && shift != 16 && shift != 32 && shift != 48) {
870 pr_err("%s: invalid shift encoding %d\n", __func__,
872 return AARCH64_BREAK_FAULT;
876 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
877 return AARCH64_BREAK_FAULT;
880 insn |= (shift >> 4) << 21;
882 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
884 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
887 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
888 enum aarch64_insn_register src,
889 enum aarch64_insn_register reg,
891 enum aarch64_insn_variant variant,
892 enum aarch64_insn_adsb_type type)
897 case AARCH64_INSN_ADSB_ADD:
898 insn = aarch64_insn_get_add_value();
900 case AARCH64_INSN_ADSB_SUB:
901 insn = aarch64_insn_get_sub_value();
903 case AARCH64_INSN_ADSB_ADD_SETFLAGS:
904 insn = aarch64_insn_get_adds_value();
906 case AARCH64_INSN_ADSB_SUB_SETFLAGS:
907 insn = aarch64_insn_get_subs_value();
910 pr_err("%s: unknown add/sub encoding %d\n", __func__, type);
911 return AARCH64_BREAK_FAULT;
915 case AARCH64_INSN_VARIANT_32BIT:
916 if (shift & ~(SZ_32 - 1)) {
917 pr_err("%s: invalid shift encoding %d\n", __func__,
919 return AARCH64_BREAK_FAULT;
922 case AARCH64_INSN_VARIANT_64BIT:
923 insn |= AARCH64_INSN_SF_BIT;
924 if (shift & ~(SZ_64 - 1)) {
925 pr_err("%s: invalid shift encoding %d\n", __func__,
927 return AARCH64_BREAK_FAULT;
931 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
932 return AARCH64_BREAK_FAULT;
936 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
938 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
940 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
942 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
945 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
946 enum aarch64_insn_register src,
947 enum aarch64_insn_variant variant,
948 enum aarch64_insn_data1_type type)
953 case AARCH64_INSN_DATA1_REVERSE_16:
954 insn = aarch64_insn_get_rev16_value();
956 case AARCH64_INSN_DATA1_REVERSE_32:
957 insn = aarch64_insn_get_rev32_value();
959 case AARCH64_INSN_DATA1_REVERSE_64:
960 if (variant != AARCH64_INSN_VARIANT_64BIT) {
961 pr_err("%s: invalid variant for reverse64 %d\n",
963 return AARCH64_BREAK_FAULT;
965 insn = aarch64_insn_get_rev64_value();
968 pr_err("%s: unknown data1 encoding %d\n", __func__, type);
969 return AARCH64_BREAK_FAULT;
973 case AARCH64_INSN_VARIANT_32BIT:
975 case AARCH64_INSN_VARIANT_64BIT:
976 insn |= AARCH64_INSN_SF_BIT;
979 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
980 return AARCH64_BREAK_FAULT;
983 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
985 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
988 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
989 enum aarch64_insn_register src,
990 enum aarch64_insn_register reg,
991 enum aarch64_insn_variant variant,
992 enum aarch64_insn_data2_type type)
997 case AARCH64_INSN_DATA2_UDIV:
998 insn = aarch64_insn_get_udiv_value();
1000 case AARCH64_INSN_DATA2_SDIV:
1001 insn = aarch64_insn_get_sdiv_value();
1003 case AARCH64_INSN_DATA2_LSLV:
1004 insn = aarch64_insn_get_lslv_value();
1006 case AARCH64_INSN_DATA2_LSRV:
1007 insn = aarch64_insn_get_lsrv_value();
1009 case AARCH64_INSN_DATA2_ASRV:
1010 insn = aarch64_insn_get_asrv_value();
1012 case AARCH64_INSN_DATA2_RORV:
1013 insn = aarch64_insn_get_rorv_value();
1016 pr_err("%s: unknown data2 encoding %d\n", __func__, type);
1017 return AARCH64_BREAK_FAULT;
1021 case AARCH64_INSN_VARIANT_32BIT:
1023 case AARCH64_INSN_VARIANT_64BIT:
1024 insn |= AARCH64_INSN_SF_BIT;
1027 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1028 return AARCH64_BREAK_FAULT;
1031 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1033 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1035 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1038 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
1039 enum aarch64_insn_register src,
1040 enum aarch64_insn_register reg1,
1041 enum aarch64_insn_register reg2,
1042 enum aarch64_insn_variant variant,
1043 enum aarch64_insn_data3_type type)
1048 case AARCH64_INSN_DATA3_MADD:
1049 insn = aarch64_insn_get_madd_value();
1051 case AARCH64_INSN_DATA3_MSUB:
1052 insn = aarch64_insn_get_msub_value();
1055 pr_err("%s: unknown data3 encoding %d\n", __func__, type);
1056 return AARCH64_BREAK_FAULT;
1060 case AARCH64_INSN_VARIANT_32BIT:
1062 case AARCH64_INSN_VARIANT_64BIT:
1063 insn |= AARCH64_INSN_SF_BIT;
1066 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1067 return AARCH64_BREAK_FAULT;
1070 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1072 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA, insn, src);
1074 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn,
1077 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn,
1081 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
1082 enum aarch64_insn_register src,
1083 enum aarch64_insn_register reg,
1085 enum aarch64_insn_variant variant,
1086 enum aarch64_insn_logic_type type)
1091 case AARCH64_INSN_LOGIC_AND:
1092 insn = aarch64_insn_get_and_value();
1094 case AARCH64_INSN_LOGIC_BIC:
1095 insn = aarch64_insn_get_bic_value();
1097 case AARCH64_INSN_LOGIC_ORR:
1098 insn = aarch64_insn_get_orr_value();
1100 case AARCH64_INSN_LOGIC_ORN:
1101 insn = aarch64_insn_get_orn_value();
1103 case AARCH64_INSN_LOGIC_EOR:
1104 insn = aarch64_insn_get_eor_value();
1106 case AARCH64_INSN_LOGIC_EON:
1107 insn = aarch64_insn_get_eon_value();
1109 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1110 insn = aarch64_insn_get_ands_value();
1112 case AARCH64_INSN_LOGIC_BIC_SETFLAGS:
1113 insn = aarch64_insn_get_bics_value();
1116 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1117 return AARCH64_BREAK_FAULT;
1121 case AARCH64_INSN_VARIANT_32BIT:
1122 if (shift & ~(SZ_32 - 1)) {
1123 pr_err("%s: invalid shift encoding %d\n", __func__,
1125 return AARCH64_BREAK_FAULT;
1128 case AARCH64_INSN_VARIANT_64BIT:
1129 insn |= AARCH64_INSN_SF_BIT;
1130 if (shift & ~(SZ_64 - 1)) {
1131 pr_err("%s: invalid shift encoding %d\n", __func__,
1133 return AARCH64_BREAK_FAULT;
1137 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1138 return AARCH64_BREAK_FAULT;
1142 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
1144 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
1146 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
1148 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6, insn, shift);
1152 * MOV (register) is architecturally an alias of ORR (shifted register) where
1153 * MOV <*d>, <*m> is equivalent to ORR <*d>, <*ZR>, <*m>
1155 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
1156 enum aarch64_insn_register src,
1157 enum aarch64_insn_variant variant)
1159 return aarch64_insn_gen_logical_shifted_reg(dst, AARCH64_INSN_REG_ZR,
1161 AARCH64_INSN_LOGIC_ORR);
1164 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
1165 enum aarch64_insn_register reg,
1166 enum aarch64_insn_adr_type type)
1172 case AARCH64_INSN_ADR_TYPE_ADR:
1173 insn = aarch64_insn_get_adr_value();
1176 case AARCH64_INSN_ADR_TYPE_ADRP:
1177 insn = aarch64_insn_get_adrp_value();
1178 offset = (addr - ALIGN_DOWN(pc, SZ_4K)) >> 12;
1181 pr_err("%s: unknown adr encoding %d\n", __func__, type);
1182 return AARCH64_BREAK_FAULT;
1185 if (offset < -SZ_1M || offset >= SZ_1M)
1186 return AARCH64_BREAK_FAULT;
1188 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, reg);
1190 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn, offset);
1194 * Decode the imm field of a branch, and return the byte offset as a
1195 * signed value (so it can be used when computing a new branch
1198 s32 aarch64_get_branch_offset(u32 insn)
1202 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) {
1203 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn);
1204 return (imm << 6) >> 4;
1207 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1208 aarch64_insn_is_bcond(insn)) {
1209 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn);
1210 return (imm << 13) >> 11;
1213 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) {
1214 imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn);
1215 return (imm << 18) >> 16;
1218 /* Unhandled instruction */
1223 * Encode the displacement of a branch in the imm field and return the
1224 * updated instruction.
1226 u32 aarch64_set_branch_offset(u32 insn, s32 offset)
1228 if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn))
1229 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26, insn,
1232 if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) ||
1233 aarch64_insn_is_bcond(insn))
1234 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19, insn,
1237 if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn))
1238 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_14, insn,
1241 /* Unhandled instruction */
1245 s32 aarch64_insn_adrp_get_offset(u32 insn)
1247 BUG_ON(!aarch64_insn_is_adrp(insn));
1248 return aarch64_insn_decode_immediate(AARCH64_INSN_IMM_ADR, insn) << 12;
1251 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
1253 BUG_ON(!aarch64_insn_is_adrp(insn));
1254 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_ADR, insn,
1259 * Extract the Op/CR data from a msr/mrs instruction.
1261 u32 aarch64_insn_extract_system_reg(u32 insn)
1263 return (insn & 0x1FFFE0) >> 5;
1266 bool aarch32_insn_is_wide(u32 insn)
1268 return insn >= 0xe800;
1272 * Macros/defines for extracting register numbers from instruction.
1274 u32 aarch32_insn_extract_reg_num(u32 insn, int offset)
1276 return (insn & (0xf << offset)) >> offset;
1279 #define OPC2_MASK 0x7
1280 #define OPC2_OFFSET 5
1281 u32 aarch32_insn_mcr_extract_opc2(u32 insn)
1283 return (insn & (OPC2_MASK << OPC2_OFFSET)) >> OPC2_OFFSET;
1286 #define CRM_MASK 0xf
1287 u32 aarch32_insn_mcr_extract_crm(u32 insn)
1289 return insn & CRM_MASK;
1292 static bool range_of_ones(u64 val)
1294 /* Doesn't handle full ones or full zeroes */
1295 u64 sval = val >> __ffs64(val);
1297 /* One of Sean Eron Anderson's bithack tricks */
1298 return ((sval + 1) & (sval)) == 0;
1301 static u32 aarch64_encode_immediate(u64 imm,
1302 enum aarch64_insn_variant variant,
1305 unsigned int immr, imms, n, ones, ror, esz, tmp;
1309 case AARCH64_INSN_VARIANT_32BIT:
1312 case AARCH64_INSN_VARIANT_64BIT:
1313 insn |= AARCH64_INSN_SF_BIT;
1317 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1318 return AARCH64_BREAK_FAULT;
1321 mask = GENMASK(esz - 1, 0);
1323 /* Can't encode full zeroes, full ones, or value wider than the mask */
1324 if (!imm || imm == mask || imm & ~mask)
1325 return AARCH64_BREAK_FAULT;
1328 * Inverse of Replicate(). Try to spot a repeating pattern
1329 * with a pow2 stride.
1331 for (tmp = esz / 2; tmp >= 2; tmp /= 2) {
1332 u64 emask = BIT(tmp) - 1;
1334 if ((imm & emask) != ((imm >> tmp) & emask))
1341 /* N is only set if we're encoding a 64bit value */
1344 /* Trim imm to the element size */
1347 /* That's how many ones we need to encode */
1348 ones = hweight64(imm);
1351 * imms is set to (ones - 1), prefixed with a string of ones
1352 * and a zero if they fit. Cap it to 6 bits.
1355 imms |= 0xf << ffs(esz);
1358 /* Compute the rotation */
1359 if (range_of_ones(imm)) {
1361 * Pattern: 0..01..10..0
1363 * Compute how many rotate we need to align it right
1368 * Pattern: 0..01..10..01..1
1370 * Fill the unused top bits with ones, and check if
1371 * the result is a valid immediate (all ones with a
1372 * contiguous ranges of zeroes).
1375 if (!range_of_ones(~imm))
1376 return AARCH64_BREAK_FAULT;
1379 * Compute the rotation to get a continuous set of
1380 * ones, with the first bit set at position 0
1386 * immr is the number of bits we need to rotate back to the
1387 * original set of ones. Note that this is relative to the
1390 immr = (esz - ror) % esz;
1392 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, n);
1393 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr);
1394 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, imms);
1397 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
1398 enum aarch64_insn_variant variant,
1399 enum aarch64_insn_register Rn,
1400 enum aarch64_insn_register Rd,
1406 case AARCH64_INSN_LOGIC_AND:
1407 insn = aarch64_insn_get_and_imm_value();
1409 case AARCH64_INSN_LOGIC_ORR:
1410 insn = aarch64_insn_get_orr_imm_value();
1412 case AARCH64_INSN_LOGIC_EOR:
1413 insn = aarch64_insn_get_eor_imm_value();
1415 case AARCH64_INSN_LOGIC_AND_SETFLAGS:
1416 insn = aarch64_insn_get_ands_imm_value();
1419 pr_err("%s: unknown logical encoding %d\n", __func__, type);
1420 return AARCH64_BREAK_FAULT;
1423 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
1424 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
1425 return aarch64_encode_immediate(imm, variant, insn);
1428 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
1429 enum aarch64_insn_register Rm,
1430 enum aarch64_insn_register Rn,
1431 enum aarch64_insn_register Rd,
1436 insn = aarch64_insn_get_extr_value();
1439 case AARCH64_INSN_VARIANT_32BIT:
1441 return AARCH64_BREAK_FAULT;
1443 case AARCH64_INSN_VARIANT_64BIT:
1445 return AARCH64_BREAK_FAULT;
1446 insn |= AARCH64_INSN_SF_BIT;
1447 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, 1);
1450 pr_err("%s: unknown variant encoding %d\n", __func__, variant);
1451 return AARCH64_BREAK_FAULT;
1454 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, lsb);
1455 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
1456 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
1457 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);