1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/kvm_host.h>
16 #include <linux/printk.h>
17 #include <linux/uaccess.h>
19 #include <asm/cacheflush.h>
20 #include <asm/cputype.h>
21 #include <asm/debug-monitors.h>
23 #include <asm/kvm_arm.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_hyp.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/perf_event.h>
28 #include <asm/sysreg.h>
30 #include <trace/events/kvm.h>
37 * All of this file is extremely similar to the ARM coproc.c, but the
38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
47 #define reg_to_encoding(x) \
48 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
49 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
51 static bool read_from_write_only(struct kvm_vcpu *vcpu,
52 struct sys_reg_params *params,
53 const struct sys_reg_desc *r)
55 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
56 print_sys_reg_instr(params);
57 kvm_inject_undefined(vcpu);
61 static bool write_to_read_only(struct kvm_vcpu *vcpu,
62 struct sys_reg_params *params,
63 const struct sys_reg_desc *r)
65 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
66 print_sys_reg_instr(params);
67 kvm_inject_undefined(vcpu);
71 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
73 u64 val = 0x8badf00d8badf00d;
75 if (vcpu->arch.sysregs_loaded_on_cpu &&
76 __vcpu_read_sys_reg_from_cpu(reg, &val))
79 return __vcpu_sys_reg(vcpu, reg);
82 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
84 if (vcpu->arch.sysregs_loaded_on_cpu &&
85 __vcpu_write_sys_reg_to_cpu(val, reg))
88 __vcpu_sys_reg(vcpu, reg) = val;
91 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
92 static u32 cache_levels;
94 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
97 /* Which cache CCSIDR represents depends on CSSELR value. */
98 static u32 get_ccsidr(u32 csselr)
102 /* Make sure noone else changes CSSELR during this! */
104 write_sysreg(csselr, csselr_el1);
106 ccsidr = read_sysreg(ccsidr_el1);
113 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
115 static bool access_dcsw(struct kvm_vcpu *vcpu,
116 struct sys_reg_params *p,
117 const struct sys_reg_desc *r)
120 return read_from_write_only(vcpu, p, r);
123 * Only track S/W ops if we don't have FWB. It still indicates
124 * that the guest is a bit broken (S/W operations should only
125 * be done by firmware, knowing that there is only a single
126 * CPU left in the system, and certainly not from non-secure
129 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
130 kvm_set_way_flush(vcpu);
135 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
137 switch (r->aarch32_map) {
139 *mask = GENMASK_ULL(31, 0);
143 *mask = GENMASK_ULL(63, 32);
147 *mask = GENMASK_ULL(63, 0);
154 * Generic accessor for VM registers. Only called as long as HCR_TVM
155 * is set. If the guest enables the MMU, we stop trapping the VM
156 * sys_regs and leave it in complete control of the caches.
158 static bool access_vm_reg(struct kvm_vcpu *vcpu,
159 struct sys_reg_params *p,
160 const struct sys_reg_desc *r)
162 bool was_enabled = vcpu_has_cache_enabled(vcpu);
163 u64 val, mask, shift;
165 BUG_ON(!p->is_write);
167 get_access_mask(r, &mask, &shift);
170 val = vcpu_read_sys_reg(vcpu, r->reg);
176 val |= (p->regval & (mask >> shift)) << shift;
177 vcpu_write_sys_reg(vcpu, val, r->reg);
179 kvm_toggle_cache(vcpu, was_enabled);
183 static bool access_actlr(struct kvm_vcpu *vcpu,
184 struct sys_reg_params *p,
185 const struct sys_reg_desc *r)
190 return ignore_write(vcpu, p);
192 get_access_mask(r, &mask, &shift);
193 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
199 * Trap handler for the GICv3 SGI generation system register.
200 * Forward the request to the VGIC emulation.
201 * The cp15_64 code makes sure this automatically works
202 * for both AArch64 and AArch32 accesses.
204 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
205 struct sys_reg_params *p,
206 const struct sys_reg_desc *r)
211 return read_from_write_only(vcpu, p, r);
214 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
215 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
216 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
217 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
220 if (p->Op0 == 0) { /* AArch32 */
222 default: /* Keep GCC quiet */
223 case 0: /* ICC_SGI1R */
226 case 1: /* ICC_ASGI1R */
227 case 2: /* ICC_SGI0R */
231 } else { /* AArch64 */
233 default: /* Keep GCC quiet */
234 case 5: /* ICC_SGI1R_EL1 */
237 case 6: /* ICC_ASGI1R_EL1 */
238 case 7: /* ICC_SGI0R_EL1 */
244 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
249 static bool access_gic_sre(struct kvm_vcpu *vcpu,
250 struct sys_reg_params *p,
251 const struct sys_reg_desc *r)
254 return ignore_write(vcpu, p);
256 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
260 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
261 struct sys_reg_params *p,
262 const struct sys_reg_desc *r)
265 return ignore_write(vcpu, p);
267 return read_zero(vcpu, p);
271 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
272 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
273 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
274 * treat it separately.
276 static bool trap_loregion(struct kvm_vcpu *vcpu,
277 struct sys_reg_params *p,
278 const struct sys_reg_desc *r)
280 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
281 u32 sr = reg_to_encoding(r);
283 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
284 kvm_inject_undefined(vcpu);
288 if (p->is_write && sr == SYS_LORID_EL1)
289 return write_to_read_only(vcpu, p, r);
291 return trap_raz_wi(vcpu, p, r);
294 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
295 struct sys_reg_params *p,
296 const struct sys_reg_desc *r)
299 return ignore_write(vcpu, p);
301 p->regval = (1 << 3);
306 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
307 struct sys_reg_params *p,
308 const struct sys_reg_desc *r)
311 return ignore_write(vcpu, p);
313 p->regval = read_sysreg(dbgauthstatus_el1);
319 * We want to avoid world-switching all the DBG registers all the
322 * - If we've touched any debug register, it is likely that we're
323 * going to touch more of them. It then makes sense to disable the
324 * traps and start doing the save/restore dance
325 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
326 * then mandatory to save/restore the registers, as the guest
329 * For this, we use a DIRTY bit, indicating the guest has modified the
330 * debug registers, used as follow:
333 * - If the dirty bit is set (because we're coming back from trapping),
334 * disable the traps, save host registers, restore guest registers.
335 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
336 * set the dirty bit, disable the traps, save host registers,
337 * restore guest registers.
338 * - Otherwise, enable the traps
341 * - If the dirty bit is set, save guest registers, restore host
342 * registers and clear the dirty bit. This ensure that the host can
343 * now use the debug registers.
345 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
346 struct sys_reg_params *p,
347 const struct sys_reg_desc *r)
350 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
351 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
353 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
356 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
362 * reg_to_dbg/dbg_to_reg
364 * A 32 bit write to a debug register leave top bits alone
365 * A 32 bit read from a debug register only returns the bottom bits
367 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
368 * hyp.S code switches between host and guest values in future.
370 static void reg_to_dbg(struct kvm_vcpu *vcpu,
371 struct sys_reg_params *p,
372 const struct sys_reg_desc *rd,
375 u64 mask, shift, val;
377 get_access_mask(rd, &mask, &shift);
381 val |= (p->regval & (mask >> shift)) << shift;
384 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
387 static void dbg_to_reg(struct kvm_vcpu *vcpu,
388 struct sys_reg_params *p,
389 const struct sys_reg_desc *rd,
394 get_access_mask(rd, &mask, &shift);
395 p->regval = (*dbg_reg & mask) >> shift;
398 static bool trap_bvr(struct kvm_vcpu *vcpu,
399 struct sys_reg_params *p,
400 const struct sys_reg_desc *rd)
402 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
405 reg_to_dbg(vcpu, p, rd, dbg_reg);
407 dbg_to_reg(vcpu, p, rd, dbg_reg);
409 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
414 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
415 const struct kvm_one_reg *reg, void __user *uaddr)
417 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
419 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
424 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
425 const struct kvm_one_reg *reg, void __user *uaddr)
427 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
429 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
434 static void reset_bvr(struct kvm_vcpu *vcpu,
435 const struct sys_reg_desc *rd)
437 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
440 static bool trap_bcr(struct kvm_vcpu *vcpu,
441 struct sys_reg_params *p,
442 const struct sys_reg_desc *rd)
444 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
447 reg_to_dbg(vcpu, p, rd, dbg_reg);
449 dbg_to_reg(vcpu, p, rd, dbg_reg);
451 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
456 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
457 const struct kvm_one_reg *reg, void __user *uaddr)
459 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
461 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
467 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
468 const struct kvm_one_reg *reg, void __user *uaddr)
470 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
472 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
477 static void reset_bcr(struct kvm_vcpu *vcpu,
478 const struct sys_reg_desc *rd)
480 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
483 static bool trap_wvr(struct kvm_vcpu *vcpu,
484 struct sys_reg_params *p,
485 const struct sys_reg_desc *rd)
487 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
490 reg_to_dbg(vcpu, p, rd, dbg_reg);
492 dbg_to_reg(vcpu, p, rd, dbg_reg);
494 trace_trap_reg(__func__, rd->CRm, p->is_write,
495 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
500 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
501 const struct kvm_one_reg *reg, void __user *uaddr)
503 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
505 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
510 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
511 const struct kvm_one_reg *reg, void __user *uaddr)
513 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
515 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
520 static void reset_wvr(struct kvm_vcpu *vcpu,
521 const struct sys_reg_desc *rd)
523 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
526 static bool trap_wcr(struct kvm_vcpu *vcpu,
527 struct sys_reg_params *p,
528 const struct sys_reg_desc *rd)
530 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
533 reg_to_dbg(vcpu, p, rd, dbg_reg);
535 dbg_to_reg(vcpu, p, rd, dbg_reg);
537 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
542 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
543 const struct kvm_one_reg *reg, void __user *uaddr)
545 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
547 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
552 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
553 const struct kvm_one_reg *reg, void __user *uaddr)
555 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
557 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
562 static void reset_wcr(struct kvm_vcpu *vcpu,
563 const struct sys_reg_desc *rd)
565 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
568 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
570 u64 amair = read_sysreg(amair_el1);
571 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
574 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
576 u64 actlr = read_sysreg(actlr_el1);
577 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
580 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
585 * Map the vcpu_id into the first three affinity level fields of
586 * the MPIDR. We limit the number of VCPUs in level 0 due to a
587 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
588 * of the GICv3 to be able to address each CPU directly when
591 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
592 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
593 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
594 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
597 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
598 const struct sys_reg_desc *r)
600 if (kvm_vcpu_has_pmu(vcpu))
606 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
610 /* No PMU available, PMCR_EL0 may UNDEF... */
611 if (!kvm_arm_support_pmu_v3())
614 pmcr = read_sysreg(pmcr_el0);
616 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
617 * except PMCR.E resetting to zero.
619 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
620 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
621 if (!system_supports_32bit_el0())
622 val |= ARMV8_PMU_PMCR_LC;
623 __vcpu_sys_reg(vcpu, r->reg) = val;
626 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
628 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
629 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
632 kvm_inject_undefined(vcpu);
637 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
639 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
642 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
644 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
647 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
649 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
652 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
654 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
657 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
658 const struct sys_reg_desc *r)
662 if (pmu_access_el0_disabled(vcpu))
666 /* Only update writeable bits of PMCR */
667 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
668 val &= ~ARMV8_PMU_PMCR_MASK;
669 val |= p->regval & ARMV8_PMU_PMCR_MASK;
670 if (!system_supports_32bit_el0())
671 val |= ARMV8_PMU_PMCR_LC;
672 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
673 kvm_pmu_handle_pmcr(vcpu, val);
674 kvm_vcpu_pmu_restore_guest(vcpu);
676 /* PMCR.P & PMCR.C are RAZ */
677 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
678 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
685 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
686 const struct sys_reg_desc *r)
688 if (pmu_access_event_counter_el0_disabled(vcpu))
692 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
694 /* return PMSELR.SEL field */
695 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
696 & ARMV8_PMU_COUNTER_MASK;
701 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
702 const struct sys_reg_desc *r)
704 u64 pmceid, mask, shift;
708 if (pmu_access_el0_disabled(vcpu))
711 get_access_mask(r, &mask, &shift);
713 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
722 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
726 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
727 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
728 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
729 kvm_inject_undefined(vcpu);
736 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
737 struct sys_reg_params *p,
738 const struct sys_reg_desc *r)
742 if (r->CRn == 9 && r->CRm == 13) {
745 if (pmu_access_event_counter_el0_disabled(vcpu))
748 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
749 & ARMV8_PMU_COUNTER_MASK;
750 } else if (r->Op2 == 0) {
752 if (pmu_access_cycle_counter_el0_disabled(vcpu))
755 idx = ARMV8_PMU_CYCLE_IDX;
757 } else if (r->CRn == 0 && r->CRm == 9) {
759 if (pmu_access_event_counter_el0_disabled(vcpu))
762 idx = ARMV8_PMU_CYCLE_IDX;
763 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
765 if (pmu_access_event_counter_el0_disabled(vcpu))
768 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
771 /* Catch any decoding mistake */
772 WARN_ON(idx == ~0UL);
774 if (!pmu_counter_idx_valid(vcpu, idx))
778 if (pmu_access_el0_disabled(vcpu))
781 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
783 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
789 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
790 const struct sys_reg_desc *r)
794 if (pmu_access_el0_disabled(vcpu))
797 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
799 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
800 reg = PMEVTYPER0_EL0 + idx;
801 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
802 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
803 if (idx == ARMV8_PMU_CYCLE_IDX)
807 reg = PMEVTYPER0_EL0 + idx;
812 if (!pmu_counter_idx_valid(vcpu, idx))
816 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
817 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
818 kvm_vcpu_pmu_restore_guest(vcpu);
820 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
826 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
827 const struct sys_reg_desc *r)
831 if (pmu_access_el0_disabled(vcpu))
834 mask = kvm_pmu_valid_counter_mask(vcpu);
836 val = p->regval & mask;
838 /* accessing PMCNTENSET_EL0 */
839 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
840 kvm_pmu_enable_counter_mask(vcpu, val);
841 kvm_vcpu_pmu_restore_guest(vcpu);
843 /* accessing PMCNTENCLR_EL0 */
844 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
845 kvm_pmu_disable_counter_mask(vcpu, val);
848 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
854 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
855 const struct sys_reg_desc *r)
857 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
859 if (check_pmu_access_disabled(vcpu, 0))
863 u64 val = p->regval & mask;
866 /* accessing PMINTENSET_EL1 */
867 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
869 /* accessing PMINTENCLR_EL1 */
870 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
872 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
878 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
879 const struct sys_reg_desc *r)
881 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
883 if (pmu_access_el0_disabled(vcpu))
888 /* accessing PMOVSSET_EL0 */
889 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
891 /* accessing PMOVSCLR_EL0 */
892 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
894 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
900 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
901 const struct sys_reg_desc *r)
906 return read_from_write_only(vcpu, p, r);
908 if (pmu_write_swinc_el0_disabled(vcpu))
911 mask = kvm_pmu_valid_counter_mask(vcpu);
912 kvm_pmu_software_increment(vcpu, p->regval & mask);
916 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
917 const struct sys_reg_desc *r)
920 if (!vcpu_mode_priv(vcpu)) {
921 kvm_inject_undefined(vcpu);
925 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
926 p->regval & ARMV8_PMU_USERENR_MASK;
928 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
929 & ARMV8_PMU_USERENR_MASK;
935 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
936 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
937 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
938 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
939 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
940 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
941 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
942 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
943 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
944 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
946 #define PMU_SYS_REG(r) \
947 SYS_DESC(r), .reset = reset_unknown, .visibility = pmu_visibility
949 /* Macro to expand the PMEVCNTRn_EL0 register */
950 #define PMU_PMEVCNTR_EL0(n) \
951 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \
952 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
954 /* Macro to expand the PMEVTYPERn_EL0 register */
955 #define PMU_PMEVTYPER_EL0(n) \
956 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \
957 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
959 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
960 const struct sys_reg_desc *r)
962 kvm_inject_undefined(vcpu);
967 /* Macro to expand the AMU counter and type registers*/
968 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
969 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
970 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
971 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
973 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
974 const struct sys_reg_desc *rd)
976 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
980 * If we land here on a PtrAuth access, that is because we didn't
981 * fixup the access on exit by allowing the PtrAuth sysregs. The only
982 * way this happens is when the guest does not have PtrAuth support
985 #define __PTRAUTH_KEY(k) \
986 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
987 .visibility = ptrauth_visibility}
989 #define PTRAUTH_KEY(k) \
990 __PTRAUTH_KEY(k ## KEYLO_EL1), \
991 __PTRAUTH_KEY(k ## KEYHI_EL1)
993 static bool access_arch_timer(struct kvm_vcpu *vcpu,
994 struct sys_reg_params *p,
995 const struct sys_reg_desc *r)
997 enum kvm_arch_timers tmr;
998 enum kvm_arch_timer_regs treg;
999 u64 reg = reg_to_encoding(r);
1002 case SYS_CNTP_TVAL_EL0:
1003 case SYS_AARCH32_CNTP_TVAL:
1005 treg = TIMER_REG_TVAL;
1007 case SYS_CNTP_CTL_EL0:
1008 case SYS_AARCH32_CNTP_CTL:
1010 treg = TIMER_REG_CTL;
1012 case SYS_CNTP_CVAL_EL0:
1013 case SYS_AARCH32_CNTP_CVAL:
1015 treg = TIMER_REG_CVAL;
1022 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1024 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1029 #define FEATURE(x) (GENMASK_ULL(x##_SHIFT + 3, x##_SHIFT))
1031 /* Read a sanitised cpufeature ID register by sys_reg_desc */
1032 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1033 struct sys_reg_desc const *r, bool raz)
1035 u32 id = reg_to_encoding(r);
1036 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1039 case SYS_ID_AA64PFR0_EL1:
1040 if (!vcpu_has_sve(vcpu))
1041 val &= ~FEATURE(ID_AA64PFR0_SVE);
1042 val &= ~FEATURE(ID_AA64PFR0_AMU);
1043 val &= ~FEATURE(ID_AA64PFR0_CSV2);
1044 val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
1045 val &= ~FEATURE(ID_AA64PFR0_CSV3);
1046 val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
1048 case SYS_ID_AA64PFR1_EL1:
1049 val &= ~FEATURE(ID_AA64PFR1_MTE);
1051 case SYS_ID_AA64ISAR1_EL1:
1052 if (!vcpu_has_ptrauth(vcpu))
1053 val &= ~(FEATURE(ID_AA64ISAR1_APA) |
1054 FEATURE(ID_AA64ISAR1_API) |
1055 FEATURE(ID_AA64ISAR1_GPA) |
1056 FEATURE(ID_AA64ISAR1_GPI));
1058 case SYS_ID_AA64DFR0_EL1:
1059 /* Limit debug to ARMv8.0 */
1060 val &= ~FEATURE(ID_AA64DFR0_DEBUGVER);
1061 val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6);
1062 /* Limit guests to PMUv3 for ARMv8.4 */
1063 val = cpuid_feature_cap_perfmon_field(val,
1064 ID_AA64DFR0_PMUVER_SHIFT,
1065 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
1066 /* Hide SPE from guests */
1067 val &= ~FEATURE(ID_AA64DFR0_PMSVER);
1069 case SYS_ID_DFR0_EL1:
1070 /* Limit guests to PMUv3 for ARMv8.4 */
1071 val = cpuid_feature_cap_perfmon_field(val,
1072 ID_DFR0_PERFMON_SHIFT,
1073 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
1080 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1081 const struct sys_reg_desc *r)
1083 u32 id = reg_to_encoding(r);
1086 case SYS_ID_AA64ZFR0_EL1:
1087 if (!vcpu_has_sve(vcpu))
1095 /* cpufeature ID register access trap handlers */
1097 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1098 struct sys_reg_params *p,
1099 const struct sys_reg_desc *r,
1103 return write_to_read_only(vcpu, p, r);
1105 p->regval = read_id_reg(vcpu, r, raz);
1109 static bool access_id_reg(struct kvm_vcpu *vcpu,
1110 struct sys_reg_params *p,
1111 const struct sys_reg_desc *r)
1113 bool raz = sysreg_visible_as_raz(vcpu, r);
1115 return __access_id_reg(vcpu, p, r, raz);
1118 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1119 struct sys_reg_params *p,
1120 const struct sys_reg_desc *r)
1122 return __access_id_reg(vcpu, p, r, true);
1125 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1126 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1127 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1129 /* Visibility overrides for SVE-specific control registers */
1130 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1131 const struct sys_reg_desc *rd)
1133 if (vcpu_has_sve(vcpu))
1139 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1140 const struct sys_reg_desc *rd,
1141 const struct kvm_one_reg *reg, void __user *uaddr)
1143 const u64 id = sys_reg_to_index(rd);
1148 err = reg_from_user(&val, uaddr, id);
1153 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1154 * it doesn't promise more than what is actually provided (the
1155 * guest could otherwise be covered in ectoplasmic residue).
1157 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1159 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1162 /* Same thing for CSV3 */
1163 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT);
1165 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
1168 /* We can only differ with CSV[23], and anything else is an error */
1169 val ^= read_id_reg(vcpu, rd, false);
1170 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) |
1171 (0xFUL << ID_AA64PFR0_CSV3_SHIFT));
1175 vcpu->kvm->arch.pfr0_csv2 = csv2;
1176 vcpu->kvm->arch.pfr0_csv3 = csv3 ;
1182 * cpufeature ID register user accessors
1184 * For now, these registers are immutable for userspace, so no values
1185 * are stored, and for set_id_reg() we don't allow the effective value
1188 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1189 const struct sys_reg_desc *rd, void __user *uaddr,
1192 const u64 id = sys_reg_to_index(rd);
1193 const u64 val = read_id_reg(vcpu, rd, raz);
1195 return reg_to_user(uaddr, &val, id);
1198 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1199 const struct sys_reg_desc *rd, void __user *uaddr,
1202 const u64 id = sys_reg_to_index(rd);
1206 err = reg_from_user(&val, uaddr, id);
1210 /* This is what we mean by invariant: you can't change it. */
1211 if (val != read_id_reg(vcpu, rd, raz))
1217 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1218 const struct kvm_one_reg *reg, void __user *uaddr)
1220 bool raz = sysreg_visible_as_raz(vcpu, rd);
1222 return __get_id_reg(vcpu, rd, uaddr, raz);
1225 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1226 const struct kvm_one_reg *reg, void __user *uaddr)
1228 bool raz = sysreg_visible_as_raz(vcpu, rd);
1230 return __set_id_reg(vcpu, rd, uaddr, raz);
1233 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1234 const struct kvm_one_reg *reg, void __user *uaddr)
1236 return __get_id_reg(vcpu, rd, uaddr, true);
1239 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1240 const struct kvm_one_reg *reg, void __user *uaddr)
1242 return __set_id_reg(vcpu, rd, uaddr, true);
1245 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1246 const struct sys_reg_desc *r)
1249 return write_to_read_only(vcpu, p, r);
1251 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1255 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1256 const struct sys_reg_desc *r)
1259 return write_to_read_only(vcpu, p, r);
1261 p->regval = read_sysreg(clidr_el1);
1265 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1266 const struct sys_reg_desc *r)
1271 vcpu_write_sys_reg(vcpu, p->regval, reg);
1273 p->regval = vcpu_read_sys_reg(vcpu, reg);
1277 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1278 const struct sys_reg_desc *r)
1283 return write_to_read_only(vcpu, p, r);
1285 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1286 p->regval = get_ccsidr(csselr);
1289 * Guests should not be doing cache operations by set/way at all, and
1290 * for this reason, we trap them and attempt to infer the intent, so
1291 * that we can flush the entire guest's address space at the appropriate
1293 * To prevent this trapping from causing performance problems, let's
1294 * expose the geometry of all data and unified caches (which are
1295 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1296 * [If guests should attempt to infer aliasing properties from the
1297 * geometry (which is not permitted by the architecture), they would
1298 * only do so for virtually indexed caches.]
1300 if (!(csselr & 1)) // data or unified cache
1301 p->regval &= ~GENMASK(27, 3);
1305 /* sys_reg_desc initialiser for known cpufeature ID registers */
1306 #define ID_SANITISED(name) { \
1307 SYS_DESC(SYS_##name), \
1308 .access = access_id_reg, \
1309 .get_user = get_id_reg, \
1310 .set_user = set_id_reg, \
1311 .visibility = id_visibility, \
1315 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1316 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1317 * (1 <= crm < 8, 0 <= Op2 < 8).
1319 #define ID_UNALLOCATED(crm, op2) { \
1320 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1321 .access = access_raz_id_reg, \
1322 .get_user = get_raz_id_reg, \
1323 .set_user = set_raz_id_reg, \
1327 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1328 * For now, these are exposed just like unallocated ID regs: they appear
1329 * RAZ for the guest.
1331 #define ID_HIDDEN(name) { \
1332 SYS_DESC(SYS_##name), \
1333 .access = access_raz_id_reg, \
1334 .get_user = get_raz_id_reg, \
1335 .set_user = set_raz_id_reg, \
1339 * Architected system registers.
1340 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1342 * Debug handling: We do trap most, if not all debug related system
1343 * registers. The implementation is good enough to ensure that a guest
1344 * can use these with minimal performance degradation. The drawback is
1345 * that we don't implement any of the external debug, none of the
1346 * OSlock protocol. This should be revisited if we ever encounter a
1347 * more demanding guest...
1349 static const struct sys_reg_desc sys_reg_descs[] = {
1350 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1351 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1352 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1354 DBG_BCR_BVR_WCR_WVR_EL1(0),
1355 DBG_BCR_BVR_WCR_WVR_EL1(1),
1356 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1357 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1358 DBG_BCR_BVR_WCR_WVR_EL1(2),
1359 DBG_BCR_BVR_WCR_WVR_EL1(3),
1360 DBG_BCR_BVR_WCR_WVR_EL1(4),
1361 DBG_BCR_BVR_WCR_WVR_EL1(5),
1362 DBG_BCR_BVR_WCR_WVR_EL1(6),
1363 DBG_BCR_BVR_WCR_WVR_EL1(7),
1364 DBG_BCR_BVR_WCR_WVR_EL1(8),
1365 DBG_BCR_BVR_WCR_WVR_EL1(9),
1366 DBG_BCR_BVR_WCR_WVR_EL1(10),
1367 DBG_BCR_BVR_WCR_WVR_EL1(11),
1368 DBG_BCR_BVR_WCR_WVR_EL1(12),
1369 DBG_BCR_BVR_WCR_WVR_EL1(13),
1370 DBG_BCR_BVR_WCR_WVR_EL1(14),
1371 DBG_BCR_BVR_WCR_WVR_EL1(15),
1373 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1374 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1375 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1376 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1377 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1378 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1379 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1380 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1382 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1383 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1384 // DBGDTR[TR]X_EL0 share the same encoding
1385 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1387 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1389 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1392 * ID regs: all ID_SANITISED() entries here must have corresponding
1393 * entries in arm64_ftr_regs[].
1396 /* AArch64 mappings of the AArch32 ID registers */
1398 ID_SANITISED(ID_PFR0_EL1),
1399 ID_SANITISED(ID_PFR1_EL1),
1400 ID_SANITISED(ID_DFR0_EL1),
1401 ID_HIDDEN(ID_AFR0_EL1),
1402 ID_SANITISED(ID_MMFR0_EL1),
1403 ID_SANITISED(ID_MMFR1_EL1),
1404 ID_SANITISED(ID_MMFR2_EL1),
1405 ID_SANITISED(ID_MMFR3_EL1),
1408 ID_SANITISED(ID_ISAR0_EL1),
1409 ID_SANITISED(ID_ISAR1_EL1),
1410 ID_SANITISED(ID_ISAR2_EL1),
1411 ID_SANITISED(ID_ISAR3_EL1),
1412 ID_SANITISED(ID_ISAR4_EL1),
1413 ID_SANITISED(ID_ISAR5_EL1),
1414 ID_SANITISED(ID_MMFR4_EL1),
1415 ID_SANITISED(ID_ISAR6_EL1),
1418 ID_SANITISED(MVFR0_EL1),
1419 ID_SANITISED(MVFR1_EL1),
1420 ID_SANITISED(MVFR2_EL1),
1421 ID_UNALLOCATED(3,3),
1422 ID_SANITISED(ID_PFR2_EL1),
1423 ID_HIDDEN(ID_DFR1_EL1),
1424 ID_SANITISED(ID_MMFR5_EL1),
1425 ID_UNALLOCATED(3,7),
1427 /* AArch64 ID registers */
1429 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1430 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
1431 ID_SANITISED(ID_AA64PFR1_EL1),
1432 ID_UNALLOCATED(4,2),
1433 ID_UNALLOCATED(4,3),
1434 ID_SANITISED(ID_AA64ZFR0_EL1),
1435 ID_UNALLOCATED(4,5),
1436 ID_UNALLOCATED(4,6),
1437 ID_UNALLOCATED(4,7),
1440 ID_SANITISED(ID_AA64DFR0_EL1),
1441 ID_SANITISED(ID_AA64DFR1_EL1),
1442 ID_UNALLOCATED(5,2),
1443 ID_UNALLOCATED(5,3),
1444 ID_HIDDEN(ID_AA64AFR0_EL1),
1445 ID_HIDDEN(ID_AA64AFR1_EL1),
1446 ID_UNALLOCATED(5,6),
1447 ID_UNALLOCATED(5,7),
1450 ID_SANITISED(ID_AA64ISAR0_EL1),
1451 ID_SANITISED(ID_AA64ISAR1_EL1),
1452 ID_UNALLOCATED(6,2),
1453 ID_UNALLOCATED(6,3),
1454 ID_UNALLOCATED(6,4),
1455 ID_UNALLOCATED(6,5),
1456 ID_UNALLOCATED(6,6),
1457 ID_UNALLOCATED(6,7),
1460 ID_SANITISED(ID_AA64MMFR0_EL1),
1461 ID_SANITISED(ID_AA64MMFR1_EL1),
1462 ID_SANITISED(ID_AA64MMFR2_EL1),
1463 ID_UNALLOCATED(7,3),
1464 ID_UNALLOCATED(7,4),
1465 ID_UNALLOCATED(7,5),
1466 ID_UNALLOCATED(7,6),
1467 ID_UNALLOCATED(7,7),
1469 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1470 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
1471 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1473 { SYS_DESC(SYS_RGSR_EL1), undef_access },
1474 { SYS_DESC(SYS_GCR_EL1), undef_access },
1476 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1477 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
1478 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1479 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1480 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1488 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1489 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1490 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1492 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1493 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1494 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1495 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1496 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1497 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1498 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1499 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1501 { SYS_DESC(SYS_TFSR_EL1), undef_access },
1502 { SYS_DESC(SYS_TFSRE0_EL1), undef_access },
1504 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1505 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1507 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
1508 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
1509 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
1510 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
1511 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
1512 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
1513 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
1514 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
1515 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
1516 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
1517 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
1518 /* PMBIDR_EL1 is not trapped */
1520 { PMU_SYS_REG(SYS_PMINTENSET_EL1),
1521 .access = access_pminten, .reg = PMINTENSET_EL1 },
1522 { PMU_SYS_REG(SYS_PMINTENCLR_EL1),
1523 .access = access_pminten, .reg = PMINTENSET_EL1 },
1524 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
1526 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1527 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1529 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1530 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1531 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1532 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1533 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1535 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1536 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1538 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1539 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1540 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1541 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1542 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1543 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1544 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1545 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1546 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1547 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1548 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1549 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1551 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1552 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1554 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1556 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1558 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1559 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1560 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1561 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1563 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
1564 .reset = reset_pmcr, .reg = PMCR_EL0 },
1565 { PMU_SYS_REG(SYS_PMCNTENSET_EL0),
1566 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1567 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),
1568 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1569 { PMU_SYS_REG(SYS_PMOVSCLR_EL0),
1570 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1571 { PMU_SYS_REG(SYS_PMSWINC_EL0),
1572 .access = access_pmswinc, .reg = PMSWINC_EL0 },
1573 { PMU_SYS_REG(SYS_PMSELR_EL0),
1574 .access = access_pmselr, .reg = PMSELR_EL0 },
1575 { PMU_SYS_REG(SYS_PMCEID0_EL0),
1576 .access = access_pmceid, .reset = NULL },
1577 { PMU_SYS_REG(SYS_PMCEID1_EL0),
1578 .access = access_pmceid, .reset = NULL },
1579 { PMU_SYS_REG(SYS_PMCCNTR_EL0),
1580 .access = access_pmu_evcntr, .reg = PMCCNTR_EL0 },
1581 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0),
1582 .access = access_pmu_evtyper, .reset = NULL },
1583 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0),
1584 .access = access_pmu_evcntr, .reset = NULL },
1586 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1587 * in 32bit mode. Here we choose to reset it as zero for consistency.
1589 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr,
1590 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
1591 { PMU_SYS_REG(SYS_PMOVSSET_EL0),
1592 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1594 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1595 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1597 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1599 { SYS_DESC(SYS_AMCR_EL0), undef_access },
1600 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1601 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1602 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1603 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1604 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1605 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1606 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
1607 AMU_AMEVCNTR0_EL0(0),
1608 AMU_AMEVCNTR0_EL0(1),
1609 AMU_AMEVCNTR0_EL0(2),
1610 AMU_AMEVCNTR0_EL0(3),
1611 AMU_AMEVCNTR0_EL0(4),
1612 AMU_AMEVCNTR0_EL0(5),
1613 AMU_AMEVCNTR0_EL0(6),
1614 AMU_AMEVCNTR0_EL0(7),
1615 AMU_AMEVCNTR0_EL0(8),
1616 AMU_AMEVCNTR0_EL0(9),
1617 AMU_AMEVCNTR0_EL0(10),
1618 AMU_AMEVCNTR0_EL0(11),
1619 AMU_AMEVCNTR0_EL0(12),
1620 AMU_AMEVCNTR0_EL0(13),
1621 AMU_AMEVCNTR0_EL0(14),
1622 AMU_AMEVCNTR0_EL0(15),
1623 AMU_AMEVTYPER0_EL0(0),
1624 AMU_AMEVTYPER0_EL0(1),
1625 AMU_AMEVTYPER0_EL0(2),
1626 AMU_AMEVTYPER0_EL0(3),
1627 AMU_AMEVTYPER0_EL0(4),
1628 AMU_AMEVTYPER0_EL0(5),
1629 AMU_AMEVTYPER0_EL0(6),
1630 AMU_AMEVTYPER0_EL0(7),
1631 AMU_AMEVTYPER0_EL0(8),
1632 AMU_AMEVTYPER0_EL0(9),
1633 AMU_AMEVTYPER0_EL0(10),
1634 AMU_AMEVTYPER0_EL0(11),
1635 AMU_AMEVTYPER0_EL0(12),
1636 AMU_AMEVTYPER0_EL0(13),
1637 AMU_AMEVTYPER0_EL0(14),
1638 AMU_AMEVTYPER0_EL0(15),
1639 AMU_AMEVCNTR1_EL0(0),
1640 AMU_AMEVCNTR1_EL0(1),
1641 AMU_AMEVCNTR1_EL0(2),
1642 AMU_AMEVCNTR1_EL0(3),
1643 AMU_AMEVCNTR1_EL0(4),
1644 AMU_AMEVCNTR1_EL0(5),
1645 AMU_AMEVCNTR1_EL0(6),
1646 AMU_AMEVCNTR1_EL0(7),
1647 AMU_AMEVCNTR1_EL0(8),
1648 AMU_AMEVCNTR1_EL0(9),
1649 AMU_AMEVCNTR1_EL0(10),
1650 AMU_AMEVCNTR1_EL0(11),
1651 AMU_AMEVCNTR1_EL0(12),
1652 AMU_AMEVCNTR1_EL0(13),
1653 AMU_AMEVCNTR1_EL0(14),
1654 AMU_AMEVCNTR1_EL0(15),
1655 AMU_AMEVTYPER1_EL0(0),
1656 AMU_AMEVTYPER1_EL0(1),
1657 AMU_AMEVTYPER1_EL0(2),
1658 AMU_AMEVTYPER1_EL0(3),
1659 AMU_AMEVTYPER1_EL0(4),
1660 AMU_AMEVTYPER1_EL0(5),
1661 AMU_AMEVTYPER1_EL0(6),
1662 AMU_AMEVTYPER1_EL0(7),
1663 AMU_AMEVTYPER1_EL0(8),
1664 AMU_AMEVTYPER1_EL0(9),
1665 AMU_AMEVTYPER1_EL0(10),
1666 AMU_AMEVTYPER1_EL0(11),
1667 AMU_AMEVTYPER1_EL0(12),
1668 AMU_AMEVTYPER1_EL0(13),
1669 AMU_AMEVTYPER1_EL0(14),
1670 AMU_AMEVTYPER1_EL0(15),
1672 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1673 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1674 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1677 PMU_PMEVCNTR_EL0(0),
1678 PMU_PMEVCNTR_EL0(1),
1679 PMU_PMEVCNTR_EL0(2),
1680 PMU_PMEVCNTR_EL0(3),
1681 PMU_PMEVCNTR_EL0(4),
1682 PMU_PMEVCNTR_EL0(5),
1683 PMU_PMEVCNTR_EL0(6),
1684 PMU_PMEVCNTR_EL0(7),
1685 PMU_PMEVCNTR_EL0(8),
1686 PMU_PMEVCNTR_EL0(9),
1687 PMU_PMEVCNTR_EL0(10),
1688 PMU_PMEVCNTR_EL0(11),
1689 PMU_PMEVCNTR_EL0(12),
1690 PMU_PMEVCNTR_EL0(13),
1691 PMU_PMEVCNTR_EL0(14),
1692 PMU_PMEVCNTR_EL0(15),
1693 PMU_PMEVCNTR_EL0(16),
1694 PMU_PMEVCNTR_EL0(17),
1695 PMU_PMEVCNTR_EL0(18),
1696 PMU_PMEVCNTR_EL0(19),
1697 PMU_PMEVCNTR_EL0(20),
1698 PMU_PMEVCNTR_EL0(21),
1699 PMU_PMEVCNTR_EL0(22),
1700 PMU_PMEVCNTR_EL0(23),
1701 PMU_PMEVCNTR_EL0(24),
1702 PMU_PMEVCNTR_EL0(25),
1703 PMU_PMEVCNTR_EL0(26),
1704 PMU_PMEVCNTR_EL0(27),
1705 PMU_PMEVCNTR_EL0(28),
1706 PMU_PMEVCNTR_EL0(29),
1707 PMU_PMEVCNTR_EL0(30),
1708 /* PMEVTYPERn_EL0 */
1709 PMU_PMEVTYPER_EL0(0),
1710 PMU_PMEVTYPER_EL0(1),
1711 PMU_PMEVTYPER_EL0(2),
1712 PMU_PMEVTYPER_EL0(3),
1713 PMU_PMEVTYPER_EL0(4),
1714 PMU_PMEVTYPER_EL0(5),
1715 PMU_PMEVTYPER_EL0(6),
1716 PMU_PMEVTYPER_EL0(7),
1717 PMU_PMEVTYPER_EL0(8),
1718 PMU_PMEVTYPER_EL0(9),
1719 PMU_PMEVTYPER_EL0(10),
1720 PMU_PMEVTYPER_EL0(11),
1721 PMU_PMEVTYPER_EL0(12),
1722 PMU_PMEVTYPER_EL0(13),
1723 PMU_PMEVTYPER_EL0(14),
1724 PMU_PMEVTYPER_EL0(15),
1725 PMU_PMEVTYPER_EL0(16),
1726 PMU_PMEVTYPER_EL0(17),
1727 PMU_PMEVTYPER_EL0(18),
1728 PMU_PMEVTYPER_EL0(19),
1729 PMU_PMEVTYPER_EL0(20),
1730 PMU_PMEVTYPER_EL0(21),
1731 PMU_PMEVTYPER_EL0(22),
1732 PMU_PMEVTYPER_EL0(23),
1733 PMU_PMEVTYPER_EL0(24),
1734 PMU_PMEVTYPER_EL0(25),
1735 PMU_PMEVTYPER_EL0(26),
1736 PMU_PMEVTYPER_EL0(27),
1737 PMU_PMEVTYPER_EL0(28),
1738 PMU_PMEVTYPER_EL0(29),
1739 PMU_PMEVTYPER_EL0(30),
1741 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1742 * in 32bit mode. Here we choose to reset it as zero for consistency.
1744 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper,
1745 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
1747 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1748 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1749 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1752 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
1753 struct sys_reg_params *p,
1754 const struct sys_reg_desc *r)
1757 return ignore_write(vcpu, p);
1759 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1760 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1761 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1763 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1764 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1765 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1766 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
1772 * AArch32 debug register mappings
1774 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1775 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1777 * None of the other registers share their location, so treat them as
1778 * if they were 64bit.
1780 #define DBG_BCR_BVR_WCR_WVR(n) \
1782 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1784 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1786 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1788 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1790 #define DBGBXVR(n) \
1791 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
1794 * Trapped cp14 registers. We generally ignore most of the external
1795 * debug, on the principle that they don't really make sense to a
1796 * guest. Revisit this one day, would this principle change.
1798 static const struct sys_reg_desc cp14_regs[] = {
1800 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
1802 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1804 DBG_BCR_BVR_WCR_WVR(0),
1806 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1807 DBG_BCR_BVR_WCR_WVR(1),
1809 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
1811 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
1812 DBG_BCR_BVR_WCR_WVR(2),
1813 /* DBGDTR[RT]Xint */
1814 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1815 /* DBGDTR[RT]Xext */
1816 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1817 DBG_BCR_BVR_WCR_WVR(3),
1818 DBG_BCR_BVR_WCR_WVR(4),
1819 DBG_BCR_BVR_WCR_WVR(5),
1821 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1823 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1824 DBG_BCR_BVR_WCR_WVR(6),
1826 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
1827 DBG_BCR_BVR_WCR_WVR(7),
1828 DBG_BCR_BVR_WCR_WVR(8),
1829 DBG_BCR_BVR_WCR_WVR(9),
1830 DBG_BCR_BVR_WCR_WVR(10),
1831 DBG_BCR_BVR_WCR_WVR(11),
1832 DBG_BCR_BVR_WCR_WVR(12),
1833 DBG_BCR_BVR_WCR_WVR(13),
1834 DBG_BCR_BVR_WCR_WVR(14),
1835 DBG_BCR_BVR_WCR_WVR(15),
1837 /* DBGDRAR (32bit) */
1838 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1842 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1845 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1849 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1852 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1865 /* DBGDSAR (32bit) */
1866 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1869 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1871 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1873 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1875 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1877 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1879 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1882 /* Trapped cp14 64bit registers */
1883 static const struct sys_reg_desc cp14_64_regs[] = {
1884 /* DBGDRAR (64bit) */
1885 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1887 /* DBGDSAR (64bit) */
1888 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1891 /* Macro to expand the PMEVCNTRn register */
1892 #define PMU_PMEVCNTR(n) \
1894 { Op1(0), CRn(0b1110), \
1895 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1898 /* Macro to expand the PMEVTYPERn register */
1899 #define PMU_PMEVTYPER(n) \
1901 { Op1(0), CRn(0b1110), \
1902 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1903 access_pmu_evtyper }
1906 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1907 * depending on the way they are accessed (as a 32bit or a 64bit
1910 static const struct sys_reg_desc cp15_regs[] = {
1911 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1912 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
1914 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
1916 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1917 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
1918 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
1920 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
1922 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
1923 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
1925 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
1926 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
1928 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
1930 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
1932 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
1934 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
1937 * DC{C,I,CI}SW operations:
1939 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1940 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1941 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1944 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1945 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1946 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1947 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1948 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1949 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1950 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1951 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1952 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1953 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1954 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1955 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1956 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1957 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1958 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1959 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
1960 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
1962 { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi },
1965 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
1967 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
1969 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
1971 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
1974 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1976 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
1979 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
1980 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2047 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2049 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2050 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2051 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2054 static const struct sys_reg_desc cp15_64_regs[] = {
2055 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2056 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2057 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2058 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2059 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2060 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2061 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2064 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2069 for (i = 0; i < n; i++) {
2070 if (!is_32 && table[i].reg && !table[i].reset) {
2071 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2076 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2077 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2085 static int match_sys_reg(const void *key, const void *elt)
2087 const unsigned long pval = (unsigned long)key;
2088 const struct sys_reg_desc *r = elt;
2090 return pval - reg_to_encoding(r);
2093 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2094 const struct sys_reg_desc table[],
2097 unsigned long pval = reg_to_encoding(params);
2099 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
2102 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2104 kvm_inject_undefined(vcpu);
2108 static void perform_access(struct kvm_vcpu *vcpu,
2109 struct sys_reg_params *params,
2110 const struct sys_reg_desc *r)
2112 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2114 /* Check for regs disabled by runtime config */
2115 if (sysreg_hidden(vcpu, r)) {
2116 kvm_inject_undefined(vcpu);
2121 * Not having an accessor means that we have configured a trap
2122 * that we don't know how to handle. This certainly qualifies
2123 * as a gross bug that should be fixed right away.
2127 /* Skip instruction if instructed so */
2128 if (likely(r->access(vcpu, params, r)))
2133 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2134 * call the corresponding trap handler.
2136 * @params: pointer to the descriptor of the access
2137 * @table: array of trap descriptors
2138 * @num: size of the trap descriptor array
2140 * Return 0 if the access has been handled, and -1 if not.
2142 static int emulate_cp(struct kvm_vcpu *vcpu,
2143 struct sys_reg_params *params,
2144 const struct sys_reg_desc *table,
2147 const struct sys_reg_desc *r;
2150 return -1; /* Not handled */
2152 r = find_reg(params, table, num);
2155 perform_access(vcpu, params, r);
2163 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2164 struct sys_reg_params *params)
2166 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2170 case ESR_ELx_EC_CP15_32:
2171 case ESR_ELx_EC_CP15_64:
2174 case ESR_ELx_EC_CP14_MR:
2175 case ESR_ELx_EC_CP14_64:
2182 print_sys_reg_msg(params,
2183 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2184 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2185 kvm_inject_undefined(vcpu);
2189 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2190 * @vcpu: The VCPU pointer
2191 * @run: The kvm_run struct
2193 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2194 const struct sys_reg_desc *global,
2197 struct sys_reg_params params;
2198 u32 esr = kvm_vcpu_get_esr(vcpu);
2199 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2200 int Rt2 = (esr >> 10) & 0x1f;
2202 params.CRm = (esr >> 1) & 0xf;
2203 params.is_write = ((esr & 1) == 0);
2206 params.Op1 = (esr >> 16) & 0xf;
2211 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2212 * backends between AArch32 and AArch64, we get away with it.
2214 if (params.is_write) {
2215 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2216 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2220 * If the table contains a handler, handle the
2221 * potential register operation in the case of a read and return
2224 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2225 /* Split up the value between registers for the read side */
2226 if (!params.is_write) {
2227 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2228 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2234 unhandled_cp_access(vcpu, ¶ms);
2239 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2240 * @vcpu: The VCPU pointer
2241 * @run: The kvm_run struct
2243 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2244 const struct sys_reg_desc *global,
2247 struct sys_reg_params params;
2248 u32 esr = kvm_vcpu_get_esr(vcpu);
2249 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2251 params.CRm = (esr >> 1) & 0xf;
2252 params.regval = vcpu_get_reg(vcpu, Rt);
2253 params.is_write = ((esr & 1) == 0);
2254 params.CRn = (esr >> 10) & 0xf;
2256 params.Op1 = (esr >> 14) & 0x7;
2257 params.Op2 = (esr >> 17) & 0x7;
2259 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2260 if (!params.is_write)
2261 vcpu_set_reg(vcpu, Rt, params.regval);
2265 unhandled_cp_access(vcpu, ¶ms);
2269 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
2271 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
2274 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
2276 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
2279 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
2281 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
2284 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
2286 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
2289 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2291 // See ARM DDI 0487E.a, section D12.3.2
2292 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2295 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2296 struct sys_reg_params *params)
2298 const struct sys_reg_desc *r;
2300 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2303 perform_access(vcpu, params, r);
2304 } else if (is_imp_def_sys_reg(params)) {
2305 kvm_inject_undefined(vcpu);
2307 print_sys_reg_msg(params,
2308 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2309 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2310 kvm_inject_undefined(vcpu);
2316 * kvm_reset_sys_regs - sets system registers to reset value
2317 * @vcpu: The VCPU pointer
2319 * This function finds the right table above and sets the registers on the
2320 * virtual CPU struct to their architecturally defined reset values.
2322 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2326 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2327 if (sys_reg_descs[i].reset)
2328 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
2332 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2333 * @vcpu: The VCPU pointer
2335 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
2337 struct sys_reg_params params;
2338 unsigned long esr = kvm_vcpu_get_esr(vcpu);
2339 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2342 trace_kvm_handle_sys_reg(esr);
2344 params.Op0 = (esr >> 20) & 3;
2345 params.Op1 = (esr >> 14) & 0x7;
2346 params.CRn = (esr >> 10) & 0xf;
2347 params.CRm = (esr >> 1) & 0xf;
2348 params.Op2 = (esr >> 17) & 0x7;
2349 params.regval = vcpu_get_reg(vcpu, Rt);
2350 params.is_write = !(esr & 1);
2352 ret = emulate_sys_reg(vcpu, ¶ms);
2354 if (!params.is_write)
2355 vcpu_set_reg(vcpu, Rt, params.regval);
2359 /******************************************************************************
2361 *****************************************************************************/
2363 static bool index_to_params(u64 id, struct sys_reg_params *params)
2365 switch (id & KVM_REG_SIZE_MASK) {
2366 case KVM_REG_SIZE_U64:
2367 /* Any unused index bits means it's not valid. */
2368 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2369 | KVM_REG_ARM_COPROC_MASK
2370 | KVM_REG_ARM64_SYSREG_OP0_MASK
2371 | KVM_REG_ARM64_SYSREG_OP1_MASK
2372 | KVM_REG_ARM64_SYSREG_CRN_MASK
2373 | KVM_REG_ARM64_SYSREG_CRM_MASK
2374 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2376 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2377 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2378 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2379 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2380 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2381 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2382 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2383 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2384 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2385 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2392 const struct sys_reg_desc *find_reg_by_id(u64 id,
2393 struct sys_reg_params *params,
2394 const struct sys_reg_desc table[],
2397 if (!index_to_params(id, params))
2400 return find_reg(params, table, num);
2403 /* Decode an index value, and find the sys_reg_desc entry. */
2404 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2407 const struct sys_reg_desc *r;
2408 struct sys_reg_params params;
2410 /* We only do sys_reg for now. */
2411 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2414 if (!index_to_params(id, ¶ms))
2417 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2419 /* Not saved in the sys_reg array and not otherwise accessible? */
2420 if (r && !(r->reg || r->get_user))
2427 * These are the invariant sys_reg registers: we let the guest see the
2428 * host versions of these, so they're part of the guest state.
2430 * A future CPU may provide a mechanism to present different values to
2431 * the guest, or a future kvm may trap them.
2434 #define FUNCTION_INVARIANT(reg) \
2435 static void get_##reg(struct kvm_vcpu *v, \
2436 const struct sys_reg_desc *r) \
2438 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2441 FUNCTION_INVARIANT(midr_el1)
2442 FUNCTION_INVARIANT(revidr_el1)
2443 FUNCTION_INVARIANT(clidr_el1)
2444 FUNCTION_INVARIANT(aidr_el1)
2446 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2448 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2451 /* ->val is filled in by kvm_sys_reg_table_init() */
2452 static struct sys_reg_desc invariant_sys_regs[] = {
2453 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2454 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2455 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2456 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2457 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2460 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2462 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2467 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2469 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2474 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2476 struct sys_reg_params params;
2477 const struct sys_reg_desc *r;
2479 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2480 ARRAY_SIZE(invariant_sys_regs));
2484 return reg_to_user(uaddr, &r->val, id);
2487 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2489 struct sys_reg_params params;
2490 const struct sys_reg_desc *r;
2492 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2494 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2495 ARRAY_SIZE(invariant_sys_regs));
2499 err = reg_from_user(&val, uaddr, id);
2503 /* This is what we mean by invariant: you can't change it. */
2510 static bool is_valid_cache(u32 val)
2514 if (val >= CSSELR_MAX)
2517 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2519 ctype = (cache_levels >> (level * 3)) & 7;
2522 case 0: /* No cache */
2524 case 1: /* Instruction cache only */
2526 case 2: /* Data cache only */
2527 case 4: /* Unified cache */
2529 case 3: /* Separate instruction and data caches */
2531 default: /* Reserved: we can't know instruction or data. */
2536 static int demux_c15_get(u64 id, void __user *uaddr)
2539 u32 __user *uval = uaddr;
2541 /* Fail if we have unknown bits set. */
2542 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2543 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2546 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2547 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2548 if (KVM_REG_SIZE(id) != 4)
2550 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2551 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2552 if (!is_valid_cache(val))
2555 return put_user(get_ccsidr(val), uval);
2561 static int demux_c15_set(u64 id, void __user *uaddr)
2564 u32 __user *uval = uaddr;
2566 /* Fail if we have unknown bits set. */
2567 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2568 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2571 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2572 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2573 if (KVM_REG_SIZE(id) != 4)
2575 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2576 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2577 if (!is_valid_cache(val))
2580 if (get_user(newval, uval))
2583 /* This is also invariant: you can't change it. */
2584 if (newval != get_ccsidr(val))
2592 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2594 const struct sys_reg_desc *r;
2595 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2597 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2598 return demux_c15_get(reg->id, uaddr);
2600 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2603 r = index_to_sys_reg_desc(vcpu, reg->id);
2605 return get_invariant_sys_reg(reg->id, uaddr);
2607 /* Check for regs disabled by runtime config */
2608 if (sysreg_hidden(vcpu, r))
2612 return (r->get_user)(vcpu, r, reg, uaddr);
2614 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2617 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2619 const struct sys_reg_desc *r;
2620 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2622 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2623 return demux_c15_set(reg->id, uaddr);
2625 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2628 r = index_to_sys_reg_desc(vcpu, reg->id);
2630 return set_invariant_sys_reg(reg->id, uaddr);
2632 /* Check for regs disabled by runtime config */
2633 if (sysreg_hidden(vcpu, r))
2637 return (r->set_user)(vcpu, r, reg, uaddr);
2639 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2642 static unsigned int num_demux_regs(void)
2644 unsigned int i, count = 0;
2646 for (i = 0; i < CSSELR_MAX; i++)
2647 if (is_valid_cache(i))
2653 static int write_demux_regids(u64 __user *uindices)
2655 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2658 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2659 for (i = 0; i < CSSELR_MAX; i++) {
2660 if (!is_valid_cache(i))
2662 if (put_user(val | i, uindices))
2669 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2671 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2672 KVM_REG_ARM64_SYSREG |
2673 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2674 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2675 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2676 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2677 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2680 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2685 if (put_user(sys_reg_to_index(reg), *uind))
2692 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2693 const struct sys_reg_desc *rd,
2695 unsigned int *total)
2698 * Ignore registers we trap but don't save,
2699 * and for which no custom user accessor is provided.
2701 if (!(rd->reg || rd->get_user))
2704 if (sysreg_hidden(vcpu, rd))
2707 if (!copy_reg_to_user(rd, uind))
2714 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2715 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2717 const struct sys_reg_desc *i2, *end2;
2718 unsigned int total = 0;
2722 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2724 while (i2 != end2) {
2725 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
2732 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2734 return ARRAY_SIZE(invariant_sys_regs)
2736 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2739 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2744 /* Then give them all the invariant registers' indices. */
2745 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2746 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2751 err = walk_sys_regs(vcpu, uindices);
2756 return write_demux_regids(uindices);
2759 void kvm_sys_reg_table_init(void)
2762 struct sys_reg_desc clidr;
2764 /* Make sure tables are unique and in order. */
2765 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2766 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2767 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2768 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2769 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2770 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
2772 /* We abuse the reset function to overwrite the table itself. */
2773 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2774 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2777 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2779 * If software reads the Cache Type fields from Ctype1
2780 * upwards, once it has seen a value of 0b000, no caches
2781 * exist at further-out levels of the hierarchy. So, for
2782 * example, if Ctype3 is the first Cache Type field with a
2783 * value of 0b000, the values of Ctype4 to Ctype7 must be
2786 get_clidr_el1(NULL, &clidr); /* Ugly... */
2787 cache_levels = clidr.val;
2788 for (i = 0; i < 7; i++)
2789 if (((cache_levels >> (i*3)) & 7) == 0)
2791 /* Clear all higher bits. */
2792 cache_levels &= (1 << (i*3))-1;