1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
12 #include <linux/bsearch.h>
13 #include <linux/kvm_host.h>
15 #include <linux/printk.h>
16 #include <linux/uaccess.h>
18 #include <asm/cacheflush.h>
19 #include <asm/cputype.h>
20 #include <asm/debug-monitors.h>
22 #include <asm/kvm_arm.h>
23 #include <asm/kvm_coproc.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_host.h>
26 #include <asm/kvm_hyp.h>
27 #include <asm/kvm_mmu.h>
28 #include <asm/perf_event.h>
29 #include <asm/sysreg.h>
31 #include <trace/events/kvm.h>
38 * All of this file is extremly similar to the ARM coproc.c, but the
39 * types are different. My gut feeling is that it should be pretty
40 * easy to merge, but that would be an ABI breakage -- again. VFP
41 * would also need to be abstracted.
43 * For AArch32, we only take care of what is being trapped. Anything
44 * that has to do with init and userspace access has to go via the
48 static bool read_from_write_only(struct kvm_vcpu *vcpu,
49 struct sys_reg_params *params,
50 const struct sys_reg_desc *r)
52 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
53 print_sys_reg_instr(params);
54 kvm_inject_undefined(vcpu);
58 static bool write_to_read_only(struct kvm_vcpu *vcpu,
59 struct sys_reg_params *params,
60 const struct sys_reg_desc *r)
62 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
63 print_sys_reg_instr(params);
64 kvm_inject_undefined(vcpu);
68 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
70 if (!vcpu->arch.sysregs_loaded_on_cpu)
74 * System registers listed in the switch are not saved on every
75 * exit from the guest but are only saved on vcpu_put.
77 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
78 * should never be listed below, because the guest cannot modify its
79 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
80 * thread when emulating cross-VCPU communication.
83 case CSSELR_EL1: return read_sysreg_s(SYS_CSSELR_EL1);
84 case SCTLR_EL1: return read_sysreg_s(SYS_SCTLR_EL12);
85 case ACTLR_EL1: return read_sysreg_s(SYS_ACTLR_EL1);
86 case CPACR_EL1: return read_sysreg_s(SYS_CPACR_EL12);
87 case TTBR0_EL1: return read_sysreg_s(SYS_TTBR0_EL12);
88 case TTBR1_EL1: return read_sysreg_s(SYS_TTBR1_EL12);
89 case TCR_EL1: return read_sysreg_s(SYS_TCR_EL12);
90 case ESR_EL1: return read_sysreg_s(SYS_ESR_EL12);
91 case AFSR0_EL1: return read_sysreg_s(SYS_AFSR0_EL12);
92 case AFSR1_EL1: return read_sysreg_s(SYS_AFSR1_EL12);
93 case FAR_EL1: return read_sysreg_s(SYS_FAR_EL12);
94 case MAIR_EL1: return read_sysreg_s(SYS_MAIR_EL12);
95 case VBAR_EL1: return read_sysreg_s(SYS_VBAR_EL12);
96 case CONTEXTIDR_EL1: return read_sysreg_s(SYS_CONTEXTIDR_EL12);
97 case TPIDR_EL0: return read_sysreg_s(SYS_TPIDR_EL0);
98 case TPIDRRO_EL0: return read_sysreg_s(SYS_TPIDRRO_EL0);
99 case TPIDR_EL1: return read_sysreg_s(SYS_TPIDR_EL1);
100 case AMAIR_EL1: return read_sysreg_s(SYS_AMAIR_EL12);
101 case CNTKCTL_EL1: return read_sysreg_s(SYS_CNTKCTL_EL12);
102 case PAR_EL1: return read_sysreg_s(SYS_PAR_EL1);
103 case DACR32_EL2: return read_sysreg_s(SYS_DACR32_EL2);
104 case IFSR32_EL2: return read_sysreg_s(SYS_IFSR32_EL2);
105 case DBGVCR32_EL2: return read_sysreg_s(SYS_DBGVCR32_EL2);
109 return __vcpu_sys_reg(vcpu, reg);
112 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
114 if (!vcpu->arch.sysregs_loaded_on_cpu)
115 goto immediate_write;
118 * System registers listed in the switch are not restored on every
119 * entry to the guest but are only restored on vcpu_load.
121 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
122 * should never be listed below, because the the MPIDR should only be
123 * set once, before running the VCPU, and never changed later.
126 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); return;
127 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); return;
128 case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); return;
129 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); return;
130 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); return;
131 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); return;
132 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); return;
133 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); return;
134 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); return;
135 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); return;
136 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); return;
137 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); return;
138 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); return;
139 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12); return;
140 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); return;
141 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); return;
142 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); return;
143 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); return;
144 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); return;
145 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); return;
146 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); return;
147 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); return;
148 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); return;
152 __vcpu_sys_reg(vcpu, reg) = val;
155 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
156 static u32 cache_levels;
158 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
159 #define CSSELR_MAX 12
161 /* Which cache CCSIDR represents depends on CSSELR value. */
162 static u32 get_ccsidr(u32 csselr)
166 /* Make sure noone else changes CSSELR during this! */
168 write_sysreg(csselr, csselr_el1);
170 ccsidr = read_sysreg(ccsidr_el1);
177 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
179 static bool access_dcsw(struct kvm_vcpu *vcpu,
180 struct sys_reg_params *p,
181 const struct sys_reg_desc *r)
184 return read_from_write_only(vcpu, p, r);
187 * Only track S/W ops if we don't have FWB. It still indicates
188 * that the guest is a bit broken (S/W operations should only
189 * be done by firmware, knowing that there is only a single
190 * CPU left in the system, and certainly not from non-secure
193 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
194 kvm_set_way_flush(vcpu);
200 * Generic accessor for VM registers. Only called as long as HCR_TVM
201 * is set. If the guest enables the MMU, we stop trapping the VM
202 * sys_regs and leave it in complete control of the caches.
204 static bool access_vm_reg(struct kvm_vcpu *vcpu,
205 struct sys_reg_params *p,
206 const struct sys_reg_desc *r)
208 bool was_enabled = vcpu_has_cache_enabled(vcpu);
212 BUG_ON(!p->is_write);
214 /* See the 32bit mapping in kvm_host.h */
218 if (!p->is_aarch32 || !p->is_32bit) {
221 val = vcpu_read_sys_reg(vcpu, reg);
223 val = (p->regval << 32) | (u64)lower_32_bits(val);
225 val = ((u64)upper_32_bits(val) << 32) |
226 lower_32_bits(p->regval);
228 vcpu_write_sys_reg(vcpu, val, reg);
230 kvm_toggle_cache(vcpu, was_enabled);
235 * Trap handler for the GICv3 SGI generation system register.
236 * Forward the request to the VGIC emulation.
237 * The cp15_64 code makes sure this automatically works
238 * for both AArch64 and AArch32 accesses.
240 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
241 struct sys_reg_params *p,
242 const struct sys_reg_desc *r)
247 return read_from_write_only(vcpu, p, r);
250 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
251 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
252 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
253 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
258 default: /* Keep GCC quiet */
259 case 0: /* ICC_SGI1R */
262 case 1: /* ICC_ASGI1R */
263 case 2: /* ICC_SGI0R */
269 default: /* Keep GCC quiet */
270 case 5: /* ICC_SGI1R_EL1 */
273 case 6: /* ICC_ASGI1R_EL1 */
274 case 7: /* ICC_SGI0R_EL1 */
280 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
285 static bool access_gic_sre(struct kvm_vcpu *vcpu,
286 struct sys_reg_params *p,
287 const struct sys_reg_desc *r)
290 return ignore_write(vcpu, p);
292 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
296 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
297 struct sys_reg_params *p,
298 const struct sys_reg_desc *r)
301 return ignore_write(vcpu, p);
303 return read_zero(vcpu, p);
307 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
308 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
309 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
310 * treat it separately.
312 static bool trap_loregion(struct kvm_vcpu *vcpu,
313 struct sys_reg_params *p,
314 const struct sys_reg_desc *r)
316 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
317 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
318 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
320 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
321 kvm_inject_undefined(vcpu);
325 if (p->is_write && sr == SYS_LORID_EL1)
326 return write_to_read_only(vcpu, p, r);
328 return trap_raz_wi(vcpu, p, r);
331 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
332 struct sys_reg_params *p,
333 const struct sys_reg_desc *r)
336 return ignore_write(vcpu, p);
338 p->regval = (1 << 3);
343 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
344 struct sys_reg_params *p,
345 const struct sys_reg_desc *r)
348 return ignore_write(vcpu, p);
350 p->regval = read_sysreg(dbgauthstatus_el1);
356 * We want to avoid world-switching all the DBG registers all the
359 * - If we've touched any debug register, it is likely that we're
360 * going to touch more of them. It then makes sense to disable the
361 * traps and start doing the save/restore dance
362 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
363 * then mandatory to save/restore the registers, as the guest
366 * For this, we use a DIRTY bit, indicating the guest has modified the
367 * debug registers, used as follow:
370 * - If the dirty bit is set (because we're coming back from trapping),
371 * disable the traps, save host registers, restore guest registers.
372 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
373 * set the dirty bit, disable the traps, save host registers,
374 * restore guest registers.
375 * - Otherwise, enable the traps
378 * - If the dirty bit is set, save guest registers, restore host
379 * registers and clear the dirty bit. This ensure that the host can
380 * now use the debug registers.
382 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
383 struct sys_reg_params *p,
384 const struct sys_reg_desc *r)
387 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
388 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
390 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
393 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
399 * reg_to_dbg/dbg_to_reg
401 * A 32 bit write to a debug register leave top bits alone
402 * A 32 bit read from a debug register only returns the bottom bits
404 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
405 * hyp.S code switches between host and guest values in future.
407 static void reg_to_dbg(struct kvm_vcpu *vcpu,
408 struct sys_reg_params *p,
415 val |= ((*dbg_reg >> 32) << 32);
419 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
422 static void dbg_to_reg(struct kvm_vcpu *vcpu,
423 struct sys_reg_params *p,
426 p->regval = *dbg_reg;
428 p->regval &= 0xffffffffUL;
431 static bool trap_bvr(struct kvm_vcpu *vcpu,
432 struct sys_reg_params *p,
433 const struct sys_reg_desc *rd)
435 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
438 reg_to_dbg(vcpu, p, dbg_reg);
440 dbg_to_reg(vcpu, p, dbg_reg);
442 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
447 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
448 const struct kvm_one_reg *reg, void __user *uaddr)
450 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
452 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
457 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
458 const struct kvm_one_reg *reg, void __user *uaddr)
460 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
462 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
467 static void reset_bvr(struct kvm_vcpu *vcpu,
468 const struct sys_reg_desc *rd)
470 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
473 static bool trap_bcr(struct kvm_vcpu *vcpu,
474 struct sys_reg_params *p,
475 const struct sys_reg_desc *rd)
477 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
480 reg_to_dbg(vcpu, p, dbg_reg);
482 dbg_to_reg(vcpu, p, dbg_reg);
484 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
489 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
490 const struct kvm_one_reg *reg, void __user *uaddr)
492 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
494 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
500 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
501 const struct kvm_one_reg *reg, void __user *uaddr)
503 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
505 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
510 static void reset_bcr(struct kvm_vcpu *vcpu,
511 const struct sys_reg_desc *rd)
513 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
516 static bool trap_wvr(struct kvm_vcpu *vcpu,
517 struct sys_reg_params *p,
518 const struct sys_reg_desc *rd)
520 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
523 reg_to_dbg(vcpu, p, dbg_reg);
525 dbg_to_reg(vcpu, p, dbg_reg);
527 trace_trap_reg(__func__, rd->reg, p->is_write,
528 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
533 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
534 const struct kvm_one_reg *reg, void __user *uaddr)
536 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
538 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
543 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
544 const struct kvm_one_reg *reg, void __user *uaddr)
546 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
548 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
553 static void reset_wvr(struct kvm_vcpu *vcpu,
554 const struct sys_reg_desc *rd)
556 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
559 static bool trap_wcr(struct kvm_vcpu *vcpu,
560 struct sys_reg_params *p,
561 const struct sys_reg_desc *rd)
563 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
566 reg_to_dbg(vcpu, p, dbg_reg);
568 dbg_to_reg(vcpu, p, dbg_reg);
570 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
575 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
576 const struct kvm_one_reg *reg, void __user *uaddr)
578 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
580 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
585 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
586 const struct kvm_one_reg *reg, void __user *uaddr)
588 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
590 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
595 static void reset_wcr(struct kvm_vcpu *vcpu,
596 const struct sys_reg_desc *rd)
598 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
601 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
603 u64 amair = read_sysreg(amair_el1);
604 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
607 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
612 * Map the vcpu_id into the first three affinity level fields of
613 * the MPIDR. We limit the number of VCPUs in level 0 due to a
614 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
615 * of the GICv3 to be able to address each CPU directly when
618 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
619 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
620 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
621 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
624 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
628 pmcr = read_sysreg(pmcr_el0);
630 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
631 * except PMCR.E resetting to zero.
633 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
634 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
635 __vcpu_sys_reg(vcpu, r->reg) = val;
638 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
640 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
641 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
644 kvm_inject_undefined(vcpu);
649 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
651 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
654 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
656 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
659 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
661 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
664 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
666 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
669 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
670 const struct sys_reg_desc *r)
674 if (!kvm_arm_pmu_v3_ready(vcpu))
675 return trap_raz_wi(vcpu, p, r);
677 if (pmu_access_el0_disabled(vcpu))
681 /* Only update writeable bits of PMCR */
682 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
683 val &= ~ARMV8_PMU_PMCR_MASK;
684 val |= p->regval & ARMV8_PMU_PMCR_MASK;
685 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
686 kvm_pmu_handle_pmcr(vcpu, val);
687 kvm_vcpu_pmu_restore_guest(vcpu);
689 /* PMCR.P & PMCR.C are RAZ */
690 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
691 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
698 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
699 const struct sys_reg_desc *r)
701 if (!kvm_arm_pmu_v3_ready(vcpu))
702 return trap_raz_wi(vcpu, p, r);
704 if (pmu_access_event_counter_el0_disabled(vcpu))
708 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
710 /* return PMSELR.SEL field */
711 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
712 & ARMV8_PMU_COUNTER_MASK;
717 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
718 const struct sys_reg_desc *r)
722 if (!kvm_arm_pmu_v3_ready(vcpu))
723 return trap_raz_wi(vcpu, p, r);
727 if (pmu_access_el0_disabled(vcpu))
731 pmceid = read_sysreg(pmceid0_el0);
733 pmceid = read_sysreg(pmceid1_el0);
740 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
744 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
745 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
746 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
747 kvm_inject_undefined(vcpu);
754 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
755 struct sys_reg_params *p,
756 const struct sys_reg_desc *r)
760 if (!kvm_arm_pmu_v3_ready(vcpu))
761 return trap_raz_wi(vcpu, p, r);
763 if (r->CRn == 9 && r->CRm == 13) {
766 if (pmu_access_event_counter_el0_disabled(vcpu))
769 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
770 & ARMV8_PMU_COUNTER_MASK;
771 } else if (r->Op2 == 0) {
773 if (pmu_access_cycle_counter_el0_disabled(vcpu))
776 idx = ARMV8_PMU_CYCLE_IDX;
780 } else if (r->CRn == 0 && r->CRm == 9) {
782 if (pmu_access_event_counter_el0_disabled(vcpu))
785 idx = ARMV8_PMU_CYCLE_IDX;
786 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
788 if (pmu_access_event_counter_el0_disabled(vcpu))
791 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
796 if (!pmu_counter_idx_valid(vcpu, idx))
800 if (pmu_access_el0_disabled(vcpu))
803 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
805 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
811 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
812 const struct sys_reg_desc *r)
816 if (!kvm_arm_pmu_v3_ready(vcpu))
817 return trap_raz_wi(vcpu, p, r);
819 if (pmu_access_el0_disabled(vcpu))
822 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
824 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
825 reg = PMEVTYPER0_EL0 + idx;
826 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
827 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
828 if (idx == ARMV8_PMU_CYCLE_IDX)
832 reg = PMEVTYPER0_EL0 + idx;
837 if (!pmu_counter_idx_valid(vcpu, idx))
841 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
842 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
843 kvm_vcpu_pmu_restore_guest(vcpu);
845 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
851 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
852 const struct sys_reg_desc *r)
856 if (!kvm_arm_pmu_v3_ready(vcpu))
857 return trap_raz_wi(vcpu, p, r);
859 if (pmu_access_el0_disabled(vcpu))
862 mask = kvm_pmu_valid_counter_mask(vcpu);
864 val = p->regval & mask;
866 /* accessing PMCNTENSET_EL0 */
867 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
868 kvm_pmu_enable_counter_mask(vcpu, val);
869 kvm_vcpu_pmu_restore_guest(vcpu);
871 /* accessing PMCNTENCLR_EL0 */
872 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
873 kvm_pmu_disable_counter_mask(vcpu, val);
876 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
882 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
883 const struct sys_reg_desc *r)
885 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
887 if (!kvm_arm_pmu_v3_ready(vcpu))
888 return trap_raz_wi(vcpu, p, r);
890 if (!vcpu_mode_priv(vcpu)) {
891 kvm_inject_undefined(vcpu);
896 u64 val = p->regval & mask;
899 /* accessing PMINTENSET_EL1 */
900 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
902 /* accessing PMINTENCLR_EL1 */
903 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
905 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
911 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
912 const struct sys_reg_desc *r)
914 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
916 if (!kvm_arm_pmu_v3_ready(vcpu))
917 return trap_raz_wi(vcpu, p, r);
919 if (pmu_access_el0_disabled(vcpu))
924 /* accessing PMOVSSET_EL0 */
925 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
927 /* accessing PMOVSCLR_EL0 */
928 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
930 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
936 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
937 const struct sys_reg_desc *r)
941 if (!kvm_arm_pmu_v3_ready(vcpu))
942 return trap_raz_wi(vcpu, p, r);
945 return read_from_write_only(vcpu, p, r);
947 if (pmu_write_swinc_el0_disabled(vcpu))
950 mask = kvm_pmu_valid_counter_mask(vcpu);
951 kvm_pmu_software_increment(vcpu, p->regval & mask);
955 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
956 const struct sys_reg_desc *r)
958 if (!kvm_arm_pmu_v3_ready(vcpu))
959 return trap_raz_wi(vcpu, p, r);
962 if (!vcpu_mode_priv(vcpu)) {
963 kvm_inject_undefined(vcpu);
967 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
968 p->regval & ARMV8_PMU_USERENR_MASK;
970 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
971 & ARMV8_PMU_USERENR_MASK;
977 #define reg_to_encoding(x) \
978 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
979 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
981 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
982 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
983 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
984 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
985 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
986 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
987 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
988 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
989 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
990 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
992 /* Macro to expand the PMEVCNTRn_EL0 register */
993 #define PMU_PMEVCNTR_EL0(n) \
994 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
995 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
997 /* Macro to expand the PMEVTYPERn_EL0 register */
998 #define PMU_PMEVTYPER_EL0(n) \
999 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
1000 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
1002 static bool trap_ptrauth(struct kvm_vcpu *vcpu,
1003 struct sys_reg_params *p,
1004 const struct sys_reg_desc *rd)
1006 kvm_arm_vcpu_ptrauth_trap(vcpu);
1009 * Return false for both cases as we never skip the trapped
1012 * - Either we re-execute the same key register access instruction
1013 * after enabling ptrauth.
1014 * - Or an UNDEF is injected as ptrauth is not supported/enabled.
1019 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1020 const struct sys_reg_desc *rd)
1022 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1025 #define __PTRAUTH_KEY(k) \
1026 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \
1027 .visibility = ptrauth_visibility}
1029 #define PTRAUTH_KEY(k) \
1030 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1031 __PTRAUTH_KEY(k ## KEYHI_EL1)
1033 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1034 struct sys_reg_params *p,
1035 const struct sys_reg_desc *r)
1037 enum kvm_arch_timers tmr;
1038 enum kvm_arch_timer_regs treg;
1039 u64 reg = reg_to_encoding(r);
1042 case SYS_CNTP_TVAL_EL0:
1043 case SYS_AARCH32_CNTP_TVAL:
1045 treg = TIMER_REG_TVAL;
1047 case SYS_CNTP_CTL_EL0:
1048 case SYS_AARCH32_CNTP_CTL:
1050 treg = TIMER_REG_CTL;
1052 case SYS_CNTP_CVAL_EL0:
1053 case SYS_AARCH32_CNTP_CVAL:
1055 treg = TIMER_REG_CVAL;
1062 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1064 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1069 /* Read a sanitised cpufeature ID register by sys_reg_desc */
1070 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1071 struct sys_reg_desc const *r, bool raz)
1073 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1074 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1075 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1077 if (id == SYS_ID_AA64PFR0_EL1 && !vcpu_has_sve(vcpu)) {
1078 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1079 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
1080 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1081 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1082 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1083 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
1089 /* cpufeature ID register access trap handlers */
1091 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1092 struct sys_reg_params *p,
1093 const struct sys_reg_desc *r,
1097 return write_to_read_only(vcpu, p, r);
1099 p->regval = read_id_reg(vcpu, r, raz);
1103 static bool access_id_reg(struct kvm_vcpu *vcpu,
1104 struct sys_reg_params *p,
1105 const struct sys_reg_desc *r)
1107 return __access_id_reg(vcpu, p, r, false);
1110 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1111 struct sys_reg_params *p,
1112 const struct sys_reg_desc *r)
1114 return __access_id_reg(vcpu, p, r, true);
1117 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1118 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1119 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1121 /* Visibility overrides for SVE-specific control registers */
1122 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1123 const struct sys_reg_desc *rd)
1125 if (vcpu_has_sve(vcpu))
1128 return REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1131 /* Visibility overrides for SVE-specific ID registers */
1132 static unsigned int sve_id_visibility(const struct kvm_vcpu *vcpu,
1133 const struct sys_reg_desc *rd)
1135 if (vcpu_has_sve(vcpu))
1138 return REG_HIDDEN_USER;
1141 /* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */
1142 static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu)
1144 if (!vcpu_has_sve(vcpu))
1147 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1);
1150 static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1151 struct sys_reg_params *p,
1152 const struct sys_reg_desc *rd)
1155 return write_to_read_only(vcpu, p, rd);
1157 p->regval = guest_id_aa64zfr0_el1(vcpu);
1161 static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1162 const struct sys_reg_desc *rd,
1163 const struct kvm_one_reg *reg, void __user *uaddr)
1167 if (WARN_ON(!vcpu_has_sve(vcpu)))
1170 val = guest_id_aa64zfr0_el1(vcpu);
1171 return reg_to_user(uaddr, &val, reg->id);
1174 static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1175 const struct sys_reg_desc *rd,
1176 const struct kvm_one_reg *reg, void __user *uaddr)
1178 const u64 id = sys_reg_to_index(rd);
1182 if (WARN_ON(!vcpu_has_sve(vcpu)))
1185 err = reg_from_user(&val, uaddr, id);
1189 /* This is what we mean by invariant: you can't change it. */
1190 if (val != guest_id_aa64zfr0_el1(vcpu))
1197 * cpufeature ID register user accessors
1199 * For now, these registers are immutable for userspace, so no values
1200 * are stored, and for set_id_reg() we don't allow the effective value
1203 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1204 const struct sys_reg_desc *rd, void __user *uaddr,
1207 const u64 id = sys_reg_to_index(rd);
1208 const u64 val = read_id_reg(vcpu, rd, raz);
1210 return reg_to_user(uaddr, &val, id);
1213 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1214 const struct sys_reg_desc *rd, void __user *uaddr,
1217 const u64 id = sys_reg_to_index(rd);
1221 err = reg_from_user(&val, uaddr, id);
1225 /* This is what we mean by invariant: you can't change it. */
1226 if (val != read_id_reg(vcpu, rd, raz))
1232 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1233 const struct kvm_one_reg *reg, void __user *uaddr)
1235 return __get_id_reg(vcpu, rd, uaddr, false);
1238 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1239 const struct kvm_one_reg *reg, void __user *uaddr)
1241 return __set_id_reg(vcpu, rd, uaddr, false);
1244 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1245 const struct kvm_one_reg *reg, void __user *uaddr)
1247 return __get_id_reg(vcpu, rd, uaddr, true);
1250 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1251 const struct kvm_one_reg *reg, void __user *uaddr)
1253 return __set_id_reg(vcpu, rd, uaddr, true);
1256 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1257 const struct sys_reg_desc *r)
1260 return write_to_read_only(vcpu, p, r);
1262 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1266 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1267 const struct sys_reg_desc *r)
1270 return write_to_read_only(vcpu, p, r);
1272 p->regval = read_sysreg(clidr_el1);
1276 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1277 const struct sys_reg_desc *r)
1280 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
1282 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
1286 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1287 const struct sys_reg_desc *r)
1292 return write_to_read_only(vcpu, p, r);
1294 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1295 p->regval = get_ccsidr(csselr);
1298 * Guests should not be doing cache operations by set/way at all, and
1299 * for this reason, we trap them and attempt to infer the intent, so
1300 * that we can flush the entire guest's address space at the appropriate
1302 * To prevent this trapping from causing performance problems, let's
1303 * expose the geometry of all data and unified caches (which are
1304 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1305 * [If guests should attempt to infer aliasing properties from the
1306 * geometry (which is not permitted by the architecture), they would
1307 * only do so for virtually indexed caches.]
1309 if (!(csselr & 1)) // data or unified cache
1310 p->regval &= ~GENMASK(27, 3);
1314 /* sys_reg_desc initialiser for known cpufeature ID registers */
1315 #define ID_SANITISED(name) { \
1316 SYS_DESC(SYS_##name), \
1317 .access = access_id_reg, \
1318 .get_user = get_id_reg, \
1319 .set_user = set_id_reg, \
1323 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1324 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1325 * (1 <= crm < 8, 0 <= Op2 < 8).
1327 #define ID_UNALLOCATED(crm, op2) { \
1328 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1329 .access = access_raz_id_reg, \
1330 .get_user = get_raz_id_reg, \
1331 .set_user = set_raz_id_reg, \
1335 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1336 * For now, these are exposed just like unallocated ID regs: they appear
1337 * RAZ for the guest.
1339 #define ID_HIDDEN(name) { \
1340 SYS_DESC(SYS_##name), \
1341 .access = access_raz_id_reg, \
1342 .get_user = get_raz_id_reg, \
1343 .set_user = set_raz_id_reg, \
1347 * Architected system registers.
1348 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1350 * Debug handling: We do trap most, if not all debug related system
1351 * registers. The implementation is good enough to ensure that a guest
1352 * can use these with minimal performance degradation. The drawback is
1353 * that we don't implement any of the external debug, none of the
1354 * OSlock protocol. This should be revisited if we ever encounter a
1355 * more demanding guest...
1357 static const struct sys_reg_desc sys_reg_descs[] = {
1358 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1359 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1360 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1362 DBG_BCR_BVR_WCR_WVR_EL1(0),
1363 DBG_BCR_BVR_WCR_WVR_EL1(1),
1364 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1365 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1366 DBG_BCR_BVR_WCR_WVR_EL1(2),
1367 DBG_BCR_BVR_WCR_WVR_EL1(3),
1368 DBG_BCR_BVR_WCR_WVR_EL1(4),
1369 DBG_BCR_BVR_WCR_WVR_EL1(5),
1370 DBG_BCR_BVR_WCR_WVR_EL1(6),
1371 DBG_BCR_BVR_WCR_WVR_EL1(7),
1372 DBG_BCR_BVR_WCR_WVR_EL1(8),
1373 DBG_BCR_BVR_WCR_WVR_EL1(9),
1374 DBG_BCR_BVR_WCR_WVR_EL1(10),
1375 DBG_BCR_BVR_WCR_WVR_EL1(11),
1376 DBG_BCR_BVR_WCR_WVR_EL1(12),
1377 DBG_BCR_BVR_WCR_WVR_EL1(13),
1378 DBG_BCR_BVR_WCR_WVR_EL1(14),
1379 DBG_BCR_BVR_WCR_WVR_EL1(15),
1381 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1382 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1383 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1384 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1385 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1386 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1387 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1388 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1390 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1391 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1392 // DBGDTR[TR]X_EL0 share the same encoding
1393 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1395 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1397 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1400 * ID regs: all ID_SANITISED() entries here must have corresponding
1401 * entries in arm64_ftr_regs[].
1404 /* AArch64 mappings of the AArch32 ID registers */
1406 ID_SANITISED(ID_PFR0_EL1),
1407 ID_SANITISED(ID_PFR1_EL1),
1408 ID_SANITISED(ID_DFR0_EL1),
1409 ID_HIDDEN(ID_AFR0_EL1),
1410 ID_SANITISED(ID_MMFR0_EL1),
1411 ID_SANITISED(ID_MMFR1_EL1),
1412 ID_SANITISED(ID_MMFR2_EL1),
1413 ID_SANITISED(ID_MMFR3_EL1),
1416 ID_SANITISED(ID_ISAR0_EL1),
1417 ID_SANITISED(ID_ISAR1_EL1),
1418 ID_SANITISED(ID_ISAR2_EL1),
1419 ID_SANITISED(ID_ISAR3_EL1),
1420 ID_SANITISED(ID_ISAR4_EL1),
1421 ID_SANITISED(ID_ISAR5_EL1),
1422 ID_SANITISED(ID_MMFR4_EL1),
1423 ID_UNALLOCATED(2,7),
1426 ID_SANITISED(MVFR0_EL1),
1427 ID_SANITISED(MVFR1_EL1),
1428 ID_SANITISED(MVFR2_EL1),
1429 ID_UNALLOCATED(3,3),
1430 ID_UNALLOCATED(3,4),
1431 ID_UNALLOCATED(3,5),
1432 ID_UNALLOCATED(3,6),
1433 ID_UNALLOCATED(3,7),
1435 /* AArch64 ID registers */
1437 ID_SANITISED(ID_AA64PFR0_EL1),
1438 ID_SANITISED(ID_AA64PFR1_EL1),
1439 ID_UNALLOCATED(4,2),
1440 ID_UNALLOCATED(4,3),
1441 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility },
1442 ID_UNALLOCATED(4,5),
1443 ID_UNALLOCATED(4,6),
1444 ID_UNALLOCATED(4,7),
1447 ID_SANITISED(ID_AA64DFR0_EL1),
1448 ID_SANITISED(ID_AA64DFR1_EL1),
1449 ID_UNALLOCATED(5,2),
1450 ID_UNALLOCATED(5,3),
1451 ID_HIDDEN(ID_AA64AFR0_EL1),
1452 ID_HIDDEN(ID_AA64AFR1_EL1),
1453 ID_UNALLOCATED(5,6),
1454 ID_UNALLOCATED(5,7),
1457 ID_SANITISED(ID_AA64ISAR0_EL1),
1458 ID_SANITISED(ID_AA64ISAR1_EL1),
1459 ID_UNALLOCATED(6,2),
1460 ID_UNALLOCATED(6,3),
1461 ID_UNALLOCATED(6,4),
1462 ID_UNALLOCATED(6,5),
1463 ID_UNALLOCATED(6,6),
1464 ID_UNALLOCATED(6,7),
1467 ID_SANITISED(ID_AA64MMFR0_EL1),
1468 ID_SANITISED(ID_AA64MMFR1_EL1),
1469 ID_SANITISED(ID_AA64MMFR2_EL1),
1470 ID_UNALLOCATED(7,3),
1471 ID_UNALLOCATED(7,4),
1472 ID_UNALLOCATED(7,5),
1473 ID_UNALLOCATED(7,6),
1474 ID_UNALLOCATED(7,7),
1476 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1477 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1478 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1479 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1480 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1481 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1489 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1490 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1491 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1493 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1494 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1495 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1496 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1497 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1498 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1499 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1500 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1502 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1503 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1505 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1506 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
1508 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1509 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1511 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1512 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1513 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1514 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1515 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1517 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1518 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1520 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1521 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1522 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1523 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1524 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1525 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1526 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1527 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1528 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1529 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1530 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1531 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1533 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1534 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1536 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1538 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1539 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1540 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1541 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1543 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
1544 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1545 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
1546 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
1547 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1548 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1549 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1550 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1551 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1552 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1553 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1555 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1556 * in 32bit mode. Here we choose to reset it as zero for consistency.
1558 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1559 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1561 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1562 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1564 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1565 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1566 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1569 PMU_PMEVCNTR_EL0(0),
1570 PMU_PMEVCNTR_EL0(1),
1571 PMU_PMEVCNTR_EL0(2),
1572 PMU_PMEVCNTR_EL0(3),
1573 PMU_PMEVCNTR_EL0(4),
1574 PMU_PMEVCNTR_EL0(5),
1575 PMU_PMEVCNTR_EL0(6),
1576 PMU_PMEVCNTR_EL0(7),
1577 PMU_PMEVCNTR_EL0(8),
1578 PMU_PMEVCNTR_EL0(9),
1579 PMU_PMEVCNTR_EL0(10),
1580 PMU_PMEVCNTR_EL0(11),
1581 PMU_PMEVCNTR_EL0(12),
1582 PMU_PMEVCNTR_EL0(13),
1583 PMU_PMEVCNTR_EL0(14),
1584 PMU_PMEVCNTR_EL0(15),
1585 PMU_PMEVCNTR_EL0(16),
1586 PMU_PMEVCNTR_EL0(17),
1587 PMU_PMEVCNTR_EL0(18),
1588 PMU_PMEVCNTR_EL0(19),
1589 PMU_PMEVCNTR_EL0(20),
1590 PMU_PMEVCNTR_EL0(21),
1591 PMU_PMEVCNTR_EL0(22),
1592 PMU_PMEVCNTR_EL0(23),
1593 PMU_PMEVCNTR_EL0(24),
1594 PMU_PMEVCNTR_EL0(25),
1595 PMU_PMEVCNTR_EL0(26),
1596 PMU_PMEVCNTR_EL0(27),
1597 PMU_PMEVCNTR_EL0(28),
1598 PMU_PMEVCNTR_EL0(29),
1599 PMU_PMEVCNTR_EL0(30),
1600 /* PMEVTYPERn_EL0 */
1601 PMU_PMEVTYPER_EL0(0),
1602 PMU_PMEVTYPER_EL0(1),
1603 PMU_PMEVTYPER_EL0(2),
1604 PMU_PMEVTYPER_EL0(3),
1605 PMU_PMEVTYPER_EL0(4),
1606 PMU_PMEVTYPER_EL0(5),
1607 PMU_PMEVTYPER_EL0(6),
1608 PMU_PMEVTYPER_EL0(7),
1609 PMU_PMEVTYPER_EL0(8),
1610 PMU_PMEVTYPER_EL0(9),
1611 PMU_PMEVTYPER_EL0(10),
1612 PMU_PMEVTYPER_EL0(11),
1613 PMU_PMEVTYPER_EL0(12),
1614 PMU_PMEVTYPER_EL0(13),
1615 PMU_PMEVTYPER_EL0(14),
1616 PMU_PMEVTYPER_EL0(15),
1617 PMU_PMEVTYPER_EL0(16),
1618 PMU_PMEVTYPER_EL0(17),
1619 PMU_PMEVTYPER_EL0(18),
1620 PMU_PMEVTYPER_EL0(19),
1621 PMU_PMEVTYPER_EL0(20),
1622 PMU_PMEVTYPER_EL0(21),
1623 PMU_PMEVTYPER_EL0(22),
1624 PMU_PMEVTYPER_EL0(23),
1625 PMU_PMEVTYPER_EL0(24),
1626 PMU_PMEVTYPER_EL0(25),
1627 PMU_PMEVTYPER_EL0(26),
1628 PMU_PMEVTYPER_EL0(27),
1629 PMU_PMEVTYPER_EL0(28),
1630 PMU_PMEVTYPER_EL0(29),
1631 PMU_PMEVTYPER_EL0(30),
1633 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1634 * in 32bit mode. Here we choose to reset it as zero for consistency.
1636 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1638 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1639 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1640 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1643 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1644 struct sys_reg_params *p,
1645 const struct sys_reg_desc *r)
1648 return ignore_write(vcpu, p);
1650 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1651 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1652 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1654 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1655 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1656 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1657 | (6 << 16) | (el3 << 14) | (el3 << 12));
1662 static bool trap_debug32(struct kvm_vcpu *vcpu,
1663 struct sys_reg_params *p,
1664 const struct sys_reg_desc *r)
1667 vcpu_cp14(vcpu, r->reg) = p->regval;
1668 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1670 p->regval = vcpu_cp14(vcpu, r->reg);
1676 /* AArch32 debug register mappings
1678 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1679 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1681 * All control registers and watchpoint value registers are mapped to
1682 * the lower 32 bits of their AArch64 equivalents. We share the trap
1683 * handlers with the above AArch64 code which checks what mode the
1687 static bool trap_xvr(struct kvm_vcpu *vcpu,
1688 struct sys_reg_params *p,
1689 const struct sys_reg_desc *rd)
1691 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1696 val &= 0xffffffffUL;
1697 val |= p->regval << 32;
1700 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1702 p->regval = *dbg_reg >> 32;
1705 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1710 #define DBG_BCR_BVR_WCR_WVR(n) \
1712 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1714 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1716 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1718 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1720 #define DBGBXVR(n) \
1721 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1724 * Trapped cp14 registers. We generally ignore most of the external
1725 * debug, on the principle that they don't really make sense to a
1726 * guest. Revisit this one day, would this principle change.
1728 static const struct sys_reg_desc cp14_regs[] = {
1730 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1732 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1734 DBG_BCR_BVR_WCR_WVR(0),
1736 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1737 DBG_BCR_BVR_WCR_WVR(1),
1739 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1741 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1742 DBG_BCR_BVR_WCR_WVR(2),
1743 /* DBGDTR[RT]Xint */
1744 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1745 /* DBGDTR[RT]Xext */
1746 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1747 DBG_BCR_BVR_WCR_WVR(3),
1748 DBG_BCR_BVR_WCR_WVR(4),
1749 DBG_BCR_BVR_WCR_WVR(5),
1751 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1753 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1754 DBG_BCR_BVR_WCR_WVR(6),
1756 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1757 DBG_BCR_BVR_WCR_WVR(7),
1758 DBG_BCR_BVR_WCR_WVR(8),
1759 DBG_BCR_BVR_WCR_WVR(9),
1760 DBG_BCR_BVR_WCR_WVR(10),
1761 DBG_BCR_BVR_WCR_WVR(11),
1762 DBG_BCR_BVR_WCR_WVR(12),
1763 DBG_BCR_BVR_WCR_WVR(13),
1764 DBG_BCR_BVR_WCR_WVR(14),
1765 DBG_BCR_BVR_WCR_WVR(15),
1767 /* DBGDRAR (32bit) */
1768 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1772 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1775 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1779 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1782 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1795 /* DBGDSAR (32bit) */
1796 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1799 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1801 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1803 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1805 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1807 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1809 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1812 /* Trapped cp14 64bit registers */
1813 static const struct sys_reg_desc cp14_64_regs[] = {
1814 /* DBGDRAR (64bit) */
1815 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1817 /* DBGDSAR (64bit) */
1818 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1821 /* Macro to expand the PMEVCNTRn register */
1822 #define PMU_PMEVCNTR(n) \
1824 { Op1(0), CRn(0b1110), \
1825 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1828 /* Macro to expand the PMEVTYPERn register */
1829 #define PMU_PMEVTYPER(n) \
1831 { Op1(0), CRn(0b1110), \
1832 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1833 access_pmu_evtyper }
1836 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1837 * depending on the way they are accessed (as a 32bit or a 64bit
1840 static const struct sys_reg_desc cp15_regs[] = {
1841 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1842 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1843 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1844 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1845 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1846 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1847 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1848 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1849 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1850 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1851 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1852 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1855 * DC{C,I,CI}SW operations:
1857 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1858 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1859 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1862 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1863 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1864 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1865 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1866 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1867 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1868 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1869 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1870 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1871 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1872 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1873 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1874 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1875 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1876 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1878 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1879 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1880 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1881 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1884 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1886 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1889 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
1890 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
1957 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1959 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
1960 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
1961 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
1964 static const struct sys_reg_desc cp15_64_regs[] = {
1965 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1966 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1967 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
1968 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1969 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
1970 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
1971 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
1974 /* Target specific emulation tables */
1975 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1977 void kvm_register_target_sys_reg_table(unsigned int target,
1978 struct kvm_sys_reg_target_table *table)
1980 target_tables[target] = table;
1983 /* Get specific register table for this target. */
1984 static const struct sys_reg_desc *get_target_table(unsigned target,
1988 struct kvm_sys_reg_target_table *table;
1990 table = target_tables[target];
1992 *num = table->table64.num;
1993 return table->table64.table;
1995 *num = table->table32.num;
1996 return table->table32.table;
2000 static int match_sys_reg(const void *key, const void *elt)
2002 const unsigned long pval = (unsigned long)key;
2003 const struct sys_reg_desc *r = elt;
2005 return pval - reg_to_encoding(r);
2008 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2009 const struct sys_reg_desc table[],
2012 unsigned long pval = reg_to_encoding(params);
2014 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
2017 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
2019 kvm_inject_undefined(vcpu);
2023 static void perform_access(struct kvm_vcpu *vcpu,
2024 struct sys_reg_params *params,
2025 const struct sys_reg_desc *r)
2027 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2029 /* Check for regs disabled by runtime config */
2030 if (sysreg_hidden_from_guest(vcpu, r)) {
2031 kvm_inject_undefined(vcpu);
2036 * Not having an accessor means that we have configured a trap
2037 * that we don't know how to handle. This certainly qualifies
2038 * as a gross bug that should be fixed right away.
2042 /* Skip instruction if instructed so */
2043 if (likely(r->access(vcpu, params, r)))
2044 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
2048 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2049 * call the corresponding trap handler.
2051 * @params: pointer to the descriptor of the access
2052 * @table: array of trap descriptors
2053 * @num: size of the trap descriptor array
2055 * Return 0 if the access has been handled, and -1 if not.
2057 static int emulate_cp(struct kvm_vcpu *vcpu,
2058 struct sys_reg_params *params,
2059 const struct sys_reg_desc *table,
2062 const struct sys_reg_desc *r;
2065 return -1; /* Not handled */
2067 r = find_reg(params, table, num);
2070 perform_access(vcpu, params, r);
2078 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2079 struct sys_reg_params *params)
2081 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
2085 case ESR_ELx_EC_CP15_32:
2086 case ESR_ELx_EC_CP15_64:
2089 case ESR_ELx_EC_CP14_MR:
2090 case ESR_ELx_EC_CP14_64:
2097 kvm_err("Unsupported guest CP%d access at: %08lx [%08lx]\n",
2098 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2099 print_sys_reg_instr(params);
2100 kvm_inject_undefined(vcpu);
2104 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2105 * @vcpu: The VCPU pointer
2106 * @run: The kvm_run struct
2108 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2109 const struct sys_reg_desc *global,
2111 const struct sys_reg_desc *target_specific,
2114 struct sys_reg_params params;
2115 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2116 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2117 int Rt2 = (hsr >> 10) & 0x1f;
2119 params.is_aarch32 = true;
2120 params.is_32bit = false;
2121 params.CRm = (hsr >> 1) & 0xf;
2122 params.is_write = ((hsr & 1) == 0);
2125 params.Op1 = (hsr >> 16) & 0xf;
2130 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2131 * backends between AArch32 and AArch64, we get away with it.
2133 if (params.is_write) {
2134 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2135 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2139 * Try to emulate the coprocessor access using the target
2140 * specific table first, and using the global table afterwards.
2141 * If either of the tables contains a handler, handle the
2142 * potential register operation in the case of a read and return
2145 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) ||
2146 !emulate_cp(vcpu, ¶ms, global, nr_global)) {
2147 /* Split up the value between registers for the read side */
2148 if (!params.is_write) {
2149 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2150 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2156 unhandled_cp_access(vcpu, ¶ms);
2161 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2162 * @vcpu: The VCPU pointer
2163 * @run: The kvm_run struct
2165 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2166 const struct sys_reg_desc *global,
2168 const struct sys_reg_desc *target_specific,
2171 struct sys_reg_params params;
2172 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2173 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2175 params.is_aarch32 = true;
2176 params.is_32bit = true;
2177 params.CRm = (hsr >> 1) & 0xf;
2178 params.regval = vcpu_get_reg(vcpu, Rt);
2179 params.is_write = ((hsr & 1) == 0);
2180 params.CRn = (hsr >> 10) & 0xf;
2182 params.Op1 = (hsr >> 14) & 0x7;
2183 params.Op2 = (hsr >> 17) & 0x7;
2185 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) ||
2186 !emulate_cp(vcpu, ¶ms, global, nr_global)) {
2187 if (!params.is_write)
2188 vcpu_set_reg(vcpu, Rt, params.regval);
2192 unhandled_cp_access(vcpu, ¶ms);
2196 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2198 const struct sys_reg_desc *target_specific;
2201 target_specific = get_target_table(vcpu->arch.target, false, &num);
2202 return kvm_handle_cp_64(vcpu,
2203 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
2204 target_specific, num);
2207 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2209 const struct sys_reg_desc *target_specific;
2212 target_specific = get_target_table(vcpu->arch.target, false, &num);
2213 return kvm_handle_cp_32(vcpu,
2214 cp15_regs, ARRAY_SIZE(cp15_regs),
2215 target_specific, num);
2218 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2220 return kvm_handle_cp_64(vcpu,
2221 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
2225 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2227 return kvm_handle_cp_32(vcpu,
2228 cp14_regs, ARRAY_SIZE(cp14_regs),
2232 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2233 struct sys_reg_params *params)
2236 const struct sys_reg_desc *table, *r;
2238 table = get_target_table(vcpu->arch.target, true, &num);
2240 /* Search target-specific then generic table. */
2241 r = find_reg(params, table, num);
2243 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2246 perform_access(vcpu, params, r);
2248 kvm_err("Unsupported guest sys_reg access at: %lx [%08lx]\n",
2249 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2250 print_sys_reg_instr(params);
2251 kvm_inject_undefined(vcpu);
2256 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
2257 const struct sys_reg_desc *table, size_t num,
2258 unsigned long *bmap)
2262 for (i = 0; i < num; i++)
2263 if (table[i].reset) {
2264 int reg = table[i].reg;
2266 table[i].reset(vcpu, &table[i]);
2267 if (reg > 0 && reg < NR_SYS_REGS)
2273 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2274 * @vcpu: The VCPU pointer
2275 * @run: The kvm_run struct
2277 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
2279 struct sys_reg_params params;
2280 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2281 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2284 trace_kvm_handle_sys_reg(esr);
2286 params.is_aarch32 = false;
2287 params.is_32bit = false;
2288 params.Op0 = (esr >> 20) & 3;
2289 params.Op1 = (esr >> 14) & 0x7;
2290 params.CRn = (esr >> 10) & 0xf;
2291 params.CRm = (esr >> 1) & 0xf;
2292 params.Op2 = (esr >> 17) & 0x7;
2293 params.regval = vcpu_get_reg(vcpu, Rt);
2294 params.is_write = !(esr & 1);
2296 ret = emulate_sys_reg(vcpu, ¶ms);
2298 if (!params.is_write)
2299 vcpu_set_reg(vcpu, Rt, params.regval);
2303 /******************************************************************************
2305 *****************************************************************************/
2307 static bool index_to_params(u64 id, struct sys_reg_params *params)
2309 switch (id & KVM_REG_SIZE_MASK) {
2310 case KVM_REG_SIZE_U64:
2311 /* Any unused index bits means it's not valid. */
2312 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2313 | KVM_REG_ARM_COPROC_MASK
2314 | KVM_REG_ARM64_SYSREG_OP0_MASK
2315 | KVM_REG_ARM64_SYSREG_OP1_MASK
2316 | KVM_REG_ARM64_SYSREG_CRN_MASK
2317 | KVM_REG_ARM64_SYSREG_CRM_MASK
2318 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2320 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2321 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2322 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2323 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2324 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2325 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2326 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2327 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2328 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2329 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2336 const struct sys_reg_desc *find_reg_by_id(u64 id,
2337 struct sys_reg_params *params,
2338 const struct sys_reg_desc table[],
2341 if (!index_to_params(id, params))
2344 return find_reg(params, table, num);
2347 /* Decode an index value, and find the sys_reg_desc entry. */
2348 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2352 const struct sys_reg_desc *table, *r;
2353 struct sys_reg_params params;
2355 /* We only do sys_reg for now. */
2356 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2359 table = get_target_table(vcpu->arch.target, true, &num);
2360 r = find_reg_by_id(id, ¶ms, table, num);
2362 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2364 /* Not saved in the sys_reg array and not otherwise accessible? */
2365 if (r && !(r->reg || r->get_user))
2372 * These are the invariant sys_reg registers: we let the guest see the
2373 * host versions of these, so they're part of the guest state.
2375 * A future CPU may provide a mechanism to present different values to
2376 * the guest, or a future kvm may trap them.
2379 #define FUNCTION_INVARIANT(reg) \
2380 static void get_##reg(struct kvm_vcpu *v, \
2381 const struct sys_reg_desc *r) \
2383 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2386 FUNCTION_INVARIANT(midr_el1)
2387 FUNCTION_INVARIANT(revidr_el1)
2388 FUNCTION_INVARIANT(clidr_el1)
2389 FUNCTION_INVARIANT(aidr_el1)
2391 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2393 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2396 /* ->val is filled in by kvm_sys_reg_table_init() */
2397 static struct sys_reg_desc invariant_sys_regs[] = {
2398 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2399 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2400 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2401 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2402 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2405 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2407 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2412 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2414 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2419 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2421 struct sys_reg_params params;
2422 const struct sys_reg_desc *r;
2424 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2425 ARRAY_SIZE(invariant_sys_regs));
2429 return reg_to_user(uaddr, &r->val, id);
2432 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2434 struct sys_reg_params params;
2435 const struct sys_reg_desc *r;
2437 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2439 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2440 ARRAY_SIZE(invariant_sys_regs));
2444 err = reg_from_user(&val, uaddr, id);
2448 /* This is what we mean by invariant: you can't change it. */
2455 static bool is_valid_cache(u32 val)
2459 if (val >= CSSELR_MAX)
2462 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2464 ctype = (cache_levels >> (level * 3)) & 7;
2467 case 0: /* No cache */
2469 case 1: /* Instruction cache only */
2471 case 2: /* Data cache only */
2472 case 4: /* Unified cache */
2474 case 3: /* Separate instruction and data caches */
2476 default: /* Reserved: we can't know instruction or data. */
2481 static int demux_c15_get(u64 id, void __user *uaddr)
2484 u32 __user *uval = uaddr;
2486 /* Fail if we have unknown bits set. */
2487 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2488 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2491 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2492 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2493 if (KVM_REG_SIZE(id) != 4)
2495 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2496 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2497 if (!is_valid_cache(val))
2500 return put_user(get_ccsidr(val), uval);
2506 static int demux_c15_set(u64 id, void __user *uaddr)
2509 u32 __user *uval = uaddr;
2511 /* Fail if we have unknown bits set. */
2512 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2513 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2516 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2517 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2518 if (KVM_REG_SIZE(id) != 4)
2520 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2521 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2522 if (!is_valid_cache(val))
2525 if (get_user(newval, uval))
2528 /* This is also invariant: you can't change it. */
2529 if (newval != get_ccsidr(val))
2537 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2539 const struct sys_reg_desc *r;
2540 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2542 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2543 return demux_c15_get(reg->id, uaddr);
2545 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2548 r = index_to_sys_reg_desc(vcpu, reg->id);
2550 return get_invariant_sys_reg(reg->id, uaddr);
2552 /* Check for regs disabled by runtime config */
2553 if (sysreg_hidden_from_user(vcpu, r))
2557 return (r->get_user)(vcpu, r, reg, uaddr);
2559 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2562 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2564 const struct sys_reg_desc *r;
2565 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2567 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2568 return demux_c15_set(reg->id, uaddr);
2570 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2573 r = index_to_sys_reg_desc(vcpu, reg->id);
2575 return set_invariant_sys_reg(reg->id, uaddr);
2577 /* Check for regs disabled by runtime config */
2578 if (sysreg_hidden_from_user(vcpu, r))
2582 return (r->set_user)(vcpu, r, reg, uaddr);
2584 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2587 static unsigned int num_demux_regs(void)
2589 unsigned int i, count = 0;
2591 for (i = 0; i < CSSELR_MAX; i++)
2592 if (is_valid_cache(i))
2598 static int write_demux_regids(u64 __user *uindices)
2600 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2603 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2604 for (i = 0; i < CSSELR_MAX; i++) {
2605 if (!is_valid_cache(i))
2607 if (put_user(val | i, uindices))
2614 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2616 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2617 KVM_REG_ARM64_SYSREG |
2618 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2619 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2620 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2621 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2622 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2625 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2630 if (put_user(sys_reg_to_index(reg), *uind))
2637 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2638 const struct sys_reg_desc *rd,
2640 unsigned int *total)
2643 * Ignore registers we trap but don't save,
2644 * and for which no custom user accessor is provided.
2646 if (!(rd->reg || rd->get_user))
2649 if (sysreg_hidden_from_user(vcpu, rd))
2652 if (!copy_reg_to_user(rd, uind))
2659 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2660 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2662 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2663 unsigned int total = 0;
2667 /* We check for duplicates here, to allow arch-specific overrides. */
2668 i1 = get_target_table(vcpu->arch.target, true, &num);
2671 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2673 BUG_ON(i1 == end1 || i2 == end2);
2675 /* Walk carefully, as both tables may refer to the same register. */
2677 int cmp = cmp_sys_reg(i1, i2);
2678 /* target-specific overrides generic entry. */
2680 err = walk_one_sys_reg(vcpu, i1, &uind, &total);
2682 err = walk_one_sys_reg(vcpu, i2, &uind, &total);
2687 if (cmp <= 0 && ++i1 == end1)
2689 if (cmp >= 0 && ++i2 == end2)
2695 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2697 return ARRAY_SIZE(invariant_sys_regs)
2699 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2702 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2707 /* Then give them all the invariant registers' indices. */
2708 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2709 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2714 err = walk_sys_regs(vcpu, uindices);
2719 return write_demux_regids(uindices);
2722 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2726 for (i = 1; i < n; i++) {
2727 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2728 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2736 void kvm_sys_reg_table_init(void)
2739 struct sys_reg_desc clidr;
2741 /* Make sure tables are unique and in order. */
2742 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2743 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2744 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2745 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2746 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2747 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2749 /* We abuse the reset function to overwrite the table itself. */
2750 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2751 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2754 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2756 * If software reads the Cache Type fields from Ctype1
2757 * upwards, once it has seen a value of 0b000, no caches
2758 * exist at further-out levels of the hierarchy. So, for
2759 * example, if Ctype3 is the first Cache Type field with a
2760 * value of 0b000, the values of Ctype4 to Ctype7 must be
2763 get_clidr_el1(NULL, &clidr); /* Ugly... */
2764 cache_levels = clidr.val;
2765 for (i = 0; i < 7; i++)
2766 if (((cache_levels >> (i*3)) & 7) == 0)
2768 /* Clear all higher bits. */
2769 cache_levels &= (1 << (i*3))-1;
2773 * kvm_reset_sys_regs - sets system registers to reset value
2774 * @vcpu: The VCPU pointer
2776 * This function finds the right table above and sets the registers on the
2777 * virtual CPU struct to their architecturally defined reset values.
2779 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2782 const struct sys_reg_desc *table;
2783 DECLARE_BITMAP(bmap, NR_SYS_REGS) = { 0, };
2785 /* Generic chip reset first (so target could override). */
2786 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs), bmap);
2788 table = get_target_table(vcpu->arch.target, true, &num);
2789 reset_sys_reg_descs(vcpu, table, num, bmap);
2791 for (num = 1; num < NR_SYS_REGS; num++) {
2792 if (WARN(!test_bit(num, bmap),
2793 "Didn't reset __vcpu_sys_reg(%zi)\n", num))