1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
12 #include <linux/bsearch.h>
13 #include <linux/kvm_host.h>
15 #include <linux/printk.h>
16 #include <linux/uaccess.h>
18 #include <asm/cacheflush.h>
19 #include <asm/cputype.h>
20 #include <asm/debug-monitors.h>
22 #include <asm/kvm_arm.h>
23 #include <asm/kvm_coproc.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_hyp.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/perf_event.h>
28 #include <asm/sysreg.h>
30 #include <trace/events/kvm.h>
37 * All of this file is extremely similar to the ARM coproc.c, but the
38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
47 static bool read_from_write_only(struct kvm_vcpu *vcpu,
48 struct sys_reg_params *params,
49 const struct sys_reg_desc *r)
51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
52 print_sys_reg_instr(params);
53 kvm_inject_undefined(vcpu);
57 static bool write_to_read_only(struct kvm_vcpu *vcpu,
58 struct sys_reg_params *params,
59 const struct sys_reg_desc *r)
61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
62 print_sys_reg_instr(params);
63 kvm_inject_undefined(vcpu);
67 static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
70 * System registers listed in the switch are not saved on every
71 * exit from the guest but are only saved on vcpu_put.
73 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
74 * should never be listed below, because the guest cannot modify its
75 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
76 * thread when emulating cross-VCPU communication.
79 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break;
80 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
81 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
82 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
83 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
84 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
85 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
86 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
87 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
88 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
89 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
90 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
91 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
92 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
93 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
94 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
95 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
96 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
97 case PAR_EL1: *val = read_sysreg_s(SYS_PAR_EL1); break;
98 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
99 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
100 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
101 default: return false;
107 static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
110 * System registers listed in the switch are not restored on every
111 * entry to the guest but are only restored on vcpu_load.
113 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
114 * should never be listed below, because the MPIDR should only be set
115 * once, before running the VCPU, and never changed later.
118 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break;
119 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
120 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
121 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
122 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
123 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
124 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
125 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
126 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
127 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
128 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
129 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
130 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
131 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
132 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
133 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
134 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
135 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
136 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
137 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
138 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
139 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
140 default: return false;
146 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
148 u64 val = 0x8badf00d8badf00d;
150 if (vcpu->arch.sysregs_loaded_on_cpu &&
151 __vcpu_read_sys_reg_from_cpu(reg, &val))
154 return __vcpu_sys_reg(vcpu, reg);
157 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
159 if (vcpu->arch.sysregs_loaded_on_cpu &&
160 __vcpu_write_sys_reg_to_cpu(val, reg))
163 __vcpu_sys_reg(vcpu, reg) = val;
166 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
167 static u32 cache_levels;
169 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
170 #define CSSELR_MAX 12
172 /* Which cache CCSIDR represents depends on CSSELR value. */
173 static u32 get_ccsidr(u32 csselr)
177 /* Make sure noone else changes CSSELR during this! */
179 write_sysreg(csselr, csselr_el1);
181 ccsidr = read_sysreg(ccsidr_el1);
188 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
190 static bool access_dcsw(struct kvm_vcpu *vcpu,
191 struct sys_reg_params *p,
192 const struct sys_reg_desc *r)
195 return read_from_write_only(vcpu, p, r);
198 * Only track S/W ops if we don't have FWB. It still indicates
199 * that the guest is a bit broken (S/W operations should only
200 * be done by firmware, knowing that there is only a single
201 * CPU left in the system, and certainly not from non-secure
204 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
205 kvm_set_way_flush(vcpu);
211 * Generic accessor for VM registers. Only called as long as HCR_TVM
212 * is set. If the guest enables the MMU, we stop trapping the VM
213 * sys_regs and leave it in complete control of the caches.
215 static bool access_vm_reg(struct kvm_vcpu *vcpu,
216 struct sys_reg_params *p,
217 const struct sys_reg_desc *r)
219 bool was_enabled = vcpu_has_cache_enabled(vcpu);
223 BUG_ON(!p->is_write);
225 /* See the 32bit mapping in kvm_host.h */
229 if (!p->is_aarch32 || !p->is_32bit) {
232 val = vcpu_read_sys_reg(vcpu, reg);
234 val = (p->regval << 32) | (u64)lower_32_bits(val);
236 val = ((u64)upper_32_bits(val) << 32) |
237 lower_32_bits(p->regval);
239 vcpu_write_sys_reg(vcpu, val, reg);
241 kvm_toggle_cache(vcpu, was_enabled);
246 * Trap handler for the GICv3 SGI generation system register.
247 * Forward the request to the VGIC emulation.
248 * The cp15_64 code makes sure this automatically works
249 * for both AArch64 and AArch32 accesses.
251 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
252 struct sys_reg_params *p,
253 const struct sys_reg_desc *r)
258 return read_from_write_only(vcpu, p, r);
261 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
262 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
263 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
264 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
269 default: /* Keep GCC quiet */
270 case 0: /* ICC_SGI1R */
273 case 1: /* ICC_ASGI1R */
274 case 2: /* ICC_SGI0R */
280 default: /* Keep GCC quiet */
281 case 5: /* ICC_SGI1R_EL1 */
284 case 6: /* ICC_ASGI1R_EL1 */
285 case 7: /* ICC_SGI0R_EL1 */
291 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
296 static bool access_gic_sre(struct kvm_vcpu *vcpu,
297 struct sys_reg_params *p,
298 const struct sys_reg_desc *r)
301 return ignore_write(vcpu, p);
303 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
307 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
308 struct sys_reg_params *p,
309 const struct sys_reg_desc *r)
312 return ignore_write(vcpu, p);
314 return read_zero(vcpu, p);
318 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
319 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
320 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
321 * treat it separately.
323 static bool trap_loregion(struct kvm_vcpu *vcpu,
324 struct sys_reg_params *p,
325 const struct sys_reg_desc *r)
327 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
328 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
329 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
331 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
332 kvm_inject_undefined(vcpu);
336 if (p->is_write && sr == SYS_LORID_EL1)
337 return write_to_read_only(vcpu, p, r);
339 return trap_raz_wi(vcpu, p, r);
342 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
343 struct sys_reg_params *p,
344 const struct sys_reg_desc *r)
347 return ignore_write(vcpu, p);
349 p->regval = (1 << 3);
354 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
355 struct sys_reg_params *p,
356 const struct sys_reg_desc *r)
359 return ignore_write(vcpu, p);
361 p->regval = read_sysreg(dbgauthstatus_el1);
367 * We want to avoid world-switching all the DBG registers all the
370 * - If we've touched any debug register, it is likely that we're
371 * going to touch more of them. It then makes sense to disable the
372 * traps and start doing the save/restore dance
373 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
374 * then mandatory to save/restore the registers, as the guest
377 * For this, we use a DIRTY bit, indicating the guest has modified the
378 * debug registers, used as follow:
381 * - If the dirty bit is set (because we're coming back from trapping),
382 * disable the traps, save host registers, restore guest registers.
383 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
384 * set the dirty bit, disable the traps, save host registers,
385 * restore guest registers.
386 * - Otherwise, enable the traps
389 * - If the dirty bit is set, save guest registers, restore host
390 * registers and clear the dirty bit. This ensure that the host can
391 * now use the debug registers.
393 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
394 struct sys_reg_params *p,
395 const struct sys_reg_desc *r)
398 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
399 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
401 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
404 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
410 * reg_to_dbg/dbg_to_reg
412 * A 32 bit write to a debug register leave top bits alone
413 * A 32 bit read from a debug register only returns the bottom bits
415 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
416 * hyp.S code switches between host and guest values in future.
418 static void reg_to_dbg(struct kvm_vcpu *vcpu,
419 struct sys_reg_params *p,
426 val |= ((*dbg_reg >> 32) << 32);
430 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
433 static void dbg_to_reg(struct kvm_vcpu *vcpu,
434 struct sys_reg_params *p,
437 p->regval = *dbg_reg;
439 p->regval &= 0xffffffffUL;
442 static bool trap_bvr(struct kvm_vcpu *vcpu,
443 struct sys_reg_params *p,
444 const struct sys_reg_desc *rd)
446 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
449 reg_to_dbg(vcpu, p, dbg_reg);
451 dbg_to_reg(vcpu, p, dbg_reg);
453 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
458 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
459 const struct kvm_one_reg *reg, void __user *uaddr)
461 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
463 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
468 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
469 const struct kvm_one_reg *reg, void __user *uaddr)
471 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
473 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
478 static void reset_bvr(struct kvm_vcpu *vcpu,
479 const struct sys_reg_desc *rd)
481 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
484 static bool trap_bcr(struct kvm_vcpu *vcpu,
485 struct sys_reg_params *p,
486 const struct sys_reg_desc *rd)
488 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
491 reg_to_dbg(vcpu, p, dbg_reg);
493 dbg_to_reg(vcpu, p, dbg_reg);
495 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
500 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
501 const struct kvm_one_reg *reg, void __user *uaddr)
503 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
505 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
511 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
512 const struct kvm_one_reg *reg, void __user *uaddr)
514 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
516 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
521 static void reset_bcr(struct kvm_vcpu *vcpu,
522 const struct sys_reg_desc *rd)
524 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
527 static bool trap_wvr(struct kvm_vcpu *vcpu,
528 struct sys_reg_params *p,
529 const struct sys_reg_desc *rd)
531 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
534 reg_to_dbg(vcpu, p, dbg_reg);
536 dbg_to_reg(vcpu, p, dbg_reg);
538 trace_trap_reg(__func__, rd->reg, p->is_write,
539 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
544 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
545 const struct kvm_one_reg *reg, void __user *uaddr)
547 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
549 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
554 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
555 const struct kvm_one_reg *reg, void __user *uaddr)
557 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
559 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
564 static void reset_wvr(struct kvm_vcpu *vcpu,
565 const struct sys_reg_desc *rd)
567 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
570 static bool trap_wcr(struct kvm_vcpu *vcpu,
571 struct sys_reg_params *p,
572 const struct sys_reg_desc *rd)
574 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
577 reg_to_dbg(vcpu, p, dbg_reg);
579 dbg_to_reg(vcpu, p, dbg_reg);
581 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
586 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
587 const struct kvm_one_reg *reg, void __user *uaddr)
589 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
591 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
596 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
597 const struct kvm_one_reg *reg, void __user *uaddr)
599 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
601 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
606 static void reset_wcr(struct kvm_vcpu *vcpu,
607 const struct sys_reg_desc *rd)
609 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
612 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
614 u64 amair = read_sysreg(amair_el1);
615 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
618 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
623 * Map the vcpu_id into the first three affinity level fields of
624 * the MPIDR. We limit the number of VCPUs in level 0 due to a
625 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
626 * of the GICv3 to be able to address each CPU directly when
629 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
630 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
631 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
632 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
635 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
639 pmcr = read_sysreg(pmcr_el0);
641 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
642 * except PMCR.E resetting to zero.
644 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
645 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
646 if (!system_supports_32bit_el0())
647 val |= ARMV8_PMU_PMCR_LC;
648 __vcpu_sys_reg(vcpu, r->reg) = val;
651 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
653 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
654 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
657 kvm_inject_undefined(vcpu);
662 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
664 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
667 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
669 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
672 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
674 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
677 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
679 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
682 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
683 const struct sys_reg_desc *r)
687 if (!kvm_arm_pmu_v3_ready(vcpu))
688 return trap_raz_wi(vcpu, p, r);
690 if (pmu_access_el0_disabled(vcpu))
694 /* Only update writeable bits of PMCR */
695 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
696 val &= ~ARMV8_PMU_PMCR_MASK;
697 val |= p->regval & ARMV8_PMU_PMCR_MASK;
698 if (!system_supports_32bit_el0())
699 val |= ARMV8_PMU_PMCR_LC;
700 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
701 kvm_pmu_handle_pmcr(vcpu, val);
702 kvm_vcpu_pmu_restore_guest(vcpu);
704 /* PMCR.P & PMCR.C are RAZ */
705 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
706 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
713 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
714 const struct sys_reg_desc *r)
716 if (!kvm_arm_pmu_v3_ready(vcpu))
717 return trap_raz_wi(vcpu, p, r);
719 if (pmu_access_event_counter_el0_disabled(vcpu))
723 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
725 /* return PMSELR.SEL field */
726 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
727 & ARMV8_PMU_COUNTER_MASK;
732 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
733 const struct sys_reg_desc *r)
737 if (!kvm_arm_pmu_v3_ready(vcpu))
738 return trap_raz_wi(vcpu, p, r);
742 if (pmu_access_el0_disabled(vcpu))
746 pmceid = read_sysreg(pmceid0_el0);
748 pmceid = read_sysreg(pmceid1_el0);
755 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
759 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
760 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
761 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
762 kvm_inject_undefined(vcpu);
769 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
770 struct sys_reg_params *p,
771 const struct sys_reg_desc *r)
775 if (!kvm_arm_pmu_v3_ready(vcpu))
776 return trap_raz_wi(vcpu, p, r);
778 if (r->CRn == 9 && r->CRm == 13) {
781 if (pmu_access_event_counter_el0_disabled(vcpu))
784 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
785 & ARMV8_PMU_COUNTER_MASK;
786 } else if (r->Op2 == 0) {
788 if (pmu_access_cycle_counter_el0_disabled(vcpu))
791 idx = ARMV8_PMU_CYCLE_IDX;
795 } else if (r->CRn == 0 && r->CRm == 9) {
797 if (pmu_access_event_counter_el0_disabled(vcpu))
800 idx = ARMV8_PMU_CYCLE_IDX;
801 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
803 if (pmu_access_event_counter_el0_disabled(vcpu))
806 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
811 if (!pmu_counter_idx_valid(vcpu, idx))
815 if (pmu_access_el0_disabled(vcpu))
818 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
820 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
826 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
827 const struct sys_reg_desc *r)
831 if (!kvm_arm_pmu_v3_ready(vcpu))
832 return trap_raz_wi(vcpu, p, r);
834 if (pmu_access_el0_disabled(vcpu))
837 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
839 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
840 reg = PMEVTYPER0_EL0 + idx;
841 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
842 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
843 if (idx == ARMV8_PMU_CYCLE_IDX)
847 reg = PMEVTYPER0_EL0 + idx;
852 if (!pmu_counter_idx_valid(vcpu, idx))
856 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
857 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
858 kvm_vcpu_pmu_restore_guest(vcpu);
860 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
866 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
867 const struct sys_reg_desc *r)
871 if (!kvm_arm_pmu_v3_ready(vcpu))
872 return trap_raz_wi(vcpu, p, r);
874 if (pmu_access_el0_disabled(vcpu))
877 mask = kvm_pmu_valid_counter_mask(vcpu);
879 val = p->regval & mask;
881 /* accessing PMCNTENSET_EL0 */
882 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
883 kvm_pmu_enable_counter_mask(vcpu, val);
884 kvm_vcpu_pmu_restore_guest(vcpu);
886 /* accessing PMCNTENCLR_EL0 */
887 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
888 kvm_pmu_disable_counter_mask(vcpu, val);
891 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
897 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
898 const struct sys_reg_desc *r)
900 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
902 if (!kvm_arm_pmu_v3_ready(vcpu))
903 return trap_raz_wi(vcpu, p, r);
905 if (!vcpu_mode_priv(vcpu)) {
906 kvm_inject_undefined(vcpu);
911 u64 val = p->regval & mask;
914 /* accessing PMINTENSET_EL1 */
915 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
917 /* accessing PMINTENCLR_EL1 */
918 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
920 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
926 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
927 const struct sys_reg_desc *r)
929 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
931 if (!kvm_arm_pmu_v3_ready(vcpu))
932 return trap_raz_wi(vcpu, p, r);
934 if (pmu_access_el0_disabled(vcpu))
939 /* accessing PMOVSSET_EL0 */
940 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
942 /* accessing PMOVSCLR_EL0 */
943 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
945 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
951 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
952 const struct sys_reg_desc *r)
956 if (!kvm_arm_pmu_v3_ready(vcpu))
957 return trap_raz_wi(vcpu, p, r);
960 return read_from_write_only(vcpu, p, r);
962 if (pmu_write_swinc_el0_disabled(vcpu))
965 mask = kvm_pmu_valid_counter_mask(vcpu);
966 kvm_pmu_software_increment(vcpu, p->regval & mask);
970 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
971 const struct sys_reg_desc *r)
973 if (!kvm_arm_pmu_v3_ready(vcpu))
974 return trap_raz_wi(vcpu, p, r);
977 if (!vcpu_mode_priv(vcpu)) {
978 kvm_inject_undefined(vcpu);
982 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
983 p->regval & ARMV8_PMU_USERENR_MASK;
985 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
986 & ARMV8_PMU_USERENR_MASK;
992 #define reg_to_encoding(x) \
993 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
994 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
996 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
997 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
998 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
999 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
1000 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
1001 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
1002 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
1003 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
1004 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
1005 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
1007 /* Macro to expand the PMEVCNTRn_EL0 register */
1008 #define PMU_PMEVCNTR_EL0(n) \
1009 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
1010 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
1012 /* Macro to expand the PMEVTYPERn_EL0 register */
1013 #define PMU_PMEVTYPER_EL0(n) \
1014 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
1015 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
1017 static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1018 const struct sys_reg_desc *r)
1020 kvm_inject_undefined(vcpu);
1025 /* Macro to expand the AMU counter and type registers*/
1026 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu }
1027 #define AMU_AMEVTYPE0_EL0(n) { SYS_DESC(SYS_AMEVTYPE0_EL0(n)), access_amu }
1028 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu }
1029 #define AMU_AMEVTYPE1_EL0(n) { SYS_DESC(SYS_AMEVTYPE1_EL0(n)), access_amu }
1031 static bool trap_ptrauth(struct kvm_vcpu *vcpu,
1032 struct sys_reg_params *p,
1033 const struct sys_reg_desc *rd)
1036 * If we land here, that is because we didn't fixup the access on exit
1037 * by allowing the PtrAuth sysregs. The only way this happens is when
1038 * the guest does not have PtrAuth support enabled.
1040 kvm_inject_undefined(vcpu);
1045 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1046 const struct sys_reg_desc *rd)
1048 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1051 #define __PTRAUTH_KEY(k) \
1052 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \
1053 .visibility = ptrauth_visibility}
1055 #define PTRAUTH_KEY(k) \
1056 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1057 __PTRAUTH_KEY(k ## KEYHI_EL1)
1059 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1060 struct sys_reg_params *p,
1061 const struct sys_reg_desc *r)
1063 enum kvm_arch_timers tmr;
1064 enum kvm_arch_timer_regs treg;
1065 u64 reg = reg_to_encoding(r);
1068 case SYS_CNTP_TVAL_EL0:
1069 case SYS_AARCH32_CNTP_TVAL:
1071 treg = TIMER_REG_TVAL;
1073 case SYS_CNTP_CTL_EL0:
1074 case SYS_AARCH32_CNTP_CTL:
1076 treg = TIMER_REG_CTL;
1078 case SYS_CNTP_CVAL_EL0:
1079 case SYS_AARCH32_CNTP_CVAL:
1081 treg = TIMER_REG_CVAL;
1088 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1090 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1095 /* Read a sanitised cpufeature ID register by sys_reg_desc */
1096 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1097 struct sys_reg_desc const *r, bool raz)
1099 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1100 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1101 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1103 if (id == SYS_ID_AA64PFR0_EL1) {
1104 if (!vcpu_has_sve(vcpu))
1105 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1106 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
1107 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
1108 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1109 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1110 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1111 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
1112 } else if (id == SYS_ID_AA64DFR0_EL1) {
1113 /* Limit guests to PMUv3 for ARMv8.1 */
1114 val = cpuid_feature_cap_perfmon_field(val,
1115 ID_AA64DFR0_PMUVER_SHIFT,
1116 ID_AA64DFR0_PMUVER_8_1);
1117 } else if (id == SYS_ID_DFR0_EL1) {
1118 /* Limit guests to PMUv3 for ARMv8.1 */
1119 val = cpuid_feature_cap_perfmon_field(val,
1120 ID_DFR0_PERFMON_SHIFT,
1121 ID_DFR0_PERFMON_8_1);
1127 /* cpufeature ID register access trap handlers */
1129 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1130 struct sys_reg_params *p,
1131 const struct sys_reg_desc *r,
1135 return write_to_read_only(vcpu, p, r);
1137 p->regval = read_id_reg(vcpu, r, raz);
1141 static bool access_id_reg(struct kvm_vcpu *vcpu,
1142 struct sys_reg_params *p,
1143 const struct sys_reg_desc *r)
1145 return __access_id_reg(vcpu, p, r, false);
1148 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1149 struct sys_reg_params *p,
1150 const struct sys_reg_desc *r)
1152 return __access_id_reg(vcpu, p, r, true);
1155 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1156 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1157 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1159 /* Visibility overrides for SVE-specific control registers */
1160 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1161 const struct sys_reg_desc *rd)
1163 if (vcpu_has_sve(vcpu))
1166 return REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1169 /* Visibility overrides for SVE-specific ID registers */
1170 static unsigned int sve_id_visibility(const struct kvm_vcpu *vcpu,
1171 const struct sys_reg_desc *rd)
1173 if (vcpu_has_sve(vcpu))
1176 return REG_HIDDEN_USER;
1179 /* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */
1180 static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu)
1182 if (!vcpu_has_sve(vcpu))
1185 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1);
1188 static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1189 struct sys_reg_params *p,
1190 const struct sys_reg_desc *rd)
1193 return write_to_read_only(vcpu, p, rd);
1195 p->regval = guest_id_aa64zfr0_el1(vcpu);
1199 static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1200 const struct sys_reg_desc *rd,
1201 const struct kvm_one_reg *reg, void __user *uaddr)
1205 if (WARN_ON(!vcpu_has_sve(vcpu)))
1208 val = guest_id_aa64zfr0_el1(vcpu);
1209 return reg_to_user(uaddr, &val, reg->id);
1212 static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1213 const struct sys_reg_desc *rd,
1214 const struct kvm_one_reg *reg, void __user *uaddr)
1216 const u64 id = sys_reg_to_index(rd);
1220 if (WARN_ON(!vcpu_has_sve(vcpu)))
1223 err = reg_from_user(&val, uaddr, id);
1227 /* This is what we mean by invariant: you can't change it. */
1228 if (val != guest_id_aa64zfr0_el1(vcpu))
1235 * cpufeature ID register user accessors
1237 * For now, these registers are immutable for userspace, so no values
1238 * are stored, and for set_id_reg() we don't allow the effective value
1241 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1242 const struct sys_reg_desc *rd, void __user *uaddr,
1245 const u64 id = sys_reg_to_index(rd);
1246 const u64 val = read_id_reg(vcpu, rd, raz);
1248 return reg_to_user(uaddr, &val, id);
1251 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1252 const struct sys_reg_desc *rd, void __user *uaddr,
1255 const u64 id = sys_reg_to_index(rd);
1259 err = reg_from_user(&val, uaddr, id);
1263 /* This is what we mean by invariant: you can't change it. */
1264 if (val != read_id_reg(vcpu, rd, raz))
1270 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1271 const struct kvm_one_reg *reg, void __user *uaddr)
1273 return __get_id_reg(vcpu, rd, uaddr, false);
1276 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1277 const struct kvm_one_reg *reg, void __user *uaddr)
1279 return __set_id_reg(vcpu, rd, uaddr, false);
1282 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1283 const struct kvm_one_reg *reg, void __user *uaddr)
1285 return __get_id_reg(vcpu, rd, uaddr, true);
1288 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1289 const struct kvm_one_reg *reg, void __user *uaddr)
1291 return __set_id_reg(vcpu, rd, uaddr, true);
1294 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1295 const struct sys_reg_desc *r)
1298 return write_to_read_only(vcpu, p, r);
1300 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1304 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1305 const struct sys_reg_desc *r)
1308 return write_to_read_only(vcpu, p, r);
1310 p->regval = read_sysreg(clidr_el1);
1314 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1315 const struct sys_reg_desc *r)
1319 /* See the 32bit mapping in kvm_host.h */
1324 vcpu_write_sys_reg(vcpu, p->regval, reg);
1326 p->regval = vcpu_read_sys_reg(vcpu, reg);
1330 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1331 const struct sys_reg_desc *r)
1336 return write_to_read_only(vcpu, p, r);
1338 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1339 p->regval = get_ccsidr(csselr);
1342 * Guests should not be doing cache operations by set/way at all, and
1343 * for this reason, we trap them and attempt to infer the intent, so
1344 * that we can flush the entire guest's address space at the appropriate
1346 * To prevent this trapping from causing performance problems, let's
1347 * expose the geometry of all data and unified caches (which are
1348 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1349 * [If guests should attempt to infer aliasing properties from the
1350 * geometry (which is not permitted by the architecture), they would
1351 * only do so for virtually indexed caches.]
1353 if (!(csselr & 1)) // data or unified cache
1354 p->regval &= ~GENMASK(27, 3);
1358 /* sys_reg_desc initialiser for known cpufeature ID registers */
1359 #define ID_SANITISED(name) { \
1360 SYS_DESC(SYS_##name), \
1361 .access = access_id_reg, \
1362 .get_user = get_id_reg, \
1363 .set_user = set_id_reg, \
1367 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1368 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1369 * (1 <= crm < 8, 0 <= Op2 < 8).
1371 #define ID_UNALLOCATED(crm, op2) { \
1372 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1373 .access = access_raz_id_reg, \
1374 .get_user = get_raz_id_reg, \
1375 .set_user = set_raz_id_reg, \
1379 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1380 * For now, these are exposed just like unallocated ID regs: they appear
1381 * RAZ for the guest.
1383 #define ID_HIDDEN(name) { \
1384 SYS_DESC(SYS_##name), \
1385 .access = access_raz_id_reg, \
1386 .get_user = get_raz_id_reg, \
1387 .set_user = set_raz_id_reg, \
1391 * Architected system registers.
1392 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1394 * Debug handling: We do trap most, if not all debug related system
1395 * registers. The implementation is good enough to ensure that a guest
1396 * can use these with minimal performance degradation. The drawback is
1397 * that we don't implement any of the external debug, none of the
1398 * OSlock protocol. This should be revisited if we ever encounter a
1399 * more demanding guest...
1401 static const struct sys_reg_desc sys_reg_descs[] = {
1402 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1403 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1404 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1406 DBG_BCR_BVR_WCR_WVR_EL1(0),
1407 DBG_BCR_BVR_WCR_WVR_EL1(1),
1408 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1409 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1410 DBG_BCR_BVR_WCR_WVR_EL1(2),
1411 DBG_BCR_BVR_WCR_WVR_EL1(3),
1412 DBG_BCR_BVR_WCR_WVR_EL1(4),
1413 DBG_BCR_BVR_WCR_WVR_EL1(5),
1414 DBG_BCR_BVR_WCR_WVR_EL1(6),
1415 DBG_BCR_BVR_WCR_WVR_EL1(7),
1416 DBG_BCR_BVR_WCR_WVR_EL1(8),
1417 DBG_BCR_BVR_WCR_WVR_EL1(9),
1418 DBG_BCR_BVR_WCR_WVR_EL1(10),
1419 DBG_BCR_BVR_WCR_WVR_EL1(11),
1420 DBG_BCR_BVR_WCR_WVR_EL1(12),
1421 DBG_BCR_BVR_WCR_WVR_EL1(13),
1422 DBG_BCR_BVR_WCR_WVR_EL1(14),
1423 DBG_BCR_BVR_WCR_WVR_EL1(15),
1425 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1426 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1427 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1428 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1429 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1430 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1431 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1432 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1434 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1435 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1436 // DBGDTR[TR]X_EL0 share the same encoding
1437 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1439 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1441 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1444 * ID regs: all ID_SANITISED() entries here must have corresponding
1445 * entries in arm64_ftr_regs[].
1448 /* AArch64 mappings of the AArch32 ID registers */
1450 ID_SANITISED(ID_PFR0_EL1),
1451 ID_SANITISED(ID_PFR1_EL1),
1452 ID_SANITISED(ID_DFR0_EL1),
1453 ID_HIDDEN(ID_AFR0_EL1),
1454 ID_SANITISED(ID_MMFR0_EL1),
1455 ID_SANITISED(ID_MMFR1_EL1),
1456 ID_SANITISED(ID_MMFR2_EL1),
1457 ID_SANITISED(ID_MMFR3_EL1),
1460 ID_SANITISED(ID_ISAR0_EL1),
1461 ID_SANITISED(ID_ISAR1_EL1),
1462 ID_SANITISED(ID_ISAR2_EL1),
1463 ID_SANITISED(ID_ISAR3_EL1),
1464 ID_SANITISED(ID_ISAR4_EL1),
1465 ID_SANITISED(ID_ISAR5_EL1),
1466 ID_SANITISED(ID_MMFR4_EL1),
1467 ID_SANITISED(ID_ISAR6_EL1),
1470 ID_SANITISED(MVFR0_EL1),
1471 ID_SANITISED(MVFR1_EL1),
1472 ID_SANITISED(MVFR2_EL1),
1473 ID_UNALLOCATED(3,3),
1474 ID_SANITISED(ID_PFR2_EL1),
1475 ID_HIDDEN(ID_DFR1_EL1),
1476 ID_SANITISED(ID_MMFR5_EL1),
1477 ID_UNALLOCATED(3,7),
1479 /* AArch64 ID registers */
1481 ID_SANITISED(ID_AA64PFR0_EL1),
1482 ID_SANITISED(ID_AA64PFR1_EL1),
1483 ID_UNALLOCATED(4,2),
1484 ID_UNALLOCATED(4,3),
1485 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility },
1486 ID_UNALLOCATED(4,5),
1487 ID_UNALLOCATED(4,6),
1488 ID_UNALLOCATED(4,7),
1491 ID_SANITISED(ID_AA64DFR0_EL1),
1492 ID_SANITISED(ID_AA64DFR1_EL1),
1493 ID_UNALLOCATED(5,2),
1494 ID_UNALLOCATED(5,3),
1495 ID_HIDDEN(ID_AA64AFR0_EL1),
1496 ID_HIDDEN(ID_AA64AFR1_EL1),
1497 ID_UNALLOCATED(5,6),
1498 ID_UNALLOCATED(5,7),
1501 ID_SANITISED(ID_AA64ISAR0_EL1),
1502 ID_SANITISED(ID_AA64ISAR1_EL1),
1503 ID_UNALLOCATED(6,2),
1504 ID_UNALLOCATED(6,3),
1505 ID_UNALLOCATED(6,4),
1506 ID_UNALLOCATED(6,5),
1507 ID_UNALLOCATED(6,6),
1508 ID_UNALLOCATED(6,7),
1511 ID_SANITISED(ID_AA64MMFR0_EL1),
1512 ID_SANITISED(ID_AA64MMFR1_EL1),
1513 ID_SANITISED(ID_AA64MMFR2_EL1),
1514 ID_UNALLOCATED(7,3),
1515 ID_UNALLOCATED(7,4),
1516 ID_UNALLOCATED(7,5),
1517 ID_UNALLOCATED(7,6),
1518 ID_UNALLOCATED(7,7),
1520 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1521 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1522 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1523 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1524 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1525 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1533 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1534 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1535 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1537 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1538 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1539 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1540 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1541 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1542 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1543 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1544 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1546 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1547 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1549 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1550 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1552 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1553 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1555 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1556 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1557 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1558 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1559 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1561 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1562 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1564 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1565 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1566 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1567 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1568 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1569 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1570 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1571 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1572 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1573 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1574 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1575 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1577 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1578 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1580 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1582 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1583 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1584 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1585 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1587 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
1588 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1589 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1590 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1591 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1592 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1593 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1594 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1595 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1596 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1597 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1599 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1600 * in 32bit mode. Here we choose to reset it as zero for consistency.
1602 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1603 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1605 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1606 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1608 { SYS_DESC(SYS_AMCR_EL0), access_amu },
1609 { SYS_DESC(SYS_AMCFGR_EL0), access_amu },
1610 { SYS_DESC(SYS_AMCGCR_EL0), access_amu },
1611 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu },
1612 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu },
1613 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu },
1614 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu },
1615 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu },
1616 AMU_AMEVCNTR0_EL0(0),
1617 AMU_AMEVCNTR0_EL0(1),
1618 AMU_AMEVCNTR0_EL0(2),
1619 AMU_AMEVCNTR0_EL0(3),
1620 AMU_AMEVCNTR0_EL0(4),
1621 AMU_AMEVCNTR0_EL0(5),
1622 AMU_AMEVCNTR0_EL0(6),
1623 AMU_AMEVCNTR0_EL0(7),
1624 AMU_AMEVCNTR0_EL0(8),
1625 AMU_AMEVCNTR0_EL0(9),
1626 AMU_AMEVCNTR0_EL0(10),
1627 AMU_AMEVCNTR0_EL0(11),
1628 AMU_AMEVCNTR0_EL0(12),
1629 AMU_AMEVCNTR0_EL0(13),
1630 AMU_AMEVCNTR0_EL0(14),
1631 AMU_AMEVCNTR0_EL0(15),
1632 AMU_AMEVTYPE0_EL0(0),
1633 AMU_AMEVTYPE0_EL0(1),
1634 AMU_AMEVTYPE0_EL0(2),
1635 AMU_AMEVTYPE0_EL0(3),
1636 AMU_AMEVTYPE0_EL0(4),
1637 AMU_AMEVTYPE0_EL0(5),
1638 AMU_AMEVTYPE0_EL0(6),
1639 AMU_AMEVTYPE0_EL0(7),
1640 AMU_AMEVTYPE0_EL0(8),
1641 AMU_AMEVTYPE0_EL0(9),
1642 AMU_AMEVTYPE0_EL0(10),
1643 AMU_AMEVTYPE0_EL0(11),
1644 AMU_AMEVTYPE0_EL0(12),
1645 AMU_AMEVTYPE0_EL0(13),
1646 AMU_AMEVTYPE0_EL0(14),
1647 AMU_AMEVTYPE0_EL0(15),
1648 AMU_AMEVCNTR1_EL0(0),
1649 AMU_AMEVCNTR1_EL0(1),
1650 AMU_AMEVCNTR1_EL0(2),
1651 AMU_AMEVCNTR1_EL0(3),
1652 AMU_AMEVCNTR1_EL0(4),
1653 AMU_AMEVCNTR1_EL0(5),
1654 AMU_AMEVCNTR1_EL0(6),
1655 AMU_AMEVCNTR1_EL0(7),
1656 AMU_AMEVCNTR1_EL0(8),
1657 AMU_AMEVCNTR1_EL0(9),
1658 AMU_AMEVCNTR1_EL0(10),
1659 AMU_AMEVCNTR1_EL0(11),
1660 AMU_AMEVCNTR1_EL0(12),
1661 AMU_AMEVCNTR1_EL0(13),
1662 AMU_AMEVCNTR1_EL0(14),
1663 AMU_AMEVCNTR1_EL0(15),
1664 AMU_AMEVTYPE1_EL0(0),
1665 AMU_AMEVTYPE1_EL0(1),
1666 AMU_AMEVTYPE1_EL0(2),
1667 AMU_AMEVTYPE1_EL0(3),
1668 AMU_AMEVTYPE1_EL0(4),
1669 AMU_AMEVTYPE1_EL0(5),
1670 AMU_AMEVTYPE1_EL0(6),
1671 AMU_AMEVTYPE1_EL0(7),
1672 AMU_AMEVTYPE1_EL0(8),
1673 AMU_AMEVTYPE1_EL0(9),
1674 AMU_AMEVTYPE1_EL0(10),
1675 AMU_AMEVTYPE1_EL0(11),
1676 AMU_AMEVTYPE1_EL0(12),
1677 AMU_AMEVTYPE1_EL0(13),
1678 AMU_AMEVTYPE1_EL0(14),
1679 AMU_AMEVTYPE1_EL0(15),
1681 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1682 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1683 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1686 PMU_PMEVCNTR_EL0(0),
1687 PMU_PMEVCNTR_EL0(1),
1688 PMU_PMEVCNTR_EL0(2),
1689 PMU_PMEVCNTR_EL0(3),
1690 PMU_PMEVCNTR_EL0(4),
1691 PMU_PMEVCNTR_EL0(5),
1692 PMU_PMEVCNTR_EL0(6),
1693 PMU_PMEVCNTR_EL0(7),
1694 PMU_PMEVCNTR_EL0(8),
1695 PMU_PMEVCNTR_EL0(9),
1696 PMU_PMEVCNTR_EL0(10),
1697 PMU_PMEVCNTR_EL0(11),
1698 PMU_PMEVCNTR_EL0(12),
1699 PMU_PMEVCNTR_EL0(13),
1700 PMU_PMEVCNTR_EL0(14),
1701 PMU_PMEVCNTR_EL0(15),
1702 PMU_PMEVCNTR_EL0(16),
1703 PMU_PMEVCNTR_EL0(17),
1704 PMU_PMEVCNTR_EL0(18),
1705 PMU_PMEVCNTR_EL0(19),
1706 PMU_PMEVCNTR_EL0(20),
1707 PMU_PMEVCNTR_EL0(21),
1708 PMU_PMEVCNTR_EL0(22),
1709 PMU_PMEVCNTR_EL0(23),
1710 PMU_PMEVCNTR_EL0(24),
1711 PMU_PMEVCNTR_EL0(25),
1712 PMU_PMEVCNTR_EL0(26),
1713 PMU_PMEVCNTR_EL0(27),
1714 PMU_PMEVCNTR_EL0(28),
1715 PMU_PMEVCNTR_EL0(29),
1716 PMU_PMEVCNTR_EL0(30),
1717 /* PMEVTYPERn_EL0 */
1718 PMU_PMEVTYPER_EL0(0),
1719 PMU_PMEVTYPER_EL0(1),
1720 PMU_PMEVTYPER_EL0(2),
1721 PMU_PMEVTYPER_EL0(3),
1722 PMU_PMEVTYPER_EL0(4),
1723 PMU_PMEVTYPER_EL0(5),
1724 PMU_PMEVTYPER_EL0(6),
1725 PMU_PMEVTYPER_EL0(7),
1726 PMU_PMEVTYPER_EL0(8),
1727 PMU_PMEVTYPER_EL0(9),
1728 PMU_PMEVTYPER_EL0(10),
1729 PMU_PMEVTYPER_EL0(11),
1730 PMU_PMEVTYPER_EL0(12),
1731 PMU_PMEVTYPER_EL0(13),
1732 PMU_PMEVTYPER_EL0(14),
1733 PMU_PMEVTYPER_EL0(15),
1734 PMU_PMEVTYPER_EL0(16),
1735 PMU_PMEVTYPER_EL0(17),
1736 PMU_PMEVTYPER_EL0(18),
1737 PMU_PMEVTYPER_EL0(19),
1738 PMU_PMEVTYPER_EL0(20),
1739 PMU_PMEVTYPER_EL0(21),
1740 PMU_PMEVTYPER_EL0(22),
1741 PMU_PMEVTYPER_EL0(23),
1742 PMU_PMEVTYPER_EL0(24),
1743 PMU_PMEVTYPER_EL0(25),
1744 PMU_PMEVTYPER_EL0(26),
1745 PMU_PMEVTYPER_EL0(27),
1746 PMU_PMEVTYPER_EL0(28),
1747 PMU_PMEVTYPER_EL0(29),
1748 PMU_PMEVTYPER_EL0(30),
1750 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1751 * in 32bit mode. Here we choose to reset it as zero for consistency.
1753 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1755 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1756 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1757 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1760 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1761 struct sys_reg_params *p,
1762 const struct sys_reg_desc *r)
1765 return ignore_write(vcpu, p);
1767 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1768 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1769 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1771 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1772 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1773 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1774 | (6 << 16) | (el3 << 14) | (el3 << 12));
1779 static bool trap_debug32(struct kvm_vcpu *vcpu,
1780 struct sys_reg_params *p,
1781 const struct sys_reg_desc *r)
1784 vcpu_cp14(vcpu, r->reg) = p->regval;
1785 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1787 p->regval = vcpu_cp14(vcpu, r->reg);
1793 /* AArch32 debug register mappings
1795 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1796 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1798 * All control registers and watchpoint value registers are mapped to
1799 * the lower 32 bits of their AArch64 equivalents. We share the trap
1800 * handlers with the above AArch64 code which checks what mode the
1804 static bool trap_xvr(struct kvm_vcpu *vcpu,
1805 struct sys_reg_params *p,
1806 const struct sys_reg_desc *rd)
1808 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1813 val &= 0xffffffffUL;
1814 val |= p->regval << 32;
1817 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1819 p->regval = *dbg_reg >> 32;
1822 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1827 #define DBG_BCR_BVR_WCR_WVR(n) \
1829 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1831 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1833 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1835 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1837 #define DBGBXVR(n) \
1838 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1841 * Trapped cp14 registers. We generally ignore most of the external
1842 * debug, on the principle that they don't really make sense to a
1843 * guest. Revisit this one day, would this principle change.
1845 static const struct sys_reg_desc cp14_regs[] = {
1847 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1849 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1851 DBG_BCR_BVR_WCR_WVR(0),
1853 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1854 DBG_BCR_BVR_WCR_WVR(1),
1856 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1858 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1859 DBG_BCR_BVR_WCR_WVR(2),
1860 /* DBGDTR[RT]Xint */
1861 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1862 /* DBGDTR[RT]Xext */
1863 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1864 DBG_BCR_BVR_WCR_WVR(3),
1865 DBG_BCR_BVR_WCR_WVR(4),
1866 DBG_BCR_BVR_WCR_WVR(5),
1868 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1870 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1871 DBG_BCR_BVR_WCR_WVR(6),
1873 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1874 DBG_BCR_BVR_WCR_WVR(7),
1875 DBG_BCR_BVR_WCR_WVR(8),
1876 DBG_BCR_BVR_WCR_WVR(9),
1877 DBG_BCR_BVR_WCR_WVR(10),
1878 DBG_BCR_BVR_WCR_WVR(11),
1879 DBG_BCR_BVR_WCR_WVR(12),
1880 DBG_BCR_BVR_WCR_WVR(13),
1881 DBG_BCR_BVR_WCR_WVR(14),
1882 DBG_BCR_BVR_WCR_WVR(15),
1884 /* DBGDRAR (32bit) */
1885 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1889 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1892 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1896 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1899 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1912 /* DBGDSAR (32bit) */
1913 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1916 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1918 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1920 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1922 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1924 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1926 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1929 /* Trapped cp14 64bit registers */
1930 static const struct sys_reg_desc cp14_64_regs[] = {
1931 /* DBGDRAR (64bit) */
1932 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1934 /* DBGDSAR (64bit) */
1935 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1938 /* Macro to expand the PMEVCNTRn register */
1939 #define PMU_PMEVCNTR(n) \
1941 { Op1(0), CRn(0b1110), \
1942 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1945 /* Macro to expand the PMEVTYPERn register */
1946 #define PMU_PMEVTYPER(n) \
1948 { Op1(0), CRn(0b1110), \
1949 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1950 access_pmu_evtyper }
1953 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1954 * depending on the way they are accessed (as a 32bit or a 64bit
1957 static const struct sys_reg_desc cp15_regs[] = {
1958 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1959 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1960 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1961 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1962 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1963 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1964 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1965 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1966 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1967 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1968 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1969 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1972 * DC{C,I,CI}SW operations:
1974 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1975 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1976 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1979 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1980 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1981 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1982 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1983 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1984 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1985 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1986 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1987 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1988 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1989 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1990 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1991 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1992 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1993 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1995 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1996 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1997 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1998 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
2001 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2003 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
2006 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2007 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2074 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2076 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2077 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2078 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
2081 static const struct sys_reg_desc cp15_64_regs[] = {
2082 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
2083 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2084 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2085 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
2086 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2087 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2088 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2091 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2096 for (i = 0; i < n; i++) {
2097 if (!is_32 && table[i].reg && !table[i].reset) {
2098 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2103 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2104 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2112 /* Target specific emulation tables */
2113 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
2115 void kvm_register_target_sys_reg_table(unsigned int target,
2116 struct kvm_sys_reg_target_table *table)
2118 if (check_sysreg_table(table->table64.table, table->table64.num, false) ||
2119 check_sysreg_table(table->table32.table, table->table32.num, true))
2122 target_tables[target] = table;
2125 /* Get specific register table for this target. */
2126 static const struct sys_reg_desc *get_target_table(unsigned target,
2130 struct kvm_sys_reg_target_table *table;
2132 table = target_tables[target];
2134 *num = table->table64.num;
2135 return table->table64.table;
2137 *num = table->table32.num;
2138 return table->table32.table;
2142 static int match_sys_reg(const void *key, const void *elt)
2144 const unsigned long pval = (unsigned long)key;
2145 const struct sys_reg_desc *r = elt;
2147 return pval - reg_to_encoding(r);
2150 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2151 const struct sys_reg_desc table[],
2154 unsigned long pval = reg_to_encoding(params);
2156 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
2159 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
2161 kvm_inject_undefined(vcpu);
2165 static void perform_access(struct kvm_vcpu *vcpu,
2166 struct sys_reg_params *params,
2167 const struct sys_reg_desc *r)
2169 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2171 /* Check for regs disabled by runtime config */
2172 if (sysreg_hidden_from_guest(vcpu, r)) {
2173 kvm_inject_undefined(vcpu);
2178 * Not having an accessor means that we have configured a trap
2179 * that we don't know how to handle. This certainly qualifies
2180 * as a gross bug that should be fixed right away.
2184 /* Skip instruction if instructed so */
2185 if (likely(r->access(vcpu, params, r)))
2186 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
2190 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2191 * call the corresponding trap handler.
2193 * @params: pointer to the descriptor of the access
2194 * @table: array of trap descriptors
2195 * @num: size of the trap descriptor array
2197 * Return 0 if the access has been handled, and -1 if not.
2199 static int emulate_cp(struct kvm_vcpu *vcpu,
2200 struct sys_reg_params *params,
2201 const struct sys_reg_desc *table,
2204 const struct sys_reg_desc *r;
2207 return -1; /* Not handled */
2209 r = find_reg(params, table, num);
2212 perform_access(vcpu, params, r);
2220 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2221 struct sys_reg_params *params)
2223 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
2227 case ESR_ELx_EC_CP15_32:
2228 case ESR_ELx_EC_CP15_64:
2231 case ESR_ELx_EC_CP14_MR:
2232 case ESR_ELx_EC_CP14_64:
2239 print_sys_reg_msg(params,
2240 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2241 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2242 kvm_inject_undefined(vcpu);
2246 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2247 * @vcpu: The VCPU pointer
2248 * @run: The kvm_run struct
2250 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2251 const struct sys_reg_desc *global,
2253 const struct sys_reg_desc *target_specific,
2256 struct sys_reg_params params;
2257 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2258 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2259 int Rt2 = (hsr >> 10) & 0x1f;
2261 params.is_aarch32 = true;
2262 params.is_32bit = false;
2263 params.CRm = (hsr >> 1) & 0xf;
2264 params.is_write = ((hsr & 1) == 0);
2267 params.Op1 = (hsr >> 16) & 0xf;
2272 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2273 * backends between AArch32 and AArch64, we get away with it.
2275 if (params.is_write) {
2276 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2277 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2281 * Try to emulate the coprocessor access using the target
2282 * specific table first, and using the global table afterwards.
2283 * If either of the tables contains a handler, handle the
2284 * potential register operation in the case of a read and return
2287 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) ||
2288 !emulate_cp(vcpu, ¶ms, global, nr_global)) {
2289 /* Split up the value between registers for the read side */
2290 if (!params.is_write) {
2291 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2292 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2298 unhandled_cp_access(vcpu, ¶ms);
2303 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2304 * @vcpu: The VCPU pointer
2305 * @run: The kvm_run struct
2307 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2308 const struct sys_reg_desc *global,
2310 const struct sys_reg_desc *target_specific,
2313 struct sys_reg_params params;
2314 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2315 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2317 params.is_aarch32 = true;
2318 params.is_32bit = true;
2319 params.CRm = (hsr >> 1) & 0xf;
2320 params.regval = vcpu_get_reg(vcpu, Rt);
2321 params.is_write = ((hsr & 1) == 0);
2322 params.CRn = (hsr >> 10) & 0xf;
2324 params.Op1 = (hsr >> 14) & 0x7;
2325 params.Op2 = (hsr >> 17) & 0x7;
2327 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) ||
2328 !emulate_cp(vcpu, ¶ms, global, nr_global)) {
2329 if (!params.is_write)
2330 vcpu_set_reg(vcpu, Rt, params.regval);
2334 unhandled_cp_access(vcpu, ¶ms);
2338 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2340 const struct sys_reg_desc *target_specific;
2343 target_specific = get_target_table(vcpu->arch.target, false, &num);
2344 return kvm_handle_cp_64(vcpu,
2345 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
2346 target_specific, num);
2349 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2351 const struct sys_reg_desc *target_specific;
2354 target_specific = get_target_table(vcpu->arch.target, false, &num);
2355 return kvm_handle_cp_32(vcpu,
2356 cp15_regs, ARRAY_SIZE(cp15_regs),
2357 target_specific, num);
2360 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2362 return kvm_handle_cp_64(vcpu,
2363 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
2367 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2369 return kvm_handle_cp_32(vcpu,
2370 cp14_regs, ARRAY_SIZE(cp14_regs),
2374 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2376 // See ARM DDI 0487E.a, section D12.3.2
2377 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2380 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2381 struct sys_reg_params *params)
2384 const struct sys_reg_desc *table, *r;
2386 table = get_target_table(vcpu->arch.target, true, &num);
2388 /* Search target-specific then generic table. */
2389 r = find_reg(params, table, num);
2391 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2394 perform_access(vcpu, params, r);
2395 } else if (is_imp_def_sys_reg(params)) {
2396 kvm_inject_undefined(vcpu);
2398 print_sys_reg_msg(params,
2399 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2400 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2401 kvm_inject_undefined(vcpu);
2406 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
2407 const struct sys_reg_desc *table, size_t num)
2411 for (i = 0; i < num; i++)
2413 table[i].reset(vcpu, &table[i]);
2417 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2418 * @vcpu: The VCPU pointer
2419 * @run: The kvm_run struct
2421 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
2423 struct sys_reg_params params;
2424 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2425 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2428 trace_kvm_handle_sys_reg(esr);
2430 params.is_aarch32 = false;
2431 params.is_32bit = false;
2432 params.Op0 = (esr >> 20) & 3;
2433 params.Op1 = (esr >> 14) & 0x7;
2434 params.CRn = (esr >> 10) & 0xf;
2435 params.CRm = (esr >> 1) & 0xf;
2436 params.Op2 = (esr >> 17) & 0x7;
2437 params.regval = vcpu_get_reg(vcpu, Rt);
2438 params.is_write = !(esr & 1);
2440 ret = emulate_sys_reg(vcpu, ¶ms);
2442 if (!params.is_write)
2443 vcpu_set_reg(vcpu, Rt, params.regval);
2447 /******************************************************************************
2449 *****************************************************************************/
2451 static bool index_to_params(u64 id, struct sys_reg_params *params)
2453 switch (id & KVM_REG_SIZE_MASK) {
2454 case KVM_REG_SIZE_U64:
2455 /* Any unused index bits means it's not valid. */
2456 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2457 | KVM_REG_ARM_COPROC_MASK
2458 | KVM_REG_ARM64_SYSREG_OP0_MASK
2459 | KVM_REG_ARM64_SYSREG_OP1_MASK
2460 | KVM_REG_ARM64_SYSREG_CRN_MASK
2461 | KVM_REG_ARM64_SYSREG_CRM_MASK
2462 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2464 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2465 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2466 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2467 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2468 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2469 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2470 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2471 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2472 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2473 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2480 const struct sys_reg_desc *find_reg_by_id(u64 id,
2481 struct sys_reg_params *params,
2482 const struct sys_reg_desc table[],
2485 if (!index_to_params(id, params))
2488 return find_reg(params, table, num);
2491 /* Decode an index value, and find the sys_reg_desc entry. */
2492 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2496 const struct sys_reg_desc *table, *r;
2497 struct sys_reg_params params;
2499 /* We only do sys_reg for now. */
2500 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2503 if (!index_to_params(id, ¶ms))
2506 table = get_target_table(vcpu->arch.target, true, &num);
2507 r = find_reg(¶ms, table, num);
2509 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2511 /* Not saved in the sys_reg array and not otherwise accessible? */
2512 if (r && !(r->reg || r->get_user))
2519 * These are the invariant sys_reg registers: we let the guest see the
2520 * host versions of these, so they're part of the guest state.
2522 * A future CPU may provide a mechanism to present different values to
2523 * the guest, or a future kvm may trap them.
2526 #define FUNCTION_INVARIANT(reg) \
2527 static void get_##reg(struct kvm_vcpu *v, \
2528 const struct sys_reg_desc *r) \
2530 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2533 FUNCTION_INVARIANT(midr_el1)
2534 FUNCTION_INVARIANT(revidr_el1)
2535 FUNCTION_INVARIANT(clidr_el1)
2536 FUNCTION_INVARIANT(aidr_el1)
2538 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2540 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2543 /* ->val is filled in by kvm_sys_reg_table_init() */
2544 static struct sys_reg_desc invariant_sys_regs[] = {
2545 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2546 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2547 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2548 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2549 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2552 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2554 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2559 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2561 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2566 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2568 struct sys_reg_params params;
2569 const struct sys_reg_desc *r;
2571 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2572 ARRAY_SIZE(invariant_sys_regs));
2576 return reg_to_user(uaddr, &r->val, id);
2579 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2581 struct sys_reg_params params;
2582 const struct sys_reg_desc *r;
2584 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2586 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2587 ARRAY_SIZE(invariant_sys_regs));
2591 err = reg_from_user(&val, uaddr, id);
2595 /* This is what we mean by invariant: you can't change it. */
2602 static bool is_valid_cache(u32 val)
2606 if (val >= CSSELR_MAX)
2609 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2611 ctype = (cache_levels >> (level * 3)) & 7;
2614 case 0: /* No cache */
2616 case 1: /* Instruction cache only */
2618 case 2: /* Data cache only */
2619 case 4: /* Unified cache */
2621 case 3: /* Separate instruction and data caches */
2623 default: /* Reserved: we can't know instruction or data. */
2628 static int demux_c15_get(u64 id, void __user *uaddr)
2631 u32 __user *uval = uaddr;
2633 /* Fail if we have unknown bits set. */
2634 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2635 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2638 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2639 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2640 if (KVM_REG_SIZE(id) != 4)
2642 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2643 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2644 if (!is_valid_cache(val))
2647 return put_user(get_ccsidr(val), uval);
2653 static int demux_c15_set(u64 id, void __user *uaddr)
2656 u32 __user *uval = uaddr;
2658 /* Fail if we have unknown bits set. */
2659 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2660 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2663 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2664 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2665 if (KVM_REG_SIZE(id) != 4)
2667 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2668 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2669 if (!is_valid_cache(val))
2672 if (get_user(newval, uval))
2675 /* This is also invariant: you can't change it. */
2676 if (newval != get_ccsidr(val))
2684 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2686 const struct sys_reg_desc *r;
2687 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2689 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2690 return demux_c15_get(reg->id, uaddr);
2692 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2695 r = index_to_sys_reg_desc(vcpu, reg->id);
2697 return get_invariant_sys_reg(reg->id, uaddr);
2699 /* Check for regs disabled by runtime config */
2700 if (sysreg_hidden_from_user(vcpu, r))
2704 return (r->get_user)(vcpu, r, reg, uaddr);
2706 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2709 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2711 const struct sys_reg_desc *r;
2712 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2714 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2715 return demux_c15_set(reg->id, uaddr);
2717 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2720 r = index_to_sys_reg_desc(vcpu, reg->id);
2722 return set_invariant_sys_reg(reg->id, uaddr);
2724 /* Check for regs disabled by runtime config */
2725 if (sysreg_hidden_from_user(vcpu, r))
2729 return (r->set_user)(vcpu, r, reg, uaddr);
2731 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2734 static unsigned int num_demux_regs(void)
2736 unsigned int i, count = 0;
2738 for (i = 0; i < CSSELR_MAX; i++)
2739 if (is_valid_cache(i))
2745 static int write_demux_regids(u64 __user *uindices)
2747 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2750 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2751 for (i = 0; i < CSSELR_MAX; i++) {
2752 if (!is_valid_cache(i))
2754 if (put_user(val | i, uindices))
2761 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2763 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2764 KVM_REG_ARM64_SYSREG |
2765 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2766 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2767 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2768 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2769 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2772 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2777 if (put_user(sys_reg_to_index(reg), *uind))
2784 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2785 const struct sys_reg_desc *rd,
2787 unsigned int *total)
2790 * Ignore registers we trap but don't save,
2791 * and for which no custom user accessor is provided.
2793 if (!(rd->reg || rd->get_user))
2796 if (sysreg_hidden_from_user(vcpu, rd))
2799 if (!copy_reg_to_user(rd, uind))
2806 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2807 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2809 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2810 unsigned int total = 0;
2814 /* We check for duplicates here, to allow arch-specific overrides. */
2815 i1 = get_target_table(vcpu->arch.target, true, &num);
2818 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2820 BUG_ON(i1 == end1 || i2 == end2);
2822 /* Walk carefully, as both tables may refer to the same register. */
2824 int cmp = cmp_sys_reg(i1, i2);
2825 /* target-specific overrides generic entry. */
2827 err = walk_one_sys_reg(vcpu, i1, &uind, &total);
2829 err = walk_one_sys_reg(vcpu, i2, &uind, &total);
2834 if (cmp <= 0 && ++i1 == end1)
2836 if (cmp >= 0 && ++i2 == end2)
2842 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2844 return ARRAY_SIZE(invariant_sys_regs)
2846 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2849 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2854 /* Then give them all the invariant registers' indices. */
2855 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2856 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2861 err = walk_sys_regs(vcpu, uindices);
2866 return write_demux_regids(uindices);
2869 void kvm_sys_reg_table_init(void)
2872 struct sys_reg_desc clidr;
2874 /* Make sure tables are unique and in order. */
2875 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2876 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2877 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2878 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2879 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2880 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
2882 /* We abuse the reset function to overwrite the table itself. */
2883 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2884 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2887 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2889 * If software reads the Cache Type fields from Ctype1
2890 * upwards, once it has seen a value of 0b000, no caches
2891 * exist at further-out levels of the hierarchy. So, for
2892 * example, if Ctype3 is the first Cache Type field with a
2893 * value of 0b000, the values of Ctype4 to Ctype7 must be
2896 get_clidr_el1(NULL, &clidr); /* Ugly... */
2897 cache_levels = clidr.val;
2898 for (i = 0; i < 7; i++)
2899 if (((cache_levels >> (i*3)) & 7) == 0)
2901 /* Clear all higher bits. */
2902 cache_levels &= (1 << (i*3))-1;
2906 * kvm_reset_sys_regs - sets system registers to reset value
2907 * @vcpu: The VCPU pointer
2909 * This function finds the right table above and sets the registers on the
2910 * virtual CPU struct to their architecturally defined reset values.
2912 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2915 const struct sys_reg_desc *table;
2917 /* Generic chip reset first (so target could override). */
2918 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2920 table = get_target_table(vcpu->arch.target, true, &num);
2921 reset_sys_reg_descs(vcpu, table, num);