1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <hyp/switch.h>
9 #include <linux/arm-smccc.h>
10 #include <linux/kvm_host.h>
11 #include <linux/types.h>
12 #include <linux/jump_label.h>
13 #include <uapi/linux/psci.h>
15 #include <kvm/arm_psci.h>
17 #include <asm/barrier.h>
18 #include <asm/cpufeature.h>
19 #include <asm/kprobes.h>
20 #include <asm/kvm_asm.h>
21 #include <asm/kvm_emulate.h>
22 #include <asm/kvm_hyp.h>
23 #include <asm/kvm_mmu.h>
24 #include <asm/fpsimd.h>
25 #include <asm/debug-monitors.h>
26 #include <asm/processor.h>
27 #include <asm/thread_info.h>
29 const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
31 static void __activate_traps(struct kvm_vcpu *vcpu)
35 ___activate_traps(vcpu);
37 val = read_sysreg(cpacr_el1);
39 val &= ~CPACR_EL1_ZEN;
42 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
43 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
44 * except for some missing controls, such as TAM.
45 * In this case, CPTR_EL2.TAM has the same position with or without
46 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
47 * shift value for trapping the AMU accesses.
52 if (update_fp_enabled(vcpu)) {
53 if (vcpu_has_sve(vcpu))
56 val &= ~CPACR_EL1_FPEN;
57 __activate_traps_fpsimd32(vcpu);
60 write_sysreg(val, cpacr_el1);
62 write_sysreg(kvm_get_hyp_vector(), vbar_el1);
64 NOKPROBE_SYMBOL(__activate_traps);
66 static void __deactivate_traps(struct kvm_vcpu *vcpu)
68 extern char vectors[]; /* kernel exception vectors */
70 ___deactivate_traps(vcpu);
72 write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
75 * ARM errata 1165522 and 1530923 require the actual execution of the
76 * above before we can switch to the EL2/EL0 translation regime used by
79 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
81 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
82 write_sysreg(vectors, vbar_el1);
84 NOKPROBE_SYMBOL(__deactivate_traps);
86 void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
88 __activate_traps_common(vcpu);
91 void deactivate_traps_vhe_put(void)
93 u64 mdcr_el2 = read_sysreg(mdcr_el2);
95 mdcr_el2 &= MDCR_EL2_HPMN_MASK |
96 MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
99 write_sysreg(mdcr_el2, mdcr_el2);
101 __deactivate_traps_common();
104 /* Switch to the guest for VHE systems running in EL2 */
105 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
107 struct kvm_cpu_context *host_ctxt;
108 struct kvm_cpu_context *guest_ctxt;
111 host_ctxt = &__hyp_this_cpu_ptr(kvm_host_data)->host_ctxt;
112 host_ctxt->__hyp_running_vcpu = vcpu;
113 guest_ctxt = &vcpu->arch.ctxt;
115 sysreg_save_host_state_vhe(host_ctxt);
118 * ARM erratum 1165522 requires us to configure both stage 1 and
119 * stage 2 translation for the guest context before we clear
122 * We have already configured the guest's stage 1 translation in
123 * kvm_vcpu_load_sysregs_vhe above. We must now call __activate_vm
124 * before __activate_traps, because __activate_vm configures
125 * stage 2 translation, and __activate_traps clear HCR_EL2.TGE
126 * (among other things).
128 __activate_vm(vcpu->arch.hw_mmu);
129 __activate_traps(vcpu);
131 sysreg_restore_guest_state_vhe(guest_ctxt);
132 __debug_switch_to_guest(vcpu);
134 __set_guest_arch_workaround_state(vcpu);
137 /* Jump in the fire! */
138 exit_code = __guest_enter(vcpu, host_ctxt);
140 /* And we're baaack! */
141 } while (fixup_guest_exit(vcpu, &exit_code));
143 __set_host_arch_workaround_state(vcpu);
145 sysreg_save_guest_state_vhe(guest_ctxt);
147 __deactivate_traps(vcpu);
149 sysreg_restore_host_state_vhe(host_ctxt);
151 if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
152 __fpsimd_save_fpexc32(vcpu);
154 __debug_switch_to_host(vcpu);
158 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
160 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
167 * Having IRQs masked via PMR when entering the guest means the GIC
168 * will not signal the CPU of interrupts of lower priority, and the
169 * only way to get out will be via guest exceptions.
170 * Naturally, we want to avoid this.
172 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
173 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
177 ret = __kvm_vcpu_run_vhe(vcpu);
180 * local_daif_restore() takes care to properly restore PSTATE.DAIF
181 * and the GIC PMR if the host is using IRQ priorities.
183 local_daif_restore(DAIF_PROCCTX_NOIRQ);
186 * When we exit from the guest we change a number of CPU configuration
187 * parameters, such as traps. Make sure these changes take effect
188 * before running the host or additional guests.
195 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par,
196 struct kvm_cpu_context *host_ctxt)
198 struct kvm_vcpu *vcpu;
199 vcpu = host_ctxt->__hyp_running_vcpu;
201 __deactivate_traps(vcpu);
202 sysreg_restore_host_state_vhe(host_ctxt);
204 panic(__hyp_panic_string,
206 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
207 read_sysreg(hpfar_el2), par, vcpu);
209 NOKPROBE_SYMBOL(__hyp_call_panic);
211 void __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
213 u64 spsr = read_sysreg_el2(SYS_SPSR);
214 u64 elr = read_sysreg_el2(SYS_ELR);
215 u64 par = read_sysreg(par_el1);
217 __hyp_call_panic(spsr, elr, par, host_ctxt);
221 asmlinkage void kvm_unexpected_el2_exception(void)
223 return __kvm_unexpected_el2_exception();