arch/arm64/kvm/hyp/vgic-v3-sr.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012-2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <linux/compiler.h>
   8 #include <linux/irqchip/arm-gic-v3.h>
   9 #include <linux/kvm_host.h>
  10
  11 #include <asm/kvm_emulate.h>
  12 #include <asm/kvm_hyp.h>
  13 #include <asm/kvm_mmu.h>
  14
  15 #define vtr_to_max_lr_idx(v)            ((v) & 0xf)
  16 #define vtr_to_nr_pre_bits(v)           ((((u32)(v) >> 26) & 7) + 1)
  17 #define vtr_to_nr_apr_regs(v)           (1 << (vtr_to_nr_pre_bits(v) - 5))
  18
  19 static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
  20 {
  21         switch (lr & 0xf) {
  22         case 0:
  23                 return read_gicreg(ICH_LR0_EL2);
  24         case 1:
  25                 return read_gicreg(ICH_LR1_EL2);
  26         case 2:
  27                 return read_gicreg(ICH_LR2_EL2);
  28         case 3:
  29                 return read_gicreg(ICH_LR3_EL2);
  30         case 4:
  31                 return read_gicreg(ICH_LR4_EL2);
  32         case 5:
  33                 return read_gicreg(ICH_LR5_EL2);
  34         case 6:
  35                 return read_gicreg(ICH_LR6_EL2);
  36         case 7:
  37                 return read_gicreg(ICH_LR7_EL2);
  38         case 8:
  39                 return read_gicreg(ICH_LR8_EL2);
  40         case 9:
  41                 return read_gicreg(ICH_LR9_EL2);
  42         case 10:
  43                 return read_gicreg(ICH_LR10_EL2);
  44         case 11:
  45                 return read_gicreg(ICH_LR11_EL2);
  46         case 12:
  47                 return read_gicreg(ICH_LR12_EL2);
  48         case 13:
  49                 return read_gicreg(ICH_LR13_EL2);
  50         case 14:
  51                 return read_gicreg(ICH_LR14_EL2);
  52         case 15:
  53                 return read_gicreg(ICH_LR15_EL2);
  54         }
  55
  56         unreachable();
  57 }
  58
  59 static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
  60 {
  61         switch (lr & 0xf) {
  62         case 0:
  63                 write_gicreg(val, ICH_LR0_EL2);
  64                 break;
  65         case 1:
  66                 write_gicreg(val, ICH_LR1_EL2);
  67                 break;
  68         case 2:
  69                 write_gicreg(val, ICH_LR2_EL2);
  70                 break;
  71         case 3:
  72                 write_gicreg(val, ICH_LR3_EL2);
  73                 break;
  74         case 4:
  75                 write_gicreg(val, ICH_LR4_EL2);
  76                 break;
  77         case 5:
  78                 write_gicreg(val, ICH_LR5_EL2);
  79                 break;
  80         case 6:
  81                 write_gicreg(val, ICH_LR6_EL2);
  82                 break;
  83         case 7:
  84                 write_gicreg(val, ICH_LR7_EL2);
  85                 break;
  86         case 8:
  87                 write_gicreg(val, ICH_LR8_EL2);
  88                 break;
  89         case 9:
  90                 write_gicreg(val, ICH_LR9_EL2);
  91                 break;
  92         case 10:
  93                 write_gicreg(val, ICH_LR10_EL2);
  94                 break;
  95         case 11:
  96                 write_gicreg(val, ICH_LR11_EL2);
  97                 break;
  98         case 12:
  99                 write_gicreg(val, ICH_LR12_EL2);
 100                 break;
 101         case 13:
 102                 write_gicreg(val, ICH_LR13_EL2);
 103                 break;
 104         case 14:
 105                 write_gicreg(val, ICH_LR14_EL2);
 106                 break;
 107         case 15:
 108                 write_gicreg(val, ICH_LR15_EL2);
 109                 break;
 110         }
 111 }
 112
 113 static void __hyp_text __vgic_v3_write_ap0rn(u32 val, int n)
 114 {
 115         switch (n) {
 116         case 0:
 117                 write_gicreg(val, ICH_AP0R0_EL2);
 118                 break;
 119         case 1:
 120                 write_gicreg(val, ICH_AP0R1_EL2);
 121                 break;
 122         case 2:
 123                 write_gicreg(val, ICH_AP0R2_EL2);
 124                 break;
 125         case 3:
 126                 write_gicreg(val, ICH_AP0R3_EL2);
 127                 break;
 128         }
 129 }
 130
 131 static void __hyp_text __vgic_v3_write_ap1rn(u32 val, int n)
 132 {
 133         switch (n) {
 134         case 0:
 135                 write_gicreg(val, ICH_AP1R0_EL2);
 136                 break;
 137         case 1:
 138                 write_gicreg(val, ICH_AP1R1_EL2);
 139                 break;
 140         case 2:
 141                 write_gicreg(val, ICH_AP1R2_EL2);
 142                 break;
 143         case 3:
 144                 write_gicreg(val, ICH_AP1R3_EL2);
 145                 break;
 146         }
 147 }
 148
 149 static u32 __hyp_text __vgic_v3_read_ap0rn(int n)
 150 {
 151         u32 val;
 152
 153         switch (n) {
 154         case 0:
 155                 val = read_gicreg(ICH_AP0R0_EL2);
 156                 break;
 157         case 1:
 158                 val = read_gicreg(ICH_AP0R1_EL2);
 159                 break;
 160         case 2:
 161                 val = read_gicreg(ICH_AP0R2_EL2);
 162                 break;
 163         case 3:
 164                 val = read_gicreg(ICH_AP0R3_EL2);
 165                 break;
 166         default:
 167                 unreachable();
 168         }
 169
 170         return val;
 171 }
 172
 173 static u32 __hyp_text __vgic_v3_read_ap1rn(int n)
 174 {
 175         u32 val;
 176
 177         switch (n) {
 178         case 0:
 179                 val = read_gicreg(ICH_AP1R0_EL2);
 180                 break;
 181         case 1:
 182                 val = read_gicreg(ICH_AP1R1_EL2);
 183                 break;
 184         case 2:
 185                 val = read_gicreg(ICH_AP1R2_EL2);
 186                 break;
 187         case 3:
 188                 val = read_gicreg(ICH_AP1R3_EL2);
 189                 break;
 190         default:
 191                 unreachable();
 192         }
 193
 194         return val;
 195 }
 196
 197 void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
 198 {
 199         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 200         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 201
 202         /*
 203          * Make sure stores to the GIC via the memory mapped interface
 204          * are now visible to the system register interface when reading the
 205          * LRs, and when reading back the VMCR on non-VHE systems.
 206          */
 207         if (used_lrs || !has_vhe()) {
 208                 if (!cpu_if->vgic_sre) {
 209                         dsb(sy);
 210                         isb();
 211                 }
 212         }
 213
 214         if (used_lrs || cpu_if->its_vpe.its_vm) {
 215                 int i;
 216                 u32 elrsr;
 217
 218                 elrsr = read_gicreg(ICH_ELRSR_EL2);
 219
 220                 write_gicreg(cpu_if->vgic_hcr & ~ICH_HCR_EN, ICH_HCR_EL2);
 221
 222                 for (i = 0; i < used_lrs; i++) {
 223                         if (elrsr & (1 << i))
 224                                 cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
 225                         else
 226                                 cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
 227
 228                         __gic_v3_set_lr(0, i);
 229                 }
 230         }
 231 }
 232
 233 void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
 234 {
 235         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 236         u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 237         int i;
 238
 239         if (used_lrs || cpu_if->its_vpe.its_vm) {
 240                 write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
 241
 242                 for (i = 0; i < used_lrs; i++)
 243                         __gic_v3_set_lr(cpu_if->vgic_lr[i], i);
 244         }
 245
 246         /*
 247          * Ensure that writes to the LRs, and on non-VHE systems ensure that
 248          * the write to the VMCR in __vgic_v3_activate_traps(), will have
 249          * reached the (re)distributors. This ensure the guest will read the
 250          * correct values from the memory-mapped interface.
 251          */
 252         if (used_lrs || !has_vhe()) {
 253                 if (!cpu_if->vgic_sre) {
 254                         isb();
 255                         dsb(sy);
 256                 }
 257         }
 258 }
 259
 260 void __hyp_text __vgic_v3_activate_traps(struct kvm_vcpu *vcpu)
 261 {
 262         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 263
 264         /*
 265          * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
 266          * Group0 interrupt (as generated in GICv2 mode) to be
 267          * delivered as a FIQ to the guest, with potentially fatal
 268          * consequences. So we must make sure that ICC_SRE_EL1 has
 269          * been actually programmed with the value we want before
 270          * starting to mess with the rest of the GIC, and VMCR_EL2 in
 271          * particular.  This logic must be called before
 272          * __vgic_v3_restore_state().
 273          */
 274         if (!cpu_if->vgic_sre) {
 275                 write_gicreg(0, ICC_SRE_EL1);
 276                 isb();
 277                 write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
 278
 279
 280                 if (has_vhe()) {
 281                         /*
 282                          * Ensure that the write to the VMCR will have reached
 283                          * the (re)distributors. This ensure the guest will
 284                          * read the correct values from the memory-mapped
 285                          * interface.
 286                          */
 287                         isb();
 288                         dsb(sy);
 289                 }
 290         }
 291
 292         /*
 293          * Prevent the guest from touching the GIC system registers if
 294          * SRE isn't enabled for GICv3 emulation.
 295          */
 296         write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
 297                      ICC_SRE_EL2);
 298
 299         /*
 300          * If we need to trap system registers, we must write
 301          * ICH_HCR_EL2 anyway, even if no interrupts are being
 302          * injected,
 303          */
 304         if (static_branch_unlikely(&vgic_v3_cpuif_trap) ||
 305             cpu_if->its_vpe.its_vm)
 306                 write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
 307 }
 308
 309 void __hyp_text __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu)
 310 {
 311         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 312         u64 val;
 313
 314         if (!cpu_if->vgic_sre) {
 315                 cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
 316         }
 317
 318         val = read_gicreg(ICC_SRE_EL2);
 319         write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
 320
 321         if (!cpu_if->vgic_sre) {
 322                 /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
 323                 isb();
 324                 write_gicreg(1, ICC_SRE_EL1);
 325         }
 326
 327         /*
 328          * If we were trapping system registers, we enabled the VGIC even if
 329          * no interrupts were being injected, and we disable it again here.
 330          */
 331         if (static_branch_unlikely(&vgic_v3_cpuif_trap) ||
 332             cpu_if->its_vpe.its_vm)
 333                 write_gicreg(0, ICH_HCR_EL2);
 334 }
 335
 336 void __hyp_text __vgic_v3_save_aprs(struct kvm_vcpu *vcpu)
 337 {
 338         struct vgic_v3_cpu_if *cpu_if;
 339         u64 val;
 340         u32 nr_pre_bits;
 341
 342         vcpu = kern_hyp_va(vcpu);
 343         cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 344
 345         val = read_gicreg(ICH_VTR_EL2);
 346         nr_pre_bits = vtr_to_nr_pre_bits(val);
 347
 348         switch (nr_pre_bits) {
 349         case 7:
 350                 cpu_if->vgic_ap0r[3] = __vgic_v3_read_ap0rn(3);
 351                 cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2);
 352                 /* Fall through */
 353         case 6:
 354                 cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1);
 355                 /* Fall through */
 356         default:
 357                 cpu_if->vgic_ap0r[0] = __vgic_v3_read_ap0rn(0);
 358         }
 359
 360         switch (nr_pre_bits) {
 361         case 7:
 362                 cpu_if->vgic_ap1r[3] = __vgic_v3_read_ap1rn(3);
 363                 cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2);
 364                 /* Fall through */
 365         case 6:
 366                 cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1);
 367                 /* Fall through */
 368         default:
 369                 cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0);
 370         }
 371 }
 372
 373 void __hyp_text __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu)
 374 {
 375         struct vgic_v3_cpu_if *cpu_if;
 376         u64 val;
 377         u32 nr_pre_bits;
 378
 379         vcpu = kern_hyp_va(vcpu);
 380         cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 381
 382         val = read_gicreg(ICH_VTR_EL2);
 383         nr_pre_bits = vtr_to_nr_pre_bits(val);
 384
 385         switch (nr_pre_bits) {
 386         case 7:
 387                 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[3], 3);
 388                 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[2], 2);
 389                 /* Fall through */
 390         case 6:
 391                 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[1], 1);
 392                 /* Fall through */
 393         default:
 394                 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[0], 0);
 395         }
 396
 397         switch (nr_pre_bits) {
 398         case 7:
 399                 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[3], 3);
 400                 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[2], 2);
 401                 /* Fall through */
 402         case 6:
 403                 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[1], 1);
 404                 /* Fall through */
 405         default:
 406                 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[0], 0);
 407         }
 408 }
 409
 410 void __hyp_text __vgic_v3_init_lrs(void)
 411 {
 412         int max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
 413         int i;
 414
 415         for (i = 0; i <= max_lr_idx; i++)
 416                 __gic_v3_set_lr(0, i);
 417 }
 418
 419 u64 __hyp_text __vgic_v3_get_ich_vtr_el2(void)
 420 {
 421         return read_gicreg(ICH_VTR_EL2);
 422 }
 423
 424 u64 __hyp_text __vgic_v3_read_vmcr(void)
 425 {
 426         return read_gicreg(ICH_VMCR_EL2);
 427 }
 428
 429 void __hyp_text __vgic_v3_write_vmcr(u32 vmcr)
 430 {
 431         write_gicreg(vmcr, ICH_VMCR_EL2);
 432 }
 433
 434 static int __hyp_text __vgic_v3_bpr_min(void)
 435 {
 436         /* See Pseudocode for VPriorityGroup */
 437         return 8 - vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2));
 438 }
 439
 440 static int __hyp_text __vgic_v3_get_group(struct kvm_vcpu *vcpu)
 441 {
 442         u32 esr = kvm_vcpu_get_hsr(vcpu);
 443         u8 crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 444
 445         return crm != 8;
 446 }
 447
 448 #define GICv3_IDLE_PRIORITY     0xff
 449
 450 static int __hyp_text __vgic_v3_highest_priority_lr(struct kvm_vcpu *vcpu,
 451                                                     u32 vmcr,
 452                                                     u64 *lr_val)
 453 {
 454         unsigned int used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 455         u8 priority = GICv3_IDLE_PRIORITY;
 456         int i, lr = -1;
 457
 458         for (i = 0; i < used_lrs; i++) {
 459                 u64 val = __gic_v3_get_lr(i);
 460                 u8 lr_prio = (val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
 461
 462                 /* Not pending in the state? */
 463                 if ((val & ICH_LR_STATE) != ICH_LR_PENDING_BIT)
 464                         continue;
 465
 466                 /* Group-0 interrupt, but Group-0 disabled? */
 467                 if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK))
 468                         continue;
 469
 470                 /* Group-1 interrupt, but Group-1 disabled? */
 471                 if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK))
 472                         continue;
 473
 474                 /* Not the highest priority? */
 475                 if (lr_prio >= priority)
 476                         continue;
 477
 478                 /* This is a candidate */
 479                 priority = lr_prio;
 480                 *lr_val = val;
 481                 lr = i;
 482         }
 483
 484         if (lr == -1)
 485                 *lr_val = ICC_IAR1_EL1_SPURIOUS;
 486
 487         return lr;
 488 }
 489
 490 static int __hyp_text __vgic_v3_find_active_lr(struct kvm_vcpu *vcpu,
 491                                                int intid, u64 *lr_val)
 492 {
 493         unsigned int used_lrs = vcpu->arch.vgic_cpu.used_lrs;
 494         int i;
 495
 496         for (i = 0; i < used_lrs; i++) {
 497                 u64 val = __gic_v3_get_lr(i);
 498
 499                 if ((val & ICH_LR_VIRTUAL_ID_MASK) == intid &&
 500                     (val & ICH_LR_ACTIVE_BIT)) {
 501                         *lr_val = val;
 502                         return i;
 503                 }
 504         }
 505
 506         *lr_val = ICC_IAR1_EL1_SPURIOUS;
 507         return -1;
 508 }
 509
 510 static int __hyp_text __vgic_v3_get_highest_active_priority(void)
 511 {
 512         u8 nr_apr_regs = vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
 513         u32 hap = 0;
 514         int i;
 515
 516         for (i = 0; i < nr_apr_regs; i++) {
 517                 u32 val;
 518
 519                 /*
 520                  * The ICH_AP0Rn_EL2 and ICH_AP1Rn_EL2 registers
 521                  * contain the active priority levels for this VCPU
 522                  * for the maximum number of supported priority
 523                  * levels, and we return the full priority level only
 524                  * if the BPR is programmed to its minimum, otherwise
 525                  * we return a combination of the priority level and
 526                  * subpriority, as determined by the setting of the
 527                  * BPR, but without the full subpriority.
 528                  */
 529                 val  = __vgic_v3_read_ap0rn(i);
 530                 val |= __vgic_v3_read_ap1rn(i);
 531                 if (!val) {
 532                         hap += 32;
 533                         continue;
 534                 }
 535
 536                 return (hap + __ffs(val)) << __vgic_v3_bpr_min();
 537         }
 538
 539         return GICv3_IDLE_PRIORITY;
 540 }
 541
 542 static unsigned int __hyp_text __vgic_v3_get_bpr0(u32 vmcr)
 543 {
 544         return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 545 }
 546
 547 static unsigned int __hyp_text __vgic_v3_get_bpr1(u32 vmcr)
 548 {
 549         unsigned int bpr;
 550
 551         if (vmcr & ICH_VMCR_CBPR_MASK) {
 552                 bpr = __vgic_v3_get_bpr0(vmcr);
 553                 if (bpr < 7)
 554                         bpr++;
 555         } else {
 556                 bpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 557         }
 558
 559         return bpr;
 560 }
 561
 562 /*
 563  * Convert a priority to a preemption level, taking the relevant BPR
 564  * into account by zeroing the sub-priority bits.
 565  */
 566 static u8 __hyp_text __vgic_v3_pri_to_pre(u8 pri, u32 vmcr, int grp)
 567 {
 568         unsigned int bpr;
 569
 570         if (!grp)
 571                 bpr = __vgic_v3_get_bpr0(vmcr) + 1;
 572         else
 573                 bpr = __vgic_v3_get_bpr1(vmcr);
 574
 575         return pri & (GENMASK(7, 0) << bpr);
 576 }
 577
 578 /*
 579  * The priority value is independent of any of the BPR values, so we
 580  * normalize it using the minimal BPR value. This guarantees that no
 581  * matter what the guest does with its BPR, we can always set/get the
 582  * same value of a priority.
 583  */
 584 static void __hyp_text __vgic_v3_set_active_priority(u8 pri, u32 vmcr, int grp)
 585 {
 586         u8 pre, ap;
 587         u32 val;
 588         int apr;
 589
 590         pre = __vgic_v3_pri_to_pre(pri, vmcr, grp);
 591         ap = pre >> __vgic_v3_bpr_min();
 592         apr = ap / 32;
 593
 594         if (!grp) {
 595                 val = __vgic_v3_read_ap0rn(apr);
 596                 __vgic_v3_write_ap0rn(val | BIT(ap % 32), apr);
 597         } else {
 598                 val = __vgic_v3_read_ap1rn(apr);
 599                 __vgic_v3_write_ap1rn(val | BIT(ap % 32), apr);
 600         }
 601 }
 602
 603 static int __hyp_text __vgic_v3_clear_highest_active_priority(void)
 604 {
 605         u8 nr_apr_regs = vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2));
 606         u32 hap = 0;
 607         int i;
 608
 609         for (i = 0; i < nr_apr_regs; i++) {
 610                 u32 ap0, ap1;
 611                 int c0, c1;
 612
 613                 ap0 = __vgic_v3_read_ap0rn(i);
 614                 ap1 = __vgic_v3_read_ap1rn(i);
 615                 if (!ap0 && !ap1) {
 616                         hap += 32;
 617                         continue;
 618                 }
 619
 620                 c0 = ap0 ? __ffs(ap0) : 32;
 621                 c1 = ap1 ? __ffs(ap1) : 32;
 622
 623                 /* Always clear the LSB, which is the highest priority */
 624                 if (c0 < c1) {
 625                         ap0 &= ~BIT(c0);
 626                         __vgic_v3_write_ap0rn(ap0, i);
 627                         hap += c0;
 628                 } else {
 629                         ap1 &= ~BIT(c1);
 630                         __vgic_v3_write_ap1rn(ap1, i);
 631                         hap += c1;
 632                 }
 633
 634                 /* Rescale to 8 bits of priority */
 635                 return hap << __vgic_v3_bpr_min();
 636         }
 637
 638         return GICv3_IDLE_PRIORITY;
 639 }
 640
 641 static void __hyp_text __vgic_v3_read_iar(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 642 {
 643         u64 lr_val;
 644         u8 lr_prio, pmr;
 645         int lr, grp;
 646
 647         grp = __vgic_v3_get_group(vcpu);
 648
 649         lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
 650         if (lr < 0)
 651                 goto spurious;
 652
 653         if (grp != !!(lr_val & ICH_LR_GROUP))
 654                 goto spurious;
 655
 656         pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 657         lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
 658         if (pmr <= lr_prio)
 659                 goto spurious;
 660
 661         if (__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio, vmcr, grp))
 662                 goto spurious;
 663
 664         lr_val &= ~ICH_LR_STATE;
 665         /* No active state for LPIs */
 666         if ((lr_val & ICH_LR_VIRTUAL_ID_MASK) <= VGIC_MAX_SPI)
 667                 lr_val |= ICH_LR_ACTIVE_BIT;
 668         __gic_v3_set_lr(lr_val, lr);
 669         __vgic_v3_set_active_priority(lr_prio, vmcr, grp);
 670         vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
 671         return;
 672
 673 spurious:
 674         vcpu_set_reg(vcpu, rt, ICC_IAR1_EL1_SPURIOUS);
 675 }
 676
 677 static void __hyp_text __vgic_v3_clear_active_lr(int lr, u64 lr_val)
 678 {
 679         lr_val &= ~ICH_LR_ACTIVE_BIT;
 680         if (lr_val & ICH_LR_HW) {
 681                 u32 pid;
 682
 683                 pid = (lr_val & ICH_LR_PHYS_ID_MASK) >> ICH_LR_PHYS_ID_SHIFT;
 684                 gic_write_dir(pid);
 685         }
 686
 687         __gic_v3_set_lr(lr_val, lr);
 688 }
 689
 690 static void __hyp_text __vgic_v3_bump_eoicount(void)
 691 {
 692         u32 hcr;
 693
 694         hcr = read_gicreg(ICH_HCR_EL2);
 695         hcr += 1 << ICH_HCR_EOIcount_SHIFT;
 696         write_gicreg(hcr, ICH_HCR_EL2);
 697 }
 698
 699 static void __hyp_text __vgic_v3_write_dir(struct kvm_vcpu *vcpu,
 700                                            u32 vmcr, int rt)
 701 {
 702         u32 vid = vcpu_get_reg(vcpu, rt);
 703         u64 lr_val;
 704         int lr;
 705
 706         /* EOImode == 0, nothing to be done here */
 707         if (!(vmcr & ICH_VMCR_EOIM_MASK))
 708                 return;
 709
 710         /* No deactivate to be performed on an LPI */
 711         if (vid >= VGIC_MIN_LPI)
 712                 return;
 713
 714         lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
 715         if (lr == -1) {
 716                 __vgic_v3_bump_eoicount();
 717                 return;
 718         }
 719
 720         __vgic_v3_clear_active_lr(lr, lr_val);
 721 }
 722
 723 static void __hyp_text __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 724 {
 725         u32 vid = vcpu_get_reg(vcpu, rt);
 726         u64 lr_val;
 727         u8 lr_prio, act_prio;
 728         int lr, grp;
 729
 730         grp = __vgic_v3_get_group(vcpu);
 731
 732         /* Drop priority in any case */
 733         act_prio = __vgic_v3_clear_highest_active_priority();
 734
 735         /* If EOIing an LPI, no deactivate to be performed */
 736         if (vid >= VGIC_MIN_LPI)
 737                 return;
 738
 739         /* EOImode == 1, nothing to be done here */
 740         if (vmcr & ICH_VMCR_EOIM_MASK)
 741                 return;
 742
 743         lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
 744         if (lr == -1) {
 745                 __vgic_v3_bump_eoicount();
 746                 return;
 747         }
 748
 749         lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
 750
 751         /* If priorities or group do not match, the guest has fscked-up. */
 752         if (grp != !!(lr_val & ICH_LR_GROUP) ||
 753             __vgic_v3_pri_to_pre(lr_prio, vmcr, grp) != act_prio)
 754                 return;
 755
 756         /* Let's now perform the deactivation */
 757         __vgic_v3_clear_active_lr(lr, lr_val);
 758 }
 759
 760 static void __hyp_text __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 761 {
 762         vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK));
 763 }
 764
 765 static void __hyp_text __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 766 {
 767         vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
 768 }
 769
 770 static void __hyp_text __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 771 {
 772         u64 val = vcpu_get_reg(vcpu, rt);
 773
 774         if (val & 1)
 775                 vmcr |= ICH_VMCR_ENG0_MASK;
 776         else
 777                 vmcr &= ~ICH_VMCR_ENG0_MASK;
 778
 779         __vgic_v3_write_vmcr(vmcr);
 780 }
 781
 782 static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 783 {
 784         u64 val = vcpu_get_reg(vcpu, rt);
 785
 786         if (val & 1)
 787                 vmcr |= ICH_VMCR_ENG1_MASK;
 788         else
 789                 vmcr &= ~ICH_VMCR_ENG1_MASK;
 790
 791         __vgic_v3_write_vmcr(vmcr);
 792 }
 793
 794 static void __hyp_text __vgic_v3_read_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 795 {
 796         vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr0(vmcr));
 797 }
 798
 799 static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 800 {
 801         vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
 802 }
 803
 804 static void __hyp_text __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 805 {
 806         u64 val = vcpu_get_reg(vcpu, rt);
 807         u8 bpr_min = __vgic_v3_bpr_min() - 1;
 808
 809         /* Enforce BPR limiting */
 810         if (val < bpr_min)
 811                 val = bpr_min;
 812
 813         val <<= ICH_VMCR_BPR0_SHIFT;
 814         val &= ICH_VMCR_BPR0_MASK;
 815         vmcr &= ~ICH_VMCR_BPR0_MASK;
 816         vmcr |= val;
 817
 818         __vgic_v3_write_vmcr(vmcr);
 819 }
 820
 821 static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 822 {
 823         u64 val = vcpu_get_reg(vcpu, rt);
 824         u8 bpr_min = __vgic_v3_bpr_min();
 825
 826         if (vmcr & ICH_VMCR_CBPR_MASK)
 827                 return;
 828
 829         /* Enforce BPR limiting */
 830         if (val < bpr_min)
 831                 val = bpr_min;
 832
 833         val <<= ICH_VMCR_BPR1_SHIFT;
 834         val &= ICH_VMCR_BPR1_MASK;
 835         vmcr &= ~ICH_VMCR_BPR1_MASK;
 836         vmcr |= val;
 837
 838         __vgic_v3_write_vmcr(vmcr);
 839 }
 840
 841 static void __hyp_text __vgic_v3_read_apxrn(struct kvm_vcpu *vcpu, int rt, int n)
 842 {
 843         u32 val;
 844
 845         if (!__vgic_v3_get_group(vcpu))
 846                 val = __vgic_v3_read_ap0rn(n);
 847         else
 848                 val = __vgic_v3_read_ap1rn(n);
 849
 850         vcpu_set_reg(vcpu, rt, val);
 851 }
 852
 853 static void __hyp_text __vgic_v3_write_apxrn(struct kvm_vcpu *vcpu, int rt, int n)
 854 {
 855         u32 val = vcpu_get_reg(vcpu, rt);
 856
 857         if (!__vgic_v3_get_group(vcpu))
 858                 __vgic_v3_write_ap0rn(val, n);
 859         else
 860                 __vgic_v3_write_ap1rn(val, n);
 861 }
 862
 863 static void __hyp_text __vgic_v3_read_apxr0(struct kvm_vcpu *vcpu,
 864                                             u32 vmcr, int rt)
 865 {
 866         __vgic_v3_read_apxrn(vcpu, rt, 0);
 867 }
 868
 869 static void __hyp_text __vgic_v3_read_apxr1(struct kvm_vcpu *vcpu,
 870                                             u32 vmcr, int rt)
 871 {
 872         __vgic_v3_read_apxrn(vcpu, rt, 1);
 873 }
 874
 875 static void __hyp_text __vgic_v3_read_apxr2(struct kvm_vcpu *vcpu,
 876                                             u32 vmcr, int rt)
 877 {
 878         __vgic_v3_read_apxrn(vcpu, rt, 2);
 879 }
 880
 881 static void __hyp_text __vgic_v3_read_apxr3(struct kvm_vcpu *vcpu,
 882                                             u32 vmcr, int rt)
 883 {
 884         __vgic_v3_read_apxrn(vcpu, rt, 3);
 885 }
 886
 887 static void __hyp_text __vgic_v3_write_apxr0(struct kvm_vcpu *vcpu,
 888                                              u32 vmcr, int rt)
 889 {
 890         __vgic_v3_write_apxrn(vcpu, rt, 0);
 891 }
 892
 893 static void __hyp_text __vgic_v3_write_apxr1(struct kvm_vcpu *vcpu,
 894                                              u32 vmcr, int rt)
 895 {
 896         __vgic_v3_write_apxrn(vcpu, rt, 1);
 897 }
 898
 899 static void __hyp_text __vgic_v3_write_apxr2(struct kvm_vcpu *vcpu,
 900                                              u32 vmcr, int rt)
 901 {
 902         __vgic_v3_write_apxrn(vcpu, rt, 2);
 903 }
 904
 905 static void __hyp_text __vgic_v3_write_apxr3(struct kvm_vcpu *vcpu,
 906                                              u32 vmcr, int rt)
 907 {
 908         __vgic_v3_write_apxrn(vcpu, rt, 3);
 909 }
 910
 911 static void __hyp_text __vgic_v3_read_hppir(struct kvm_vcpu *vcpu,
 912                                             u32 vmcr, int rt)
 913 {
 914         u64 lr_val;
 915         int lr, lr_grp, grp;
 916
 917         grp = __vgic_v3_get_group(vcpu);
 918
 919         lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
 920         if (lr == -1)
 921                 goto spurious;
 922
 923         lr_grp = !!(lr_val & ICH_LR_GROUP);
 924         if (lr_grp != grp)
 925                 lr_val = ICC_IAR1_EL1_SPURIOUS;
 926
 927 spurious:
 928         vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
 929 }
 930
 931 static void __hyp_text __vgic_v3_read_pmr(struct kvm_vcpu *vcpu,
 932                                           u32 vmcr, int rt)
 933 {
 934         vmcr &= ICH_VMCR_PMR_MASK;
 935         vmcr >>= ICH_VMCR_PMR_SHIFT;
 936         vcpu_set_reg(vcpu, rt, vmcr);
 937 }
 938
 939 static void __hyp_text __vgic_v3_write_pmr(struct kvm_vcpu *vcpu,
 940                                            u32 vmcr, int rt)
 941 {
 942         u32 val = vcpu_get_reg(vcpu, rt);
 943
 944         val <<= ICH_VMCR_PMR_SHIFT;
 945         val &= ICH_VMCR_PMR_MASK;
 946         vmcr &= ~ICH_VMCR_PMR_MASK;
 947         vmcr |= val;
 948
 949         write_gicreg(vmcr, ICH_VMCR_EL2);
 950 }
 951
 952 static void __hyp_text __vgic_v3_read_rpr(struct kvm_vcpu *vcpu,
 953                                           u32 vmcr, int rt)
 954 {
 955         u32 val = __vgic_v3_get_highest_active_priority();
 956         vcpu_set_reg(vcpu, rt, val);
 957 }
 958
 959 static void __hyp_text __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu,
 960                                            u32 vmcr, int rt)
 961 {
 962         u32 vtr, val;
 963
 964         vtr = read_gicreg(ICH_VTR_EL2);
 965         /* PRIbits */
 966         val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
 967         /* IDbits */
 968         val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
 969         /* SEIS */
 970         val |= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT;
 971         /* A3V */
 972         val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
 973         /* EOImode */
 974         val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
 975         /* CBPR */
 976         val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 977
 978         vcpu_set_reg(vcpu, rt, val);
 979 }
 980
 981 static void __hyp_text __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu,
 982                                             u32 vmcr, int rt)
 983 {
 984         u32 val = vcpu_get_reg(vcpu, rt);
 985
 986         if (val & ICC_CTLR_EL1_CBPR_MASK)
 987                 vmcr |= ICH_VMCR_CBPR_MASK;
 988         else
 989                 vmcr &= ~ICH_VMCR_CBPR_MASK;
 990
 991         if (val & ICC_CTLR_EL1_EOImode_MASK)
 992                 vmcr |= ICH_VMCR_EOIM_MASK;
 993         else
 994                 vmcr &= ~ICH_VMCR_EOIM_MASK;
 995
 996         write_gicreg(vmcr, ICH_VMCR_EL2);
 997 }
 998
 999 int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
1000 {
1001         int rt;
1002         u32 esr;
1003         u32 vmcr;
1004         void (*fn)(struct kvm_vcpu *, u32, int);
1005         bool is_read;
1006         u32 sysreg;
1007
1008         esr = kvm_vcpu_get_hsr(vcpu);
1009         if (vcpu_mode_is_32bit(vcpu)) {
1010                 if (!kvm_condition_valid(vcpu)) {
1011                         __kvm_skip_instr(vcpu);
1012                         return 1;
1013                 }
1014
1015                 sysreg = esr_cp15_to_sysreg(esr);
1016         } else {
1017                 sysreg = esr_sys64_to_sysreg(esr);
1018         }
1019
1020         is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
1021
1022         switch (sysreg) {
1023         case SYS_ICC_IAR0_EL1:
1024         case SYS_ICC_IAR1_EL1:
1025                 if (unlikely(!is_read))
1026                         return 0;
1027                 fn = __vgic_v3_read_iar;
1028                 break;
1029         case SYS_ICC_EOIR0_EL1:
1030         case SYS_ICC_EOIR1_EL1:
1031                 if (unlikely(is_read))
1032                         return 0;
1033                 fn = __vgic_v3_write_eoir;
1034                 break;
1035         case SYS_ICC_IGRPEN1_EL1:
1036                 if (is_read)
1037                         fn = __vgic_v3_read_igrpen1;
1038                 else
1039                         fn = __vgic_v3_write_igrpen1;
1040                 break;
1041         case SYS_ICC_BPR1_EL1:
1042                 if (is_read)
1043                         fn = __vgic_v3_read_bpr1;
1044                 else
1045                         fn = __vgic_v3_write_bpr1;
1046                 break;
1047         case SYS_ICC_AP0Rn_EL1(0):
1048         case SYS_ICC_AP1Rn_EL1(0):
1049                 if (is_read)
1050                         fn = __vgic_v3_read_apxr0;
1051                 else
1052                         fn = __vgic_v3_write_apxr0;
1053                 break;
1054         case SYS_ICC_AP0Rn_EL1(1):
1055         case SYS_ICC_AP1Rn_EL1(1):
1056                 if (is_read)
1057                         fn = __vgic_v3_read_apxr1;
1058                 else
1059                         fn = __vgic_v3_write_apxr1;
1060                 break;
1061         case SYS_ICC_AP0Rn_EL1(2):
1062         case SYS_ICC_AP1Rn_EL1(2):
1063                 if (is_read)
1064                         fn = __vgic_v3_read_apxr2;
1065                 else
1066                         fn = __vgic_v3_write_apxr2;
1067                 break;
1068         case SYS_ICC_AP0Rn_EL1(3):
1069         case SYS_ICC_AP1Rn_EL1(3):
1070                 if (is_read)
1071                         fn = __vgic_v3_read_apxr3;
1072                 else
1073                         fn = __vgic_v3_write_apxr3;
1074                 break;
1075         case SYS_ICC_HPPIR0_EL1:
1076         case SYS_ICC_HPPIR1_EL1:
1077                 if (unlikely(!is_read))
1078                         return 0;
1079                 fn = __vgic_v3_read_hppir;
1080                 break;
1081         case SYS_ICC_IGRPEN0_EL1:
1082                 if (is_read)
1083                         fn = __vgic_v3_read_igrpen0;
1084                 else
1085                         fn = __vgic_v3_write_igrpen0;
1086                 break;
1087         case SYS_ICC_BPR0_EL1:
1088                 if (is_read)
1089                         fn = __vgic_v3_read_bpr0;
1090                 else
1091                         fn = __vgic_v3_write_bpr0;
1092                 break;
1093         case SYS_ICC_DIR_EL1:
1094                 if (unlikely(is_read))
1095                         return 0;
1096                 fn = __vgic_v3_write_dir;
1097                 break;
1098         case SYS_ICC_RPR_EL1:
1099                 if (unlikely(!is_read))
1100                         return 0;
1101                 fn = __vgic_v3_read_rpr;
1102                 break;
1103         case SYS_ICC_CTLR_EL1:
1104                 if (is_read)
1105                         fn = __vgic_v3_read_ctlr;
1106                 else
1107                         fn = __vgic_v3_write_ctlr;
1108                 break;
1109         case SYS_ICC_PMR_EL1:
1110                 if (is_read)
1111                         fn = __vgic_v3_read_pmr;
1112                 else
1113                         fn = __vgic_v3_write_pmr;
1114                 break;
1115         default:
1116                 return 0;
1117         }
1118
1119         vmcr = __vgic_v3_read_vmcr();
1120         rt = kvm_vcpu_sys_get_rt(vcpu);
1121         fn(vcpu, vmcr, rt);
1122
1123         __kvm_skip_instr(vcpu);
1124
1125         return 1;
1126 }