arch/arm64/kvm/hyp/nvhe/switch.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <hyp/switch.h>
   8 #include <hyp/sysreg-sr.h>
   9
  10 #include <linux/arm-smccc.h>
  11 #include <linux/kvm_host.h>
  12 #include <linux/types.h>
  13 #include <linux/jump_label.h>
  14 #include <uapi/linux/psci.h>
  15
  16 #include <kvm/arm_psci.h>
  17
  18 #include <asm/barrier.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/kprobes.h>
  21 #include <asm/kvm_asm.h>
  22 #include <asm/kvm_emulate.h>
  23 #include <asm/kvm_hyp.h>
  24 #include <asm/kvm_mmu.h>
  25 #include <asm/fpsimd.h>
  26 #include <asm/debug-monitors.h>
  27 #include <asm/processor.h>
  28 #include <asm/thread_info.h>
  29
  30 #include <nvhe/mem_protect.h>
  31
  32 /* Non-VHE specific context */
  33 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
  34 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
  35 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
  36
  37 static void __activate_traps(struct kvm_vcpu *vcpu)
  38 {
  39         u64 val;
  40
  41         ___activate_traps(vcpu);
  42         __activate_traps_common(vcpu);
  43
  44         val = CPTR_EL2_DEFAULT;
  45         val |= CPTR_EL2_TTA | CPTR_EL2_TAM;
  46         if (!update_fp_enabled(vcpu)) {
  47                 val |= CPTR_EL2_TFP | CPTR_EL2_TZ;
  48                 __activate_traps_fpsimd32(vcpu);
  49         }
  50
  51         write_sysreg(val, cptr_el2);
  52         write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2);
  53
  54         if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
  55                 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
  56
  57                 isb();
  58                 /*
  59                  * At this stage, and thanks to the above isb(), S2 is
  60                  * configured and enabled. We can now restore the guest's S1
  61                  * configuration: SCTLR, and only then TCR.
  62                  */
  63                 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
  64                 isb();
  65                 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1),   SYS_TCR);
  66         }
  67 }
  68
  69 static void __deactivate_traps(struct kvm_vcpu *vcpu)
  70 {
  71         extern char __kvm_hyp_host_vector[];
  72         u64 mdcr_el2, cptr;
  73
  74         ___deactivate_traps(vcpu);
  75
  76         mdcr_el2 = read_sysreg(mdcr_el2);
  77
  78         if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
  79                 u64 val;
  80
  81                 /*
  82                  * Set the TCR and SCTLR registers in the exact opposite
  83                  * sequence as __activate_traps (first prevent walks,
  84                  * then force the MMU on). A generous sprinkling of isb()
  85                  * ensure that things happen in this exact order.
  86                  */
  87                 val = read_sysreg_el1(SYS_TCR);
  88                 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR);
  89                 isb();
  90                 val = read_sysreg_el1(SYS_SCTLR);
  91                 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR);
  92                 isb();
  93         }
  94
  95         __deactivate_traps_common();
  96
  97         mdcr_el2 &= MDCR_EL2_HPMN_MASK;
  98         mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
  99         mdcr_el2 |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT;
 100
 101         write_sysreg(mdcr_el2, mdcr_el2);
 102         write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2);
 103
 104         cptr = CPTR_EL2_DEFAULT;
 105         if (vcpu_has_sve(vcpu) && (vcpu->arch.flags & KVM_ARM64_FP_ENABLED))
 106                 cptr |= CPTR_EL2_TZ;
 107
 108         write_sysreg(cptr, cptr_el2);
 109         write_sysreg(__kvm_hyp_host_vector, vbar_el2);
 110 }
 111
 112 /* Save VGICv3 state on non-VHE systems */
 113 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
 114 {
 115         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 116                 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3);
 117                 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
 118         }
 119 }
 120
 121 /* Restore VGICv3 state on non_VEH systems */
 122 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
 123 {
 124         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 125                 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3);
 126                 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3);
 127         }
 128 }
 129
 130 /**
 131  * Disable host events, enable guest events
 132  */
 133 static bool __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
 134 {
 135         struct kvm_host_data *host;
 136         struct kvm_pmu_events *pmu;
 137
 138         host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
 139         pmu = &host->pmu_events;
 140
 141         if (pmu->events_host)
 142                 write_sysreg(pmu->events_host, pmcntenclr_el0);
 143
 144         if (pmu->events_guest)
 145                 write_sysreg(pmu->events_guest, pmcntenset_el0);
 146
 147         return (pmu->events_host || pmu->events_guest);
 148 }
 149
 150 /**
 151  * Disable guest events, enable host events
 152  */
 153 static void __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
 154 {
 155         struct kvm_host_data *host;
 156         struct kvm_pmu_events *pmu;
 157
 158         host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
 159         pmu = &host->pmu_events;
 160
 161         if (pmu->events_guest)
 162                 write_sysreg(pmu->events_guest, pmcntenclr_el0);
 163
 164         if (pmu->events_host)
 165                 write_sysreg(pmu->events_host, pmcntenset_el0);
 166 }
 167
 168 /* Switch to the guest for legacy non-VHE systems */
 169 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 170 {
 171         struct kvm_cpu_context *host_ctxt;
 172         struct kvm_cpu_context *guest_ctxt;
 173         struct kvm_s2_mmu *mmu;
 174         bool pmu_switch_needed;
 175         u64 exit_code;
 176
 177         /*
 178          * Having IRQs masked via PMR when entering the guest means the GIC
 179          * will not signal the CPU of interrupts of lower priority, and the
 180          * only way to get out will be via guest exceptions.
 181          * Naturally, we want to avoid this.
 182          */
 183         if (system_uses_irq_prio_masking()) {
 184                 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET);
 185                 pmr_sync();
 186         }
 187
 188         host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
 189         host_ctxt->__hyp_running_vcpu = vcpu;
 190         guest_ctxt = &vcpu->arch.ctxt;
 191
 192         pmu_switch_needed = __pmu_switch_to_guest(host_ctxt);
 193
 194         __sysreg_save_state_nvhe(host_ctxt);
 195         /*
 196          * We must flush and disable the SPE buffer for nVHE, as
 197          * the translation regime(EL1&0) is going to be loaded with
 198          * that of the guest. And we must do this before we change the
 199          * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and
 200          * before we load guest Stage1.
 201          */
 202         __debug_save_host_buffers_nvhe(vcpu);
 203
 204         __kvm_adjust_pc(vcpu);
 205
 206         /*
 207          * We must restore the 32-bit state before the sysregs, thanks
 208          * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
 209          *
 210          * Also, and in order to be able to deal with erratum #1319537 (A57)
 211          * and #1319367 (A72), we must ensure that all VM-related sysreg are
 212          * restored before we enable S2 translation.
 213          */
 214         __sysreg32_restore_state(vcpu);
 215         __sysreg_restore_state_nvhe(guest_ctxt);
 216
 217         mmu = kern_hyp_va(vcpu->arch.hw_mmu);
 218         __load_stage2(mmu, kern_hyp_va(mmu->arch));
 219         __activate_traps(vcpu);
 220
 221         __hyp_vgic_restore_state(vcpu);
 222         __timer_enable_traps(vcpu);
 223
 224         __debug_switch_to_guest(vcpu);
 225
 226         do {
 227                 /* Jump in the fire! */
 228                 exit_code = __guest_enter(vcpu);
 229
 230                 /* And we're baaack! */
 231         } while (fixup_guest_exit(vcpu, &exit_code));
 232
 233         __sysreg_save_state_nvhe(guest_ctxt);
 234         __sysreg32_save_state(vcpu);
 235         __timer_disable_traps(vcpu);
 236         __hyp_vgic_save_state(vcpu);
 237
 238         __deactivate_traps(vcpu);
 239         __load_host_stage2();
 240
 241         __sysreg_restore_state_nvhe(host_ctxt);
 242
 243         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 244                 __fpsimd_save_fpexc32(vcpu);
 245
 246         __debug_switch_to_host(vcpu);
 247         /*
 248          * This must come after restoring the host sysregs, since a non-VHE
 249          * system may enable SPE here and make use of the TTBRs.
 250          */
 251         __debug_restore_host_buffers_nvhe(vcpu);
 252
 253         if (pmu_switch_needed)
 254                 __pmu_switch_to_host(host_ctxt);
 255
 256         /* Returning to host will clear PSR.I, remask PMR if needed */
 257         if (system_uses_irq_prio_masking())
 258                 gic_write_pmr(GIC_PRIO_IRQOFF);
 259
 260         host_ctxt->__hyp_running_vcpu = NULL;
 261
 262         return exit_code;
 263 }
 264
 265 void __noreturn hyp_panic(void)
 266 {
 267         u64 spsr = read_sysreg_el2(SYS_SPSR);
 268         u64 elr = read_sysreg_el2(SYS_ELR);
 269         u64 par = read_sysreg_par();
 270         struct kvm_cpu_context *host_ctxt;
 271         struct kvm_vcpu *vcpu;
 272
 273         host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
 274         vcpu = host_ctxt->__hyp_running_vcpu;
 275
 276         if (vcpu) {
 277                 __timer_disable_traps(vcpu);
 278                 __deactivate_traps(vcpu);
 279                 __load_host_stage2();
 280                 __sysreg_restore_state_nvhe(host_ctxt);
 281         }
 282
 283         __hyp_do_panic(host_ctxt, spsr, elr, par);
 284         unreachable();
 285 }
 286
 287 asmlinkage void kvm_unexpected_el2_exception(void)
 288 {
 289         return __kvm_unexpected_el2_exception();
 290 }